1 /*- 2 * Copyright (c) 2013, 2014 Andrew Turner 3 * Copyright (c) 2015,2021 The FreeBSD Foundation 4 * 5 * Portions of this software were developed by Andrew Turner 6 * under sponsorship from the FreeBSD Foundation. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #if !defined(_MACHINE_ARMREG_H_) && \ 31 !defined(_MACHINE_CPU_H_) && \ 32 !defined(_MACHINE_HYPERVISOR_H_) && \ 33 !defined(_MACHINE_SYSINSN_H_) 34 #error Do not include this file directly 35 #endif 36 37 #ifndef _MACHINE__ARMREG_H_ 38 #define _MACHINE__ARMREG_H_ 39 40 #define __MRS_REG_ALT_NAME(op0, op1, crn, crm, op2) \ 41 S##op0##_##op1##_C##crn##_C##crm##_##op2 42 #define _MRS_REG_ALT_NAME(op0, op1, crn, crm, op2) \ 43 __MRS_REG_ALT_NAME(op0, op1, crn, crm, op2) 44 #define MRS_REG_ALT_NAME(reg) \ 45 _MRS_REG_ALT_NAME(reg##_op0, reg##_op1, reg##_CRn, reg##_CRm, reg##_op2) 46 47 48 #define READ_SPECIALREG(reg) \ 49 ({ uint64_t _val; \ 50 __asm __volatile("mrs %0, " __STRING(reg) : "=&r" (_val)); \ 51 _val; \ 52 }) 53 #define WRITE_SPECIALREG(reg, _val) \ 54 __asm __volatile("msr " __STRING(reg) ", %0" : : "r"((uint64_t)_val)) 55 56 57 #define __SYS_ALT_NAME(op1, crn, crm, op2) \ 58 "#" #op1 ", C" #crn ", C" #crm ", #" #op2 59 #define _SYS_ALT_NAME(op1, crn, crm, op2) \ 60 __SYS_ALT_NAME(op1, crn, crm, op2) 61 #define SYS_ALT_NAME(insn) \ 62 _SYS_ALT_NAME(insn##_op1, insn##_CRn, insn##_CRm, insn##_op2) 63 64 #define SYS(insn) do { \ 65 _Static_assert(insn##_op0 == 1, "Invalid SYS instruction"); \ 66 __asm __volatile("sys " SYS_ALT_NAME(insn)); \ 67 } while (0) 68 69 #define SYS_ARG(insn, _val) do { \ 70 _Static_assert(insn##_op0 == 1, "Invalid SYS instruction"); \ 71 __asm __volatile("sys " SYS_ALT_NAME(insn) ", %0" \ 72 : : "r"((uint64_t)_val)); \ 73 } while (0) 74 75 #define SYSL(insn) \ 76 ({ \ 77 uint64_t _val; \ 78 _Static_assert(insn##_op0 == 1, "Invalid SYS instruction"); \ 79 __asm __volatile("sysl %0, " SYS_ALT_NAME(insn) \ 80 : "=&r"(_val)); \ 81 _val; \ 82 }) 83 84 /* TODO: Use CNTPCTSS when FEAT_ECV is available */ 85 #define READ_CNTPCT() \ 86 ({ uint64_t _val; \ 87 __asm __volatile("isb\nmrs %0, cntpct_el0" : "=&r" (_val));\ 88 _val; \ 89 }) 90 91 #define UL(x) UINT64_C(x) 92 93 #endif /* !_MACHINE__ARMREG_H_ */ 94