1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2020 Oleksandr Tymoshenko <gonzo@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29 #ifndef __IMX8MQ_CCM_H__ 30 #define __IMX8MQ_CCM_H__ 31 32 #define IMX8MQ_CLK_DUMMY 0 33 #define IMX8MQ_CLK_32K 1 34 #define IMX8MQ_CLK_25M 2 35 #define IMX8MQ_CLK_27M 3 36 #define IMX8MQ_CLK_EXT1 4 37 #define IMX8MQ_CLK_EXT2 5 38 #define IMX8MQ_CLK_EXT3 6 39 #define IMX8MQ_CLK_EXT4 7 40 41 #define IMX8MQ_ARM_PLL_REF_SEL 8 42 #define IMX8MQ_ARM_PLL_REF_DIV 9 43 #define IMX8MQ_ARM_PLL 10 44 #define IMX8MQ_ARM_PLL_BYPASS 11 45 #define IMX8MQ_ARM_PLL_OUT 12 46 47 #define IMX8MQ_GPU_PLL_REF_SEL 13 48 #define IMX8MQ_GPU_PLL_REF_DIV 14 49 #define IMX8MQ_GPU_PLL 15 50 #define IMX8MQ_GPU_PLL_BYPASS 16 51 #define IMX8MQ_GPU_PLL_OUT 17 52 53 #define IMX8MQ_VPU_PLL_REF_SEL 18 54 #define IMX8MQ_VPU_PLL_REF_DIV 19 55 #define IMX8MQ_VPU_PLL 20 56 #define IMX8MQ_VPU_PLL_BYPASS 21 57 #define IMX8MQ_VPU_PLL_OUT 22 58 59 #define IMX8MQ_AUDIO_PLL1_REF_SEL 23 60 #define IMX8MQ_AUDIO_PLL1_REF_DIV 24 61 #define IMX8MQ_AUDIO_PLL1 25 62 #define IMX8MQ_AUDIO_PLL1_BYPASS 26 63 #define IMX8MQ_AUDIO_PLL1_OUT 27 64 65 #define IMX8MQ_AUDIO_PLL2_REF_SEL 28 66 #define IMX8MQ_AUDIO_PLL2_REF_DIV 29 67 #define IMX8MQ_AUDIO_PLL2 30 68 #define IMX8MQ_AUDIO_PLL2_BYPASS 31 69 #define IMX8MQ_AUDIO_PLL2_OUT 32 70 71 #define IMX8MQ_VIDEO_PLL1_REF_SEL 33 72 #define IMX8MQ_VIDEO_PLL1_REF_DIV 34 73 #define IMX8MQ_VIDEO_PLL1 35 74 #define IMX8MQ_VIDEO_PLL1_BYPASS 36 75 #define IMX8MQ_VIDEO_PLL1_OUT 37 76 77 #define IMX8MQ_SYS3_PLL1_REF_SEL 54 78 #define IMX8MQ_SYS3_PLL1 56 79 80 #define IMX8MQ_DRAM_PLL1_REF_SEL 62 81 82 #define IMX8MQ_SYS1_PLL_40M 70 83 #define IMX8MQ_SYS1_PLL_80M 71 84 #define IMX8MQ_SYS1_PLL_100M 72 85 #define IMX8MQ_SYS1_PLL_133M 73 86 #define IMX8MQ_SYS1_PLL_160M 74 87 #define IMX8MQ_SYS1_PLL_200M 75 88 #define IMX8MQ_SYS1_PLL_266M 76 89 #define IMX8MQ_SYS1_PLL_400M 77 90 #define IMX8MQ_SYS1_PLL_800M 78 91 92 #define IMX8MQ_SYS2_PLL_50M 79 93 #define IMX8MQ_SYS2_PLL_100M 80 94 #define IMX8MQ_SYS2_PLL_125M 81 95 #define IMX8MQ_SYS2_PLL_166M 82 96 #define IMX8MQ_SYS2_PLL_200M 83 97 #define IMX8MQ_SYS2_PLL_250M 84 98 #define IMX8MQ_SYS2_PLL_333M 85 99 #define IMX8MQ_SYS2_PLL_500M 86 100 #define IMX8MQ_SYS2_PLL_1000M 87 101 102 #define IMX8MQ_CLK_ENET_AXI 104 103 #define IMX8MQ_CLK_USB_BUS 110 104 105 #define IMX8MQ_CLK_AHB 116 106 107 #define IMX8MQ_CLK_ENET_REF 137 108 #define IMX8MQ_CLK_ENET_TIMER 138 109 #define IMX8MQ_CLK_ENET_PHY_REF 139 110 #define IMX8MQ_CLK_USDHC1 142 111 #define IMX8MQ_CLK_USDHC2 143 112 #define IMX8MQ_CLK_I2C1 144 113 #define IMX8MQ_CLK_I2C2 145 114 #define IMX8MQ_CLK_I2C3 146 115 #define IMX8MQ_CLK_I2C4 147 116 #define IMX8MQ_CLK_UART1 148 117 #define IMX8MQ_CLK_UART2 149 118 #define IMX8MQ_CLK_UART3 150 119 #define IMX8MQ_CLK_UART4 151 120 #define IMX8MQ_CLK_USB_CORE_REF 152 121 #define IMX8MQ_CLK_USB_PHY_REF 153 122 123 #define IMX8MQ_CLK_ENET1_ROOT 182 124 #define IMX8MQ_CLK_I2C1_ROOT 184 125 #define IMX8MQ_CLK_I2C2_ROOT 185 126 #define IMX8MQ_CLK_I2C3_ROOT 186 127 #define IMX8MQ_CLK_I2C4_ROOT 187 128 #define IMX8MQ_CLK_UART1_ROOT 202 129 #define IMX8MQ_CLK_UART2_ROOT 203 130 #define IMX8MQ_CLK_UART3_ROOT 204 131 #define IMX8MQ_CLK_UART4_ROOT 205 132 #define IMX8MQ_CLK_USB1_CTRL_ROOT 206 133 #define IMX8MQ_CLK_USB2_CTRL_ROOT 207 134 #define IMX8MQ_CLK_USB1_PHY_ROOT 208 135 #define IMX8MQ_CLK_USB2_PHY_ROOT 209 136 #define IMX8MQ_CLK_USDHC1_ROOT 210 137 #define IMX8MQ_CLK_USDHC2_ROOT 211 138 139 #define IMX8MQ_SYS1_PLL_OUT 231 140 #define IMX8MQ_SYS2_PLL_OUT 232 141 #define IMX8MQ_SYS3_PLL_OUT 233 142 143 #define IMX8MQ_CLK_IPG_ROOT 236 144 145 #define IMX8MQ_CLK_TMU_ROOT 246 146 147 #define IMX8MQ_CLK_GPIO1_ROOT 259 148 #define IMX8MQ_CLK_GPIO2_ROOT 260 149 #define IMX8MQ_CLK_GPIO3_ROOT 261 150 #define IMX8MQ_CLK_GPIO4_ROOT 262 151 #define IMX8MQ_CLK_GPIO5_ROOT 263 152 153 #define IMX8MQ_VIDEO2_PLL1_REF_SEL 266 154 155 #define IMX8MQ_SYS1_PLL_40M_CG 267 156 #define IMX8MQ_SYS1_PLL_80M_CG 268 157 #define IMX8MQ_SYS1_PLL_100M_CG 269 158 #define IMX8MQ_SYS1_PLL_133M_CG 270 159 #define IMX8MQ_SYS1_PLL_160M_CG 271 160 #define IMX8MQ_SYS1_PLL_200M_CG 272 161 #define IMX8MQ_SYS1_PLL_266M_CG 273 162 #define IMX8MQ_SYS1_PLL_400M_CG 274 163 #define IMX8MQ_SYS1_PLL_800M_CG 275 164 #define IMX8MQ_SYS2_PLL_50M_CG 276 165 #define IMX8MQ_SYS2_PLL_100M_CG 277 166 #define IMX8MQ_SYS2_PLL_125M_CG 278 167 #define IMX8MQ_SYS2_PLL_166M_CG 279 168 #define IMX8MQ_SYS2_PLL_200M_CG 280 169 #define IMX8MQ_SYS2_PLL_250M_CG 281 170 #define IMX8MQ_SYS2_PLL_333M_CG 282 171 #define IMX8MQ_SYS2_PLL_500M_CG 283 172 #define IMX8MQ_SYS2_PLL_1000M_CG 284 173 174 #endif 175