1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2020 Oleksandr Tymoshenko <gonzo@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/bus.h> 32 #include <sys/kernel.h> 33 #include <sys/module.h> 34 #include <sys/rman.h> 35 #include <sys/proc.h> 36 #include <sys/lock.h> 37 #include <sys/mutex.h> 38 39 #include <machine/bus.h> 40 #include <machine/intr.h> 41 42 #include <dev/ofw/openfirm.h> 43 #include <dev/ofw/ofw_bus.h> 44 #include <dev/ofw/ofw_bus_subr.h> 45 46 #include "pic_if.h" 47 48 struct imx7gpc_softc { 49 device_t dev; 50 struct resource *memres; 51 device_t parent; 52 }; 53 54 static struct ofw_compat_data compat_data[] = { 55 { "fsl,imx7gpc", 1}, 56 { "fsl,imx8mq-gpc", 1}, 57 { NULL, 0} 58 }; 59 60 static int 61 imx7gpc_activate_intr(device_t dev, struct intr_irqsrc *isrc, 62 struct resource *res, struct intr_map_data *data) 63 { 64 struct imx7gpc_softc *sc = device_get_softc(dev); 65 66 return (PIC_ACTIVATE_INTR(sc->parent, isrc, res, data)); 67 } 68 69 static void 70 imx7gpc_disable_intr(device_t dev, struct intr_irqsrc *isrc) 71 { 72 struct imx7gpc_softc *sc = device_get_softc(dev); 73 74 PIC_DISABLE_INTR(sc->parent, isrc); 75 } 76 77 static void 78 imx7gpc_enable_intr(device_t dev, struct intr_irqsrc *isrc) 79 { 80 struct imx7gpc_softc *sc = device_get_softc(dev); 81 82 PIC_ENABLE_INTR(sc->parent, isrc); 83 } 84 85 static int 86 imx7gpc_map_intr(device_t dev, struct intr_map_data *data, 87 struct intr_irqsrc **isrcp) 88 { 89 struct imx7gpc_softc *sc = device_get_softc(dev); 90 91 return (PIC_MAP_INTR(sc->parent, data, isrcp)); 92 } 93 94 static int 95 imx7gpc_deactivate_intr(device_t dev, struct intr_irqsrc *isrc, 96 struct resource *res, struct intr_map_data *data) 97 { 98 struct imx7gpc_softc *sc = device_get_softc(dev); 99 100 return (PIC_DEACTIVATE_INTR(sc->parent, isrc, res, data)); 101 } 102 103 static int 104 imx7gpc_setup_intr(device_t dev, struct intr_irqsrc *isrc, 105 struct resource *res, struct intr_map_data *data) 106 { 107 struct imx7gpc_softc *sc = device_get_softc(dev); 108 109 return (PIC_SETUP_INTR(sc->parent, isrc, res, data)); 110 } 111 112 static int 113 imx7gpc_teardown_intr(device_t dev, struct intr_irqsrc *isrc, 114 struct resource *res, struct intr_map_data *data) 115 { 116 struct imx7gpc_softc *sc = device_get_softc(dev); 117 118 return (PIC_TEARDOWN_INTR(sc->parent, isrc, res, data)); 119 } 120 121 static void 122 imx7gpc_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 123 { 124 struct imx7gpc_softc *sc = device_get_softc(dev); 125 126 PIC_PRE_ITHREAD(sc->parent, isrc); 127 } 128 129 static void 130 imx7gpc_post_ithread(device_t dev, struct intr_irqsrc *isrc) 131 { 132 struct imx7gpc_softc *sc = device_get_softc(dev); 133 134 PIC_POST_ITHREAD(sc->parent, isrc); 135 } 136 137 static void 138 imx7gpc_post_filter(device_t dev, struct intr_irqsrc *isrc) 139 { 140 struct imx7gpc_softc *sc = device_get_softc(dev); 141 142 PIC_POST_FILTER(sc->parent, isrc); 143 } 144 145 #ifdef SMP 146 static int 147 imx7gpc_bind_intr(device_t dev, struct intr_irqsrc *isrc) 148 { 149 struct imx7gpc_softc *sc = device_get_softc(dev); 150 151 return (PIC_BIND_INTR(sc->parent, isrc)); 152 } 153 #endif 154 155 static int 156 imx7gpc_probe(device_t dev) 157 { 158 159 if (!ofw_bus_status_okay(dev)) 160 return (ENXIO); 161 162 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 163 return (ENXIO); 164 165 device_set_desc(dev, "General Power Controller"); 166 return (BUS_PROBE_DEFAULT); 167 } 168 169 static int 170 imx7gpc_attach(device_t dev) 171 { 172 struct imx7gpc_softc *sc = device_get_softc(dev); 173 phandle_t node; 174 phandle_t parent_xref; 175 int i, rv; 176 177 sc->dev = dev; 178 179 node = ofw_bus_get_node(dev); 180 181 rv = OF_getencprop(node, "interrupt-parent", &parent_xref, 182 sizeof(parent_xref)); 183 if (rv <= 0) { 184 device_printf(dev, "Can't read parent node property\n"); 185 return (ENXIO); 186 } 187 sc->parent = OF_device_from_xref(parent_xref); 188 if (sc->parent == NULL) { 189 device_printf(dev, "Can't find parent controller\n"); 190 return (ENXIO); 191 } 192 193 i = 0; 194 sc->memres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &i, 195 RF_ACTIVE); 196 if (sc->memres == NULL) { 197 device_printf(dev, "could not allocate resources\n"); 198 return (ENXIO); 199 } 200 201 /* TODO: power up OTG domain and unmask all interrupts */ 202 203 if (intr_pic_register(dev, OF_xref_from_node(node)) == NULL) { 204 bus_release_resource(dev, SYS_RES_MEMORY, i, sc->memres); 205 device_printf(dev, "Cannot register PIC\n"); 206 return (ENXIO); 207 } 208 209 return (0); 210 } 211 212 static device_method_t imx7gpc_methods[] = { 213 DEVMETHOD(device_probe, imx7gpc_probe), 214 DEVMETHOD(device_attach, imx7gpc_attach), 215 216 /* Interrupt controller interface */ 217 DEVMETHOD(pic_activate_intr, imx7gpc_activate_intr), 218 DEVMETHOD(pic_disable_intr, imx7gpc_disable_intr), 219 DEVMETHOD(pic_enable_intr, imx7gpc_enable_intr), 220 DEVMETHOD(pic_map_intr, imx7gpc_map_intr), 221 DEVMETHOD(pic_deactivate_intr, imx7gpc_deactivate_intr), 222 DEVMETHOD(pic_setup_intr, imx7gpc_setup_intr), 223 DEVMETHOD(pic_teardown_intr, imx7gpc_teardown_intr), 224 DEVMETHOD(pic_pre_ithread, imx7gpc_pre_ithread), 225 DEVMETHOD(pic_post_ithread, imx7gpc_post_ithread), 226 DEVMETHOD(pic_post_filter, imx7gpc_post_filter), 227 #ifdef SMP 228 DEVMETHOD(pic_bind_intr, imx7gpc_bind_intr), 229 #endif 230 231 DEVMETHOD_END 232 }; 233 234 static driver_t imx7gpc_driver = { 235 "imx7gpc", 236 imx7gpc_methods, 237 sizeof(struct imx7gpc_softc), 238 }; 239 240 EARLY_DRIVER_MODULE(imx7gpc, ofwbus, imx7gpc_driver, 0, 0, 241 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE); 242 EARLY_DRIVER_MODULE(imx7gpc, simplebus, imx7gpc_driver, 0, 0, 243 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE); 244