1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2020 Oleksandr Tymoshenko <gonzo@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/param.h> 29 #include <sys/systm.h> 30 #include <sys/bus.h> 31 #include <sys/kernel.h> 32 #include <sys/module.h> 33 #include <sys/rman.h> 34 #include <sys/proc.h> 35 #include <sys/lock.h> 36 #include <sys/mutex.h> 37 38 #include <machine/bus.h> 39 #include <machine/intr.h> 40 41 #include <dev/ofw/openfirm.h> 42 #include <dev/ofw/ofw_bus.h> 43 #include <dev/ofw/ofw_bus_subr.h> 44 45 #include "pic_if.h" 46 47 struct imx7gpc_softc { 48 device_t dev; 49 struct resource *memres; 50 device_t parent; 51 }; 52 53 static struct ofw_compat_data compat_data[] = { 54 { "fsl,imx7gpc", 1}, 55 { "fsl,imx8mq-gpc", 1}, 56 { NULL, 0} 57 }; 58 59 static int 60 imx7gpc_activate_intr(device_t dev, struct intr_irqsrc *isrc, 61 struct resource *res, struct intr_map_data *data) 62 { 63 struct imx7gpc_softc *sc = device_get_softc(dev); 64 65 return (PIC_ACTIVATE_INTR(sc->parent, isrc, res, data)); 66 } 67 68 static void 69 imx7gpc_disable_intr(device_t dev, struct intr_irqsrc *isrc) 70 { 71 struct imx7gpc_softc *sc = device_get_softc(dev); 72 73 PIC_DISABLE_INTR(sc->parent, isrc); 74 } 75 76 static void 77 imx7gpc_enable_intr(device_t dev, struct intr_irqsrc *isrc) 78 { 79 struct imx7gpc_softc *sc = device_get_softc(dev); 80 81 PIC_ENABLE_INTR(sc->parent, isrc); 82 } 83 84 static int 85 imx7gpc_map_intr(device_t dev, struct intr_map_data *data, 86 struct intr_irqsrc **isrcp) 87 { 88 struct imx7gpc_softc *sc = device_get_softc(dev); 89 90 return (PIC_MAP_INTR(sc->parent, data, isrcp)); 91 } 92 93 static int 94 imx7gpc_deactivate_intr(device_t dev, struct intr_irqsrc *isrc, 95 struct resource *res, struct intr_map_data *data) 96 { 97 struct imx7gpc_softc *sc = device_get_softc(dev); 98 99 return (PIC_DEACTIVATE_INTR(sc->parent, isrc, res, data)); 100 } 101 102 static int 103 imx7gpc_setup_intr(device_t dev, struct intr_irqsrc *isrc, 104 struct resource *res, struct intr_map_data *data) 105 { 106 struct imx7gpc_softc *sc = device_get_softc(dev); 107 108 return (PIC_SETUP_INTR(sc->parent, isrc, res, data)); 109 } 110 111 static int 112 imx7gpc_teardown_intr(device_t dev, struct intr_irqsrc *isrc, 113 struct resource *res, struct intr_map_data *data) 114 { 115 struct imx7gpc_softc *sc = device_get_softc(dev); 116 117 return (PIC_TEARDOWN_INTR(sc->parent, isrc, res, data)); 118 } 119 120 static void 121 imx7gpc_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 122 { 123 struct imx7gpc_softc *sc = device_get_softc(dev); 124 125 PIC_PRE_ITHREAD(sc->parent, isrc); 126 } 127 128 static void 129 imx7gpc_post_ithread(device_t dev, struct intr_irqsrc *isrc) 130 { 131 struct imx7gpc_softc *sc = device_get_softc(dev); 132 133 PIC_POST_ITHREAD(sc->parent, isrc); 134 } 135 136 static void 137 imx7gpc_post_filter(device_t dev, struct intr_irqsrc *isrc) 138 { 139 struct imx7gpc_softc *sc = device_get_softc(dev); 140 141 PIC_POST_FILTER(sc->parent, isrc); 142 } 143 144 #ifdef SMP 145 static int 146 imx7gpc_bind_intr(device_t dev, struct intr_irqsrc *isrc) 147 { 148 struct imx7gpc_softc *sc = device_get_softc(dev); 149 150 return (PIC_BIND_INTR(sc->parent, isrc)); 151 } 152 #endif 153 154 static int 155 imx7gpc_probe(device_t dev) 156 { 157 158 if (!ofw_bus_status_okay(dev)) 159 return (ENXIO); 160 161 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 162 return (ENXIO); 163 164 device_set_desc(dev, "General Power Controller"); 165 return (BUS_PROBE_DEFAULT); 166 } 167 168 static int 169 imx7gpc_attach(device_t dev) 170 { 171 struct imx7gpc_softc *sc = device_get_softc(dev); 172 phandle_t node; 173 phandle_t parent_xref; 174 int i, rv; 175 176 sc->dev = dev; 177 178 node = ofw_bus_get_node(dev); 179 180 rv = OF_getencprop(node, "interrupt-parent", &parent_xref, 181 sizeof(parent_xref)); 182 if (rv <= 0) { 183 device_printf(dev, "Can't read parent node property\n"); 184 return (ENXIO); 185 } 186 sc->parent = OF_device_from_xref(parent_xref); 187 if (sc->parent == NULL) { 188 device_printf(dev, "Can't find parent controller\n"); 189 return (ENXIO); 190 } 191 192 i = 0; 193 sc->memres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &i, 194 RF_ACTIVE); 195 if (sc->memres == NULL) { 196 device_printf(dev, "could not allocate resources\n"); 197 return (ENXIO); 198 } 199 200 /* TODO: power up OTG domain and unmask all interrupts */ 201 202 if (intr_pic_register(dev, OF_xref_from_node(node)) == NULL) { 203 bus_release_resource(dev, SYS_RES_MEMORY, i, sc->memres); 204 device_printf(dev, "Cannot register PIC\n"); 205 return (ENXIO); 206 } 207 208 return (0); 209 } 210 211 static device_method_t imx7gpc_methods[] = { 212 DEVMETHOD(device_probe, imx7gpc_probe), 213 DEVMETHOD(device_attach, imx7gpc_attach), 214 215 /* Interrupt controller interface */ 216 DEVMETHOD(pic_activate_intr, imx7gpc_activate_intr), 217 DEVMETHOD(pic_disable_intr, imx7gpc_disable_intr), 218 DEVMETHOD(pic_enable_intr, imx7gpc_enable_intr), 219 DEVMETHOD(pic_map_intr, imx7gpc_map_intr), 220 DEVMETHOD(pic_deactivate_intr, imx7gpc_deactivate_intr), 221 DEVMETHOD(pic_setup_intr, imx7gpc_setup_intr), 222 DEVMETHOD(pic_teardown_intr, imx7gpc_teardown_intr), 223 DEVMETHOD(pic_pre_ithread, imx7gpc_pre_ithread), 224 DEVMETHOD(pic_post_ithread, imx7gpc_post_ithread), 225 DEVMETHOD(pic_post_filter, imx7gpc_post_filter), 226 #ifdef SMP 227 DEVMETHOD(pic_bind_intr, imx7gpc_bind_intr), 228 #endif 229 230 DEVMETHOD_END 231 }; 232 233 static driver_t imx7gpc_driver = { 234 "imx7gpc", 235 imx7gpc_methods, 236 sizeof(struct imx7gpc_softc), 237 }; 238 239 EARLY_DRIVER_MODULE(imx7gpc, ofwbus, imx7gpc_driver, 0, 0, 240 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE); 241 EARLY_DRIVER_MODULE(imx7gpc, simplebus, imx7gpc_driver, 0, 0, 242 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE); 243