1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2020 Oleksandr Tymoshenko <gonzo@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/bus.h> 32 33 #include <dev/extres/clk/clk.h> 34 35 #include <arm64/freescale/imx/clk/imx_clk_sscg_pll.h> 36 37 #include "clkdev_if.h" 38 39 struct imx_clk_sscg_pll_sc { 40 uint32_t offset; 41 }; 42 43 #define WRITE4(_clk, off, val) \ 44 CLKDEV_WRITE_4(clknode_get_device(_clk), off, val) 45 #define READ4(_clk, off, val) \ 46 CLKDEV_READ_4(clknode_get_device(_clk), off, val) 47 #define DEVICE_LOCK(_clk) \ 48 CLKDEV_DEVICE_LOCK(clknode_get_device(_clk)) 49 #define DEVICE_UNLOCK(_clk) \ 50 CLKDEV_DEVICE_UNLOCK(clknode_get_device(_clk)) 51 52 #define CFG0 0x00 53 #define CFG0_PLL_LOCK (1 << 31) 54 #define CFG0_PD (1 << 7) 55 #define CFG0_BYPASS2 (1 << 5) 56 #define CFG0_BYPASS1 (1 << 4) 57 #define CFG1 0x04 58 #define CFG2 0x08 59 #define CFG2_DIVR1_MASK (7 << 25) 60 #define CFG2_DIVR1_SHIFT 25 61 #define CFG2_DIVR2_MASK (0x3f << 19) 62 #define CFG2_DIVR2_SHIFT 19 63 #define CFG2_DIVF1_MASK (0x3f << 13) 64 #define CFG2_DIVF1_SHIFT 13 65 #define CFG2_DIVF2_MASK (0x3f << 7) 66 #define CFG2_DIVF2_SHIFT 7 67 #define CFG2_DIV_MASK (0x3f << 1) 68 #define CFG2_DIV_SHIFT 1 69 70 #if 0 71 #define dprintf(format, arg...) \ 72 printf("%s:(%s)" format, __func__, clknode_get_name(clk), arg) 73 #else 74 #define dprintf(format, arg...) 75 #endif 76 77 static int 78 imx_clk_sscg_pll_init(struct clknode *clk, device_t dev) 79 { 80 if (clknode_get_parents_num(clk) > 1) { 81 device_printf(clknode_get_device(clk), 82 "error: SSCG PLL does not support more than one parent yet\n"); 83 return (EINVAL); 84 } 85 clknode_init_parent_idx(clk, 0); 86 87 return (0); 88 } 89 90 static int 91 imx_clk_sscg_pll_set_gate(struct clknode *clk, bool enable) 92 { 93 struct imx_clk_sscg_pll_sc *sc; 94 uint32_t cfg0; 95 int timeout; 96 97 sc = clknode_get_softc(clk); 98 99 DEVICE_LOCK(clk); 100 READ4(clk, sc->offset + CFG0, &cfg0); 101 if (enable) 102 cfg0 &= ~(CFG0_PD); 103 else 104 cfg0 |= CFG0_PD; 105 WRITE4(clk, sc->offset + CFG0, cfg0); 106 107 /* Reading lock */ 108 if (enable) { 109 for (timeout = 1000; timeout; timeout--) { 110 READ4(clk, sc->offset + CFG0, &cfg0); 111 if (cfg0 & CFG0_PLL_LOCK) 112 break; 113 DELAY(1); 114 } 115 } 116 117 DEVICE_UNLOCK(clk); 118 119 return (0); 120 } 121 122 static int 123 imx_clk_sscg_pll_recalc(struct clknode *clk, uint64_t *freq) 124 { 125 struct imx_clk_sscg_pll_sc *sc; 126 uint32_t cfg0, cfg2; 127 int divr1, divr2, divf1, divf2, div; 128 129 sc = clknode_get_softc(clk); 130 131 DEVICE_LOCK(clk); 132 READ4(clk, sc->offset + CFG0, &cfg0); 133 READ4(clk, sc->offset + CFG2, &cfg2); 134 DEVICE_UNLOCK(clk); 135 136 /* PLL is bypassed */ 137 if (cfg0 & CFG0_BYPASS2) 138 return (0); 139 140 divr1 = (cfg2 & CFG2_DIVR1_MASK) >> CFG2_DIVR1_SHIFT; 141 divr2 = (cfg2 & CFG2_DIVR2_MASK) >> CFG2_DIVR2_SHIFT; 142 divf1 = (cfg2 & CFG2_DIVF1_MASK) >> CFG2_DIVF1_SHIFT; 143 divf2 = (cfg2 & CFG2_DIVF2_MASK) >> CFG2_DIVF2_SHIFT; 144 div = (cfg2 & CFG2_DIV_MASK) >> CFG2_DIV_SHIFT; 145 146 if (cfg0 & CFG0_BYPASS1) { 147 *freq = *freq / ((divr2 + 1) * (div + 1)); 148 return (0); 149 } 150 151 *freq *= 2 * (divf1 + 1) * (divf2 + 1); 152 *freq /= (divr1 + 1) * (divr2 + 1) * (div + 1); 153 154 return (0); 155 } 156 157 static clknode_method_t imx_clk_sscg_pll_clknode_methods[] = { 158 /* Device interface */ 159 CLKNODEMETHOD(clknode_init, imx_clk_sscg_pll_init), 160 CLKNODEMETHOD(clknode_set_gate, imx_clk_sscg_pll_set_gate), 161 CLKNODEMETHOD(clknode_recalc_freq, imx_clk_sscg_pll_recalc), 162 CLKNODEMETHOD_END 163 }; 164 165 DEFINE_CLASS_1(imx_clk_sscg_pll_clknode, imx_clk_sscg_pll_clknode_class, 166 imx_clk_sscg_pll_clknode_methods, sizeof(struct imx_clk_sscg_pll_sc), 167 clknode_class); 168 169 int 170 imx_clk_sscg_pll_register(struct clkdom *clkdom, 171 struct imx_clk_sscg_pll_def *clkdef) 172 { 173 struct clknode *clk; 174 struct imx_clk_sscg_pll_sc *sc; 175 176 clk = clknode_create(clkdom, &imx_clk_sscg_pll_clknode_class, 177 &clkdef->clkdef); 178 if (clk == NULL) 179 return (1); 180 181 sc = clknode_get_softc(clk); 182 183 sc->offset = clkdef->offset; 184 185 clknode_register(clkdom, clk); 186 187 return (0); 188 } 189