1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2020 Oleksandr Tymoshenko <gonzo@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/bus.h> 34 35 #include <dev/extres/clk/clk.h> 36 37 #include <arm64/freescale/imx/clk/imx_clk_sscg_pll.h> 38 39 #include "clkdev_if.h" 40 41 struct imx_clk_sscg_pll_sc { 42 uint32_t offset; 43 }; 44 45 #define WRITE4(_clk, off, val) \ 46 CLKDEV_WRITE_4(clknode_get_device(_clk), off, val) 47 #define READ4(_clk, off, val) \ 48 CLKDEV_READ_4(clknode_get_device(_clk), off, val) 49 #define DEVICE_LOCK(_clk) \ 50 CLKDEV_DEVICE_LOCK(clknode_get_device(_clk)) 51 #define DEVICE_UNLOCK(_clk) \ 52 CLKDEV_DEVICE_UNLOCK(clknode_get_device(_clk)) 53 54 #define CFG0 0x00 55 #define CFG0_PLL_LOCK (1 << 31) 56 #define CFG0_PD (1 << 7) 57 #define CFG0_BYPASS2 (1 << 5) 58 #define CFG0_BYPASS1 (1 << 4) 59 #define CFG1 0x04 60 #define CFG2 0x08 61 #define CFG2_DIVR1_MASK (7 << 25) 62 #define CFG2_DIVR1_SHIFT 25 63 #define CFG2_DIVR2_MASK (0x3f << 19) 64 #define CFG2_DIVR2_SHIFT 19 65 #define CFG2_DIVF1_MASK (0x3f << 13) 66 #define CFG2_DIVF1_SHIFT 13 67 #define CFG2_DIVF2_MASK (0x3f << 7) 68 #define CFG2_DIVF2_SHIFT 7 69 #define CFG2_DIV_MASK (0x3f << 1) 70 #define CFG2_DIV_SHIFT 1 71 72 #if 0 73 #define dprintf(format, arg...) \ 74 printf("%s:(%s)" format, __func__, clknode_get_name(clk), arg) 75 #else 76 #define dprintf(format, arg...) 77 #endif 78 79 static int 80 imx_clk_sscg_pll_init(struct clknode *clk, device_t dev) 81 { 82 if (clknode_get_parents_num(clk) > 1) { 83 device_printf(clknode_get_device(clk), 84 "error: SSCG PLL does not support more than one parent yet\n"); 85 return (EINVAL); 86 } 87 clknode_init_parent_idx(clk, 0); 88 89 return (0); 90 } 91 92 static int 93 imx_clk_sscg_pll_set_gate(struct clknode *clk, bool enable) 94 { 95 struct imx_clk_sscg_pll_sc *sc; 96 uint32_t cfg0; 97 int timeout; 98 99 sc = clknode_get_softc(clk); 100 101 DEVICE_LOCK(clk); 102 READ4(clk, sc->offset + CFG0, &cfg0); 103 if (enable) 104 cfg0 &= ~(CFG0_PD); 105 else 106 cfg0 |= CFG0_PD; 107 WRITE4(clk, sc->offset + CFG0, cfg0); 108 109 /* Reading lock */ 110 if (enable) { 111 for (timeout = 1000; timeout; timeout--) { 112 READ4(clk, sc->offset + CFG0, &cfg0); 113 if (cfg0 & CFG0_PLL_LOCK) 114 break; 115 DELAY(1); 116 } 117 } 118 119 DEVICE_UNLOCK(clk); 120 121 return (0); 122 } 123 124 static int 125 imx_clk_sscg_pll_recalc(struct clknode *clk, uint64_t *freq) 126 { 127 struct imx_clk_sscg_pll_sc *sc; 128 uint32_t cfg0, cfg2; 129 int divr1, divr2, divf1, divf2, div; 130 131 sc = clknode_get_softc(clk); 132 133 DEVICE_LOCK(clk); 134 READ4(clk, sc->offset + CFG0, &cfg0); 135 READ4(clk, sc->offset + CFG2, &cfg2); 136 DEVICE_UNLOCK(clk); 137 138 /* PLL is bypassed */ 139 if (cfg0 & CFG0_BYPASS2) 140 return (0); 141 142 divr1 = (cfg2 & CFG2_DIVR1_MASK) >> CFG2_DIVR1_SHIFT; 143 divr2 = (cfg2 & CFG2_DIVR2_MASK) >> CFG2_DIVR2_SHIFT; 144 divf1 = (cfg2 & CFG2_DIVF1_MASK) >> CFG2_DIVF1_SHIFT; 145 divf2 = (cfg2 & CFG2_DIVF2_MASK) >> CFG2_DIVF2_SHIFT; 146 div = (cfg2 & CFG2_DIV_MASK) >> CFG2_DIV_SHIFT; 147 148 if (cfg0 & CFG0_BYPASS1) { 149 *freq = *freq / ((divr2 + 1) * (div + 1)); 150 return (0); 151 } 152 153 *freq *= 2 * (divf1 + 1) * (divf2 + 1); 154 *freq /= (divr1 + 1) * (divr2 + 1) * (div + 1); 155 156 return (0); 157 } 158 159 static clknode_method_t imx_clk_sscg_pll_clknode_methods[] = { 160 /* Device interface */ 161 CLKNODEMETHOD(clknode_init, imx_clk_sscg_pll_init), 162 CLKNODEMETHOD(clknode_set_gate, imx_clk_sscg_pll_set_gate), 163 CLKNODEMETHOD(clknode_recalc_freq, imx_clk_sscg_pll_recalc), 164 CLKNODEMETHOD_END 165 }; 166 167 DEFINE_CLASS_1(imx_clk_sscg_pll_clknode, imx_clk_sscg_pll_clknode_class, 168 imx_clk_sscg_pll_clknode_methods, sizeof(struct imx_clk_sscg_pll_sc), 169 clknode_class); 170 171 int 172 imx_clk_sscg_pll_register(struct clkdom *clkdom, 173 struct imx_clk_sscg_pll_def *clkdef) 174 { 175 struct clknode *clk; 176 struct imx_clk_sscg_pll_sc *sc; 177 178 clk = clknode_create(clkdom, &imx_clk_sscg_pll_clknode_class, 179 &clkdef->clkdef); 180 if (clk == NULL) 181 return (1); 182 183 sc = clknode_get_softc(clk); 184 185 sc->offset = clkdef->offset; 186 187 clknode_register(clkdom, clk); 188 189 return (0); 190 } 191