1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2020 Oleksandr Tymoshenko <gonzo@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/bus.h> 32 33 #include <dev/extres/clk/clk.h> 34 35 #include <arm64/freescale/imx/clk/imx_clk_frac_pll.h> 36 37 #include "clkdev_if.h" 38 39 struct imx_clk_frac_pll_sc { 40 uint32_t offset; 41 }; 42 43 #define WRITE4(_clk, off, val) \ 44 CLKDEV_WRITE_4(clknode_get_device(_clk), off, val) 45 #define READ4(_clk, off, val) \ 46 CLKDEV_READ_4(clknode_get_device(_clk), off, val) 47 #define DEVICE_LOCK(_clk) \ 48 CLKDEV_DEVICE_LOCK(clknode_get_device(_clk)) 49 #define DEVICE_UNLOCK(_clk) \ 50 CLKDEV_DEVICE_UNLOCK(clknode_get_device(_clk)) 51 52 #define CFG0 0 53 #define CFG0_PLL_LOCK (1 << 31) 54 #define CFG0_PD (1 << 19) 55 #define CFG0_BYPASS (1 << 14) 56 #define CFG0_NEWDIV_VAL (1 << 12) 57 #define CFG0_NEWDIV_ACK (1 << 11) 58 #define CFG0_OUTPUT_DIV_MASK (0x1f << 0) 59 #define CFG0_OUTPUT_DIV_SHIFT 0 60 #define CFG1 4 61 #define CFG1_FRAC_DIV_MASK (0xffffff << 7) 62 #define CFG1_FRAC_DIV_SHIFT 7 63 #define CFG1_INT_DIV_MASK (0x7f << 0) 64 #define CFG1_INT_DIV_SHIFT 0 65 66 #if 0 67 #define dprintf(format, arg...) \ 68 printf("%s:(%s)" format, __func__, clknode_get_name(clk), arg) 69 #else 70 #define dprintf(format, arg...) 71 #endif 72 73 static int 74 imx_clk_frac_pll_init(struct clknode *clk, device_t dev) 75 { 76 77 clknode_init_parent_idx(clk, 0); 78 return (0); 79 } 80 81 static int 82 imx_clk_frac_pll_set_gate(struct clknode *clk, bool enable) 83 { 84 struct imx_clk_frac_pll_sc *sc; 85 uint32_t cfg0; 86 int timeout; 87 88 sc = clknode_get_softc(clk); 89 90 DEVICE_LOCK(clk); 91 READ4(clk, sc->offset + CFG0, &cfg0); 92 if (enable) 93 cfg0 &= ~(CFG0_PD); 94 else 95 cfg0 |= CFG0_PD; 96 WRITE4(clk, sc->offset + CFG0, cfg0); 97 98 /* Wait for PLL to lock */ 99 if (enable && ((cfg0 & CFG0_BYPASS) == 0)) { 100 for (timeout = 1000; timeout; timeout--) { 101 READ4(clk, sc->offset + CFG0, &cfg0); 102 if (cfg0 & CFG0_PLL_LOCK) 103 break; 104 DELAY(1); 105 } 106 } 107 108 DEVICE_UNLOCK(clk); 109 110 return (0); 111 } 112 113 static int 114 imx_clk_frac_pll_recalc(struct clknode *clk, uint64_t *freq) 115 { 116 struct imx_clk_frac_pll_sc *sc; 117 uint32_t cfg0, cfg1; 118 uint64_t div, divfi, divff, divf_val; 119 120 sc = clknode_get_softc(clk); 121 122 DEVICE_LOCK(clk); 123 READ4(clk, sc->offset + CFG0, &cfg0); 124 READ4(clk, sc->offset + CFG1, &cfg1); 125 DEVICE_UNLOCK(clk); 126 127 div = (cfg0 & CFG0_OUTPUT_DIV_MASK) >> CFG0_OUTPUT_DIV_SHIFT; 128 div = (div + 1) * 2; 129 divff = (cfg1 & CFG1_FRAC_DIV_MASK) >> CFG1_FRAC_DIV_SHIFT; 130 divfi = (cfg1 & CFG1_INT_DIV_MASK) >> CFG1_INT_DIV_SHIFT; 131 132 /* PLL is bypassed */ 133 if (cfg0 & CFG0_BYPASS) 134 return (0); 135 136 divf_val = 1 + divfi + (divff/0x1000000); 137 *freq = *freq * 8 * divf_val / div; 138 139 return (0); 140 } 141 142 static clknode_method_t imx_clk_frac_pll_clknode_methods[] = { 143 /* Device interface */ 144 CLKNODEMETHOD(clknode_init, imx_clk_frac_pll_init), 145 CLKNODEMETHOD(clknode_set_gate, imx_clk_frac_pll_set_gate), 146 CLKNODEMETHOD(clknode_recalc_freq, imx_clk_frac_pll_recalc), 147 CLKNODEMETHOD_END 148 }; 149 150 DEFINE_CLASS_1(imx_clk_frac_pll_clknode, imx_clk_frac_pll_clknode_class, 151 imx_clk_frac_pll_clknode_methods, sizeof(struct imx_clk_frac_pll_sc), 152 clknode_class); 153 154 int 155 imx_clk_frac_pll_register(struct clkdom *clkdom, 156 struct imx_clk_frac_pll_def *clkdef) 157 { 158 struct clknode *clk; 159 struct imx_clk_frac_pll_sc *sc; 160 161 clk = clknode_create(clkdom, &imx_clk_frac_pll_clknode_class, 162 &clkdef->clkdef); 163 if (clk == NULL) 164 return (1); 165 166 sc = clknode_get_softc(clk); 167 168 sc->offset = clkdef->offset; 169 170 clknode_register(clkdom, clk); 171 172 return (0); 173 } 174