1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2020 Oleksandr Tymoshenko <gonzo@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/bus.h> 34 35 #include <dev/extres/clk/clk.h> 36 37 #include <arm64/freescale/imx/clk/imx_clk_frac_pll.h> 38 39 #include "clkdev_if.h" 40 41 struct imx_clk_frac_pll_sc { 42 uint32_t offset; 43 }; 44 45 #define WRITE4(_clk, off, val) \ 46 CLKDEV_WRITE_4(clknode_get_device(_clk), off, val) 47 #define READ4(_clk, off, val) \ 48 CLKDEV_READ_4(clknode_get_device(_clk), off, val) 49 #define DEVICE_LOCK(_clk) \ 50 CLKDEV_DEVICE_LOCK(clknode_get_device(_clk)) 51 #define DEVICE_UNLOCK(_clk) \ 52 CLKDEV_DEVICE_UNLOCK(clknode_get_device(_clk)) 53 54 #define CFG0 0 55 #define CFG0_PLL_LOCK (1 << 31) 56 #define CFG0_PD (1 << 19) 57 #define CFG0_BYPASS (1 << 14) 58 #define CFG0_NEWDIV_VAL (1 << 12) 59 #define CFG0_NEWDIV_ACK (1 << 11) 60 #define CFG0_OUTPUT_DIV_MASK (0x1f << 0) 61 #define CFG0_OUTPUT_DIV_SHIFT 0 62 #define CFG1 4 63 #define CFG1_FRAC_DIV_MASK (0xffffff << 7) 64 #define CFG1_FRAC_DIV_SHIFT 7 65 #define CFG1_INT_DIV_MASK (0x7f << 0) 66 #define CFG1_INT_DIV_SHIFT 0 67 68 #if 0 69 #define dprintf(format, arg...) \ 70 printf("%s:(%s)" format, __func__, clknode_get_name(clk), arg) 71 #else 72 #define dprintf(format, arg...) 73 #endif 74 75 static int 76 imx_clk_frac_pll_init(struct clknode *clk, device_t dev) 77 { 78 79 clknode_init_parent_idx(clk, 0); 80 return (0); 81 } 82 83 static int 84 imx_clk_frac_pll_set_gate(struct clknode *clk, bool enable) 85 { 86 struct imx_clk_frac_pll_sc *sc; 87 uint32_t cfg0; 88 int timeout; 89 90 sc = clknode_get_softc(clk); 91 92 DEVICE_LOCK(clk); 93 READ4(clk, sc->offset + CFG0, &cfg0); 94 if (enable) 95 cfg0 &= ~(CFG0_PD); 96 else 97 cfg0 |= CFG0_PD; 98 WRITE4(clk, sc->offset + CFG0, cfg0); 99 100 /* Wait for PLL to lock */ 101 if (enable && ((cfg0 & CFG0_BYPASS) == 0)) { 102 for (timeout = 1000; timeout; timeout--) { 103 READ4(clk, sc->offset + CFG0, &cfg0); 104 if (cfg0 & CFG0_PLL_LOCK) 105 break; 106 DELAY(1); 107 } 108 } 109 110 DEVICE_UNLOCK(clk); 111 112 return (0); 113 } 114 115 static int 116 imx_clk_frac_pll_recalc(struct clknode *clk, uint64_t *freq) 117 { 118 struct imx_clk_frac_pll_sc *sc; 119 uint32_t cfg0, cfg1; 120 uint64_t div, divfi, divff, divf_val; 121 122 sc = clknode_get_softc(clk); 123 124 DEVICE_LOCK(clk); 125 READ4(clk, sc->offset + CFG0, &cfg0); 126 READ4(clk, sc->offset + CFG1, &cfg1); 127 DEVICE_UNLOCK(clk); 128 129 div = (cfg0 & CFG0_OUTPUT_DIV_MASK) >> CFG0_OUTPUT_DIV_SHIFT; 130 div = (div + 1) * 2; 131 divff = (cfg1 & CFG1_FRAC_DIV_MASK) >> CFG1_FRAC_DIV_SHIFT; 132 divfi = (cfg1 & CFG1_INT_DIV_MASK) >> CFG1_INT_DIV_SHIFT; 133 134 /* PLL is bypassed */ 135 if (cfg0 & CFG0_BYPASS) 136 return (0); 137 138 divf_val = 1 + divfi + (divff/0x1000000); 139 *freq = *freq * 8 * divf_val / div; 140 141 return (0); 142 } 143 144 static clknode_method_t imx_clk_frac_pll_clknode_methods[] = { 145 /* Device interface */ 146 CLKNODEMETHOD(clknode_init, imx_clk_frac_pll_init), 147 CLKNODEMETHOD(clknode_set_gate, imx_clk_frac_pll_set_gate), 148 CLKNODEMETHOD(clknode_recalc_freq, imx_clk_frac_pll_recalc), 149 CLKNODEMETHOD_END 150 }; 151 152 DEFINE_CLASS_1(imx_clk_frac_pll_clknode, imx_clk_frac_pll_clknode_class, 153 imx_clk_frac_pll_clknode_methods, sizeof(struct imx_clk_frac_pll_sc), 154 clknode_class); 155 156 int 157 imx_clk_frac_pll_register(struct clkdom *clkdom, 158 struct imx_clk_frac_pll_def *clkdef) 159 { 160 struct clknode *clk; 161 struct imx_clk_frac_pll_sc *sc; 162 163 clk = clknode_create(clkdom, &imx_clk_frac_pll_clknode_class, 164 &clkdef->clkdef); 165 if (clk == NULL) 166 return (1); 167 168 sc = clknode_get_softc(clk); 169 170 sc->offset = clkdef->offset; 171 172 clknode_register(clkdom, clk); 173 174 return (0); 175 } 176