1 /*- 2 * Copyright (c) 2018-2020 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by SRI International and the University of 6 * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237 7 * ("CTSRD"), as part of the DARPA CRASH research programme. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #ifndef _ARM64_CORESIGHT_CORESIGHT_TMC_H_ 32 #define _ARM64_CORESIGHT_CORESIGHT_TMC_H_ 33 34 #define TMC_RSZ 0x004 /* RAM Size Register */ 35 #define TMC_STS 0x00C /* Status Register */ 36 #define STS_MEMERR (1 << 5) 37 #define STS_EMPTY (1 << 4) 38 #define STS_FTEMPTY (1 << 3) 39 #define STS_TMCREADY (1 << 2) 40 #define STS_TRIGGERED (1 << 1) 41 #define STS_FULL (1 << 0) 42 #define TMC_RRD 0x010 /* RAM Read Data Register */ 43 #define TMC_RRP 0x014 /* RAM Read Pointer Register */ 44 #define TMC_RWP 0x018 /* RAM Write Pointer Register */ 45 #define TMC_TRG 0x01C /* Trigger Counter Register */ 46 #define TMC_CTL 0x020 /* Control Register */ 47 #define CTL_TRACECAPTEN (1 << 0) /* Controls trace capture. */ 48 #define TMC_RWD 0x024 /* RAM Write Data Register */ 49 #define TMC_MODE 0x028 /* Mode Register */ 50 #define MODE_HW_FIFO 2 51 #define MODE_SW_FIFO 1 52 #define MODE_CIRCULAR_BUFFER 0 53 #define TMC_LBUFLEVEL 0x02C /* Latched Buffer Fill Level */ 54 #define TMC_CBUFLEVEL 0x030 /* Current Buffer Fill Level */ 55 #define TMC_BUFWM 0x034 /* Buffer Level Water Mark */ 56 #define TMC_RRPHI 0x038 /* RAM Read Pointer High Register */ 57 #define TMC_RWPHI 0x03C /* RAM Write Pointer High Register */ 58 #define TMC_AXICTL 0x110 /* AXI Control Register */ 59 #define AXICTL_WRBURSTLEN_S 8 60 #define AXICTL_WRBURSTLEN_M (0xf << AXICTL_WRBURSTLEN_S) 61 #define AXICTL_WRBURSTLEN_16 (0xf << AXICTL_WRBURSTLEN_S) 62 #define AXICTL_SG_MODE (1 << 7) /* Scatter Gather Mode */ 63 #define AXICTL_CACHE_CTRL_BIT3 (1 << 5) 64 #define AXICTL_CACHE_CTRL_BIT2 (1 << 4) 65 #define AXICTL_CACHE_CTRL_BIT1 (1 << 3) 66 #define AXICTL_CACHE_CTRL_BIT0 (1 << 2) 67 #define AXICTL_AXCACHE_OS (0xf << 2) 68 #define AXICTL_PROT_CTRL_BIT1 (1 << 1) 69 #define AXICTL_PROT_CTRL_BIT0 (1 << 0) 70 #define TMC_DBALO 0x118 /* Data Buffer Address Low Register */ 71 #define TMC_DBAHI 0x11C /* Data Buffer Address High Register */ 72 #define TMC_FFSR 0x300 /* Formatter and Flush Status Register */ 73 #define TMC_FFCR 0x304 /* Formatter and Flush Control Register */ 74 #define FFCR_EN_FMT (1 << 0) 75 #define FFCR_EN_TI (1 << 1) 76 #define FFCR_FON_FLIN (1 << 4) 77 #define FFCR_FON_TRIG_EVT (1 << 5) 78 #define FFCR_FLUSH_MAN (1 << 6) 79 #define FFCR_TRIGON_TRIGIN (1 << 8) 80 #define TMC_PSCR 0x308 /* Periodic Synchronization Counter Register */ 81 #define TMC_ITATBMDATA0 0xED0 /* Integration Test ATB Master Data Register 0 */ 82 #define TMC_ITATBMCTR2 0xED4 /* Integration Test ATB Master Interface Control 2 Register */ 83 #define TMC_ITATBMCTR1 0xED8 /* Integration Test ATB Master Control Register 1 */ 84 #define TMC_ITATBMCTR0 0xEDC /* Integration Test ATB Master Interface Control 0 Register */ 85 #define TMC_ITMISCOP0 0xEE0 /* Integration Test Miscellaneous Output Register 0 */ 86 #define TMC_ITTRFLIN 0xEE8 /* Integration Test Trigger In and Flush In Register */ 87 #define TMC_ITATBDATA0 0xEEC /* Integration Test ATB Data Register 0 */ 88 #define TMC_ITATBCTR2 0xEF0 /* Integration Test ATB Control 2 Register */ 89 #define TMC_ITATBCTR1 0xEF4 /* Integration Test ATB Control 1 Register */ 90 #define TMC_ITATBCTR0 0xEF8 /* Integration Test ATB Control 0 Register */ 91 #define TMC_ITCTRL 0xF00 /* Integration Mode Control Register */ 92 #define TMC_CLAIMSET 0xFA0 /* Claim Tag Set Register */ 93 #define TMC_CLAIMCLR 0xFA4 /* Claim Tag Clear Register */ 94 #define TMC_LAR 0xFB0 /* Lock Access Register */ 95 #define TMC_LSR 0xFB4 /* Lock Status Register */ 96 #define TMC_AUTHSTATUS 0xFB8 /* Authentication Status Register */ 97 #define TMC_DEVID 0xFC8 /* Device Configuration Register */ 98 #define DEVID_CONFIGTYPE_S 6 99 #define DEVID_CONFIGTYPE_M (0x3 << DEVID_CONFIGTYPE_S) 100 #define DEVID_CONFIGTYPE_ETB (0 << DEVID_CONFIGTYPE_S) 101 #define DEVID_CONFIGTYPE_ETR (1 << DEVID_CONFIGTYPE_S) 102 #define DEVID_CONFIGTYPE_ETF (2 << DEVID_CONFIGTYPE_S) 103 #define TMC_DEVTYPE 0xFCC /* Device Type Identifier Register */ 104 #define TMC_PERIPHID4 0xFD0 /* Peripheral ID4 Register */ 105 #define TMC_PERIPHID5 0xFD4 /* Peripheral ID5 Register */ 106 #define TMC_PERIPHID6 0xFD8 /* Peripheral ID6 Register */ 107 #define TMC_PERIPHID7 0xFDC /* Peripheral ID7 Register */ 108 #define TMC_PERIPHID0 0xFE0 /* Peripheral ID0 Register */ 109 #define TMC_PERIPHID1 0xFE4 /* Peripheral ID1 Register */ 110 #define TMC_PERIPHID2 0xFE8 /* Peripheral ID2 Register */ 111 #define TMC_PERIPHID3 0xFEC /* Peripheral ID3 Register */ 112 #define TMC_COMPID0 0xFF0 /* Component ID0 Register */ 113 #define TMC_COMPID1 0xFF4 /* Component ID1 Register */ 114 #define TMC_COMPID2 0xFF8 /* Component ID2 Register */ 115 #define TMC_COMPID3 0xFFC /* Component ID3 Register */ 116 117 DECLARE_CLASS(tmc_driver); 118 119 struct tmc_softc { 120 struct resource *res; 121 device_t dev; 122 uint64_t cycle; 123 struct coresight_platform_data *pdata; 124 uint32_t dev_type; 125 #define CORESIGHT_UNKNOWN 0 126 #define CORESIGHT_ETR 1 127 #define CORESIGHT_ETF 2 128 uint32_t nev; 129 struct coresight_event *event; 130 boolean_t etf_configured; 131 }; 132 133 int tmc_attach(device_t dev); 134 135 #endif /* !_ARM64_CORESIGHT_CORESIGHT_TMC_H_ */ 136