1 /*- 2 * Copyright (c) 2018-2020 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by BAE Systems, the University of Cambridge 6 * Computer Laboratory, and Memorial University under DARPA/AFRL contract 7 * FA8650-15-C-7558 ("CADETS"), as part of the DARPA Transparent Computing 8 * (TC) research program. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/rman.h> 37 #include <sys/kernel.h> 38 #include <sys/module.h> 39 #include <machine/bus.h> 40 41 #include <arm64/coresight/coresight.h> 42 #include <arm64/coresight/coresight_etm4x.h> 43 44 #include "coresight_if.h" 45 46 #define ETM_DEBUG 47 #undef ETM_DEBUG 48 49 #ifdef ETM_DEBUG 50 #define dprintf(fmt, ...) printf(fmt, ##__VA_ARGS__) 51 #else 52 #define dprintf(fmt, ...) 53 #endif 54 55 /* 56 * Typical trace flow: 57 * 58 * CPU0 -> ETM0 -> funnel1 -> funnel0 -> ETF -> replicator -> ETR -> DRAM 59 * CPU1 -> ETM1 -> funnel1 -^ 60 * CPU2 -> ETM2 -> funnel1 -^ 61 * CPU3 -> ETM3 -> funnel1 -^ 62 */ 63 64 static struct resource_spec etm_spec[] = { 65 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 66 { -1, 0 } 67 }; 68 69 static int 70 etm_prepare(device_t dev, struct coresight_event *event) 71 { 72 struct etm_softc *sc; 73 uint32_t reg; 74 int i; 75 76 sc = device_get_softc(dev); 77 78 /* Configure ETM */ 79 80 /* 81 * Enable the return stack, global timestamping, 82 * Context ID, and Virtual context identifier tracing. 83 */ 84 reg = TRCCONFIGR_RS | TRCCONFIGR_TS; 85 reg |= TRCCONFIGR_CID | TRCCONFIGR_VMID; 86 reg |= TRCCONFIGR_INSTP0_LDRSTR; 87 reg |= TRCCONFIGR_COND_ALL; 88 bus_write_4(sc->res, TRCCONFIGR, reg); 89 90 /* Disable all event tracing. */ 91 bus_write_4(sc->res, TRCEVENTCTL0R, 0); 92 bus_write_4(sc->res, TRCEVENTCTL1R, 0); 93 94 /* Disable stalling, if implemented. */ 95 bus_write_4(sc->res, TRCSTALLCTLR, 0); 96 97 /* Enable trace synchronization every 4096 bytes of trace. */ 98 bus_write_4(sc->res, TRCSYNCPR, TRCSYNCPR_4K); 99 100 /* Set a value for the trace ID */ 101 bus_write_4(sc->res, TRCTRACEIDR, event->etm.trace_id); 102 103 /* 104 * Disable the timestamp event. The trace unit still generates 105 * timestamps due to other reasons such as trace synchronization. 106 */ 107 bus_write_4(sc->res, TRCTSCTLR, 0); 108 109 /* 110 * Enable ViewInst to trace everything, with the start/stop 111 * logic started. 112 */ 113 reg = TRCVICTLR_SSSTATUS; 114 115 /* The number of the single resource used to activate the event. */ 116 reg |= (1 << EVENT_SEL_S); 117 118 if (event->excp_level > 2) 119 return (-1); 120 121 reg |= TRCVICTLR_EXLEVEL_NS_M; 122 reg &= ~TRCVICTLR_EXLEVEL_NS(event->excp_level); 123 reg |= TRCVICTLR_EXLEVEL_S_M; 124 reg &= ~TRCVICTLR_EXLEVEL_S(event->excp_level); 125 bus_write_4(sc->res, TRCVICTLR, reg); 126 127 for (i = 0; i < event->naddr * 2; i++) { 128 dprintf("configure range %d, address %lx\n", 129 i, event->addr[i]); 130 bus_write_8(sc->res, TRCACVR(i), event->addr[i]); 131 132 reg = 0; 133 /* Secure state */ 134 reg |= TRCACATR_EXLEVEL_S_M; 135 reg &= ~TRCACATR_EXLEVEL_S(event->excp_level); 136 /* Non-secure state */ 137 reg |= TRCACATR_EXLEVEL_NS_M; 138 reg &= ~TRCACATR_EXLEVEL_NS(event->excp_level); 139 bus_write_4(sc->res, TRCACATR(i), reg); 140 141 /* Address range is included */ 142 reg = bus_read_4(sc->res, TRCVIIECTLR); 143 reg |= (1 << (TRCVIIECTLR_INCLUDE_S + i / 2)); 144 bus_write_4(sc->res, TRCVIIECTLR, reg); 145 } 146 147 /* No address filtering for ViewData. */ 148 bus_write_4(sc->res, TRCVDARCCTLR, 0); 149 150 /* Clear the STATUS bit to zero */ 151 bus_write_4(sc->res, TRCSSCSR(0), 0); 152 153 if (event->naddr == 0) { 154 /* No address range filtering for ViewInst. */ 155 bus_write_4(sc->res, TRCVIIECTLR, 0); 156 } 157 158 /* No start or stop points for ViewInst. */ 159 bus_write_4(sc->res, TRCVISSCTLR, 0); 160 161 /* Disable ViewData */ 162 bus_write_4(sc->res, TRCVDCTLR, 0); 163 164 /* No address filtering for ViewData. */ 165 bus_write_4(sc->res, TRCVDSACCTLR, 0); 166 167 return (0); 168 } 169 170 static int 171 etm_init(device_t dev) 172 { 173 struct etm_softc *sc; 174 uint32_t reg __unused; 175 176 sc = device_get_softc(dev); 177 178 /* Unlocking Coresight */ 179 bus_write_4(sc->res, CORESIGHT_LAR, CORESIGHT_UNLOCK); 180 181 /* Unlocking ETM */ 182 bus_write_4(sc->res, TRCOSLAR, 0); 183 184 reg = bus_read_4(sc->res, TRCIDR(1)); 185 dprintf("ETM Version: %d.%d\n", 186 (reg & TRCIDR1_TRCARCHMAJ_M) >> TRCIDR1_TRCARCHMAJ_S, 187 (reg & TRCIDR1_TRCARCHMIN_M) >> TRCIDR1_TRCARCHMIN_S); 188 189 return (0); 190 } 191 192 static int 193 etm_enable(device_t dev, struct endpoint *endp, 194 struct coresight_event *event) 195 { 196 struct etm_softc *sc; 197 uint32_t reg; 198 199 sc = device_get_softc(dev); 200 201 etm_prepare(dev, event); 202 203 /* Enable the trace unit */ 204 bus_write_4(sc->res, TRCPRGCTLR, TRCPRGCTLR_EN); 205 206 /* Wait for an IDLE bit to be LOW */ 207 do { 208 reg = bus_read_4(sc->res, TRCSTATR); 209 } while ((reg & TRCSTATR_IDLE) == 1); 210 211 if ((bus_read_4(sc->res, TRCPRGCTLR) & TRCPRGCTLR_EN) == 0) 212 panic("etm is not enabled\n"); 213 214 return (0); 215 } 216 217 static void 218 etm_disable(device_t dev, struct endpoint *endp, 219 struct coresight_event *event) 220 { 221 struct etm_softc *sc; 222 uint32_t reg; 223 224 sc = device_get_softc(dev); 225 226 /* Disable the trace unit */ 227 bus_write_4(sc->res, TRCPRGCTLR, 0); 228 229 /* Wait for an IDLE bit */ 230 do { 231 reg = bus_read_4(sc->res, TRCSTATR); 232 } while ((reg & TRCSTATR_IDLE) == 0); 233 } 234 235 int 236 etm_attach(device_t dev) 237 { 238 struct coresight_desc desc; 239 struct etm_softc *sc; 240 241 sc = device_get_softc(dev); 242 243 if (bus_alloc_resources(dev, etm_spec, &sc->res) != 0) { 244 device_printf(dev, "cannot allocate resources for device\n"); 245 return (ENXIO); 246 } 247 248 desc.pdata = sc->pdata; 249 desc.dev = dev; 250 desc.dev_type = CORESIGHT_ETMV4; 251 coresight_register(&desc); 252 253 return (0); 254 } 255 256 static device_method_t etm_methods[] = { 257 /* Coresight interface */ 258 DEVMETHOD(coresight_init, etm_init), 259 DEVMETHOD(coresight_enable, etm_enable), 260 DEVMETHOD(coresight_disable, etm_disable), 261 DEVMETHOD_END 262 }; 263 264 DEFINE_CLASS_0(etm, etm_driver, etm_methods, sizeof(struct etm_softc)); 265