1 /*- 2 * Copyright (c) 2018-2020 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by SRI International and the University of 6 * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237 7 * ("CTSRD"), as part of the DARPA CRASH research programme. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 #include <sys/rman.h> 36 #include <sys/kernel.h> 37 #include <sys/lock.h> 38 #include <sys/module.h> 39 #include <sys/mutex.h> 40 #include <machine/bus.h> 41 42 #include <arm64/coresight/coresight.h> 43 44 static struct mtx cs_mtx; 45 struct coresight_device_list cs_devs; 46 47 int 48 coresight_register(struct coresight_desc *desc) 49 { 50 struct coresight_device *cs_dev; 51 52 cs_dev = malloc(sizeof(struct coresight_device), 53 M_CORESIGHT, M_WAITOK | M_ZERO); 54 cs_dev->dev = desc->dev; 55 cs_dev->pdata = desc->pdata; 56 cs_dev->dev_type = desc->dev_type; 57 58 mtx_lock(&cs_mtx); 59 TAILQ_INSERT_TAIL(&cs_devs, cs_dev, link); 60 mtx_unlock(&cs_mtx); 61 62 return (0); 63 } 64 65 struct endpoint * 66 coresight_get_output_endpoint(struct coresight_platform_data *pdata) 67 { 68 struct endpoint *endp; 69 70 if (pdata->out_ports != 1) 71 return (NULL); 72 73 TAILQ_FOREACH(endp, &pdata->endpoints, link) { 74 if (endp->input == 0) 75 return (endp); 76 } 77 78 return (NULL); 79 } 80 81 struct coresight_device * 82 coresight_get_output_device(struct endpoint *endp, struct endpoint **out_endp) 83 { 84 struct coresight_platform_data *pdata; 85 struct coresight_device *cs_dev; 86 struct endpoint *endp2; 87 88 TAILQ_FOREACH(cs_dev, &cs_devs, link) { 89 pdata = cs_dev->pdata; 90 TAILQ_FOREACH(endp2, &cs_dev->pdata->endpoints, link) { 91 switch (pdata->bus_type) { 92 case CORESIGHT_BUS_FDT: 93 #ifdef FDT 94 if (endp->their_node == endp2->my_node) { 95 *out_endp = endp2; 96 return (cs_dev); 97 } 98 #endif 99 break; 100 101 case CORESIGHT_BUS_ACPI: 102 #ifdef DEV_ACPI 103 if (endp->their_handle == endp2->my_handle) { 104 *out_endp = endp2; 105 return (cs_dev); 106 } 107 #endif 108 break; 109 } 110 } 111 } 112 113 return (NULL); 114 } 115 116 static void 117 coresight_init(void) 118 { 119 120 mtx_init(&cs_mtx, "ARM Coresight", NULL, MTX_DEF); 121 TAILQ_INIT(&cs_devs); 122 } 123 124 SYSINIT(coresight, SI_SUB_DRIVERS, SI_ORDER_FIRST, coresight_init, NULL); 125