1 /*- 2 * Copyright (c) 2015 The FreeBSD Foundation 3 * 4 * This software was developed by Semihalf under 5 * the sponsorship of the FreeBSD Foundation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* PCIe external MAC root complex driver (PEM) for Cavium Thunder SOC */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include "opt_platform.h" 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/bus.h> 39 #include <sys/kernel.h> 40 #include <sys/malloc.h> 41 #include <sys/module.h> 42 #include <sys/rman.h> 43 #include <sys/endian.h> 44 45 #ifdef FDT 46 #include <dev/ofw/openfirm.h> 47 #include <dev/ofw/ofw_bus.h> 48 #include <dev/ofw/ofw_bus_subr.h> 49 #include <dev/ofw/ofw_pci.h> 50 #endif 51 52 #include <dev/pci/pcivar.h> 53 #include <dev/pci/pcireg.h> 54 #include <dev/pci/pci_host_generic.h> 55 #include <dev/pci/pcib_private.h> 56 57 #include <machine/bus.h> 58 #include <machine/resource.h> 59 #include <machine/smp.h> 60 #include <machine/intr.h> 61 62 #include <arm64/cavium/thunder_pcie_common.h> 63 #include <arm64/cavium/thunder_pcie_pem.h> 64 #include "pcib_if.h" 65 66 #define THUNDER_PEM_DEVICE_ID 0xa020 67 #define THUNDER_PEM_VENDOR_ID 0x177d 68 69 /* ThunderX specific defines */ 70 #define THUNDER_PEMn_REG_BASE(unit) (0x87e0c0000000UL | ((unit) << 24)) 71 #define PCIERC_CFG002 0x08 72 #define PCIERC_CFG006 0x18 73 #define PCIERC_CFG032 0x80 74 #define PCIERC_CFG006_SEC_BUS(reg) (((reg) >> 8) & 0xFF) 75 #define PEM_CFG_RD_REG_ALIGN(reg) ((reg) & ~0x3) 76 #define PEM_CFG_RD_REG_DATA(val) (((val) >> 32) & 0xFFFFFFFF) 77 #define PEM_CFG_RD 0x30 78 #define PEM_CFG_LINK_MASK 0x3 79 #define PEM_CFG_LINK_RDY 0x3 80 #define PEM_CFG_SLIX_TO_REG(slix) ((slix) << 4) 81 #define SBNUM_OFFSET 0x8 82 #define SBNUM_MASK 0xFF 83 #define PEM_ON_REG 0x420 84 #define PEM_CTL_STATUS 0x0 85 #define PEM_LINK_ENABLE (1 << 4) 86 #define PEM_LINK_DLLA (1 << 29) 87 #define PEM_LINK_LT (1 << 27) 88 #define PEM_BUS_SHIFT (24) 89 #define PEM_SLOT_SHIFT (19) 90 #define PEM_FUNC_SHIFT (16) 91 #define SLIX_S2M_REGX_ACC 0x874001000000UL 92 #define SLIX_S2M_REGX_ACC_SIZE 0x1000 93 #define SLIX_S2M_REGX_ACC_SPACING 0x001000000000UL 94 #define SLI_BASE 0x880000000000UL 95 #define SLI_WINDOW_SPACING 0x004000000000UL 96 #define SLI_PCI_OFFSET 0x001000000000UL 97 #define SLI_NODE_SHIFT (44) 98 #define SLI_NODE_MASK (3) 99 #define SLI_GROUP_SHIFT (40) 100 #define SLI_ID_SHIFT (24) 101 #define SLI_ID_MASK (7) 102 #define SLI_PEMS_PER_GROUP (3) 103 #define SLI_GROUPS_PER_NODE (2) 104 #define SLI_PEMS_PER_NODE (SLI_PEMS_PER_GROUP * SLI_GROUPS_PER_NODE) 105 #define SLI_ACC_REG_CNT (256) 106 107 /* 108 * Each PEM device creates its own bus with 109 * own address translation, so we can adjust bus addresses 110 * as we want. To support 32-bit cards let's assume 111 * PCI window assignment looks as following: 112 * 113 * 0x00000000 - 0x000FFFFF IO 114 * 0x00100000 - 0xFFFFFFFF Memory 115 */ 116 #define PCI_IO_BASE 0x00000000UL 117 #define PCI_IO_SIZE 0x00100000UL 118 #define PCI_MEMORY_BASE PCI_IO_SIZE 119 #define PCI_MEMORY_SIZE 0xFFF00000UL 120 121 #define RID_PEM_SPACE 1 122 123 static int thunder_pem_activate_resource(device_t, device_t, int, int, 124 struct resource *); 125 static int thunder_pem_adjust_resource(device_t, device_t, int, 126 struct resource *, rman_res_t, rman_res_t); 127 static struct resource * thunder_pem_alloc_resource(device_t, device_t, int, 128 int *, rman_res_t, rman_res_t, rman_res_t, u_int); 129 static int thunder_pem_alloc_msi(device_t, device_t, int, int, int *); 130 static int thunder_pem_release_msi(device_t, device_t, int, int *); 131 static int thunder_pem_alloc_msix(device_t, device_t, int *); 132 static int thunder_pem_release_msix(device_t, device_t, int); 133 static int thunder_pem_map_msi(device_t, device_t, int, uint64_t *, uint32_t *); 134 static int thunder_pem_get_id(device_t, device_t, enum pci_id_type, 135 uintptr_t *); 136 static int thunder_pem_attach(device_t); 137 static int thunder_pem_deactivate_resource(device_t, device_t, int, int, 138 struct resource *); 139 static bus_dma_tag_t thunder_pem_get_dma_tag(device_t, device_t); 140 static int thunder_pem_detach(device_t); 141 static uint64_t thunder_pem_config_reg_read(struct thunder_pem_softc *, int); 142 static int thunder_pem_link_init(struct thunder_pem_softc *); 143 static int thunder_pem_maxslots(device_t); 144 static int thunder_pem_probe(device_t); 145 static uint32_t thunder_pem_read_config(device_t, u_int, u_int, u_int, u_int, 146 int); 147 static int thunder_pem_read_ivar(device_t, device_t, int, uintptr_t *); 148 static void thunder_pem_release_all(device_t); 149 static int thunder_pem_release_resource(device_t, device_t, int, int, 150 struct resource *); 151 static struct rman * thunder_pem_rman(struct thunder_pem_softc *, int); 152 static void thunder_pem_slix_s2m_regx_acc_modify(struct thunder_pem_softc *, 153 int, int); 154 static void thunder_pem_write_config(device_t, u_int, u_int, u_int, u_int, 155 uint32_t, int); 156 static int thunder_pem_write_ivar(device_t, device_t, int, uintptr_t); 157 158 /* Global handlers for SLI interface */ 159 static bus_space_handle_t sli0_s2m_regx_base = 0; 160 static bus_space_handle_t sli1_s2m_regx_base = 0; 161 162 static device_method_t thunder_pem_methods[] = { 163 /* Device interface */ 164 DEVMETHOD(device_probe, thunder_pem_probe), 165 DEVMETHOD(device_attach, thunder_pem_attach), 166 DEVMETHOD(device_detach, thunder_pem_detach), 167 168 /* Bus interface */ 169 DEVMETHOD(bus_read_ivar, thunder_pem_read_ivar), 170 DEVMETHOD(bus_write_ivar, thunder_pem_write_ivar), 171 DEVMETHOD(bus_alloc_resource, thunder_pem_alloc_resource), 172 DEVMETHOD(bus_release_resource, thunder_pem_release_resource), 173 DEVMETHOD(bus_adjust_resource, thunder_pem_adjust_resource), 174 DEVMETHOD(bus_activate_resource, thunder_pem_activate_resource), 175 DEVMETHOD(bus_deactivate_resource, thunder_pem_deactivate_resource), 176 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 177 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 178 179 DEVMETHOD(bus_get_dma_tag, thunder_pem_get_dma_tag), 180 181 /* pcib interface */ 182 DEVMETHOD(pcib_maxslots, thunder_pem_maxslots), 183 DEVMETHOD(pcib_read_config, thunder_pem_read_config), 184 DEVMETHOD(pcib_write_config, thunder_pem_write_config), 185 DEVMETHOD(pcib_alloc_msix, thunder_pem_alloc_msix), 186 DEVMETHOD(pcib_release_msix, thunder_pem_release_msix), 187 DEVMETHOD(pcib_alloc_msi, thunder_pem_alloc_msi), 188 DEVMETHOD(pcib_release_msi, thunder_pem_release_msi), 189 DEVMETHOD(pcib_map_msi, thunder_pem_map_msi), 190 DEVMETHOD(pcib_get_id, thunder_pem_get_id), 191 192 DEVMETHOD_END 193 }; 194 195 DEFINE_CLASS_0(pcib, thunder_pem_driver, thunder_pem_methods, 196 sizeof(struct thunder_pem_softc)); 197 198 static devclass_t thunder_pem_devclass; 199 extern struct bus_space memmap_bus; 200 201 DRIVER_MODULE(thunder_pem, pci, thunder_pem_driver, thunder_pem_devclass, 0, 0); 202 MODULE_DEPEND(thunder_pem, pci, 1, 1, 1); 203 204 static int 205 thunder_pem_maxslots(device_t dev) 206 { 207 208 #if 0 209 /* max slots per bus acc. to standard */ 210 return (PCI_SLOTMAX); 211 #else 212 /* 213 * ARM64TODO Workaround - otherwise an em(4) interface appears to be 214 * present on every PCI function on the bus to which it is connected 215 */ 216 return (0); 217 #endif 218 } 219 220 static int 221 thunder_pem_read_ivar(device_t dev, device_t child, int index, 222 uintptr_t *result) 223 { 224 struct thunder_pem_softc *sc; 225 int secondary_bus = 0; 226 227 sc = device_get_softc(dev); 228 229 if (index == PCIB_IVAR_BUS) { 230 secondary_bus = thunder_pem_config_reg_read(sc, PCIERC_CFG006); 231 *result = PCIERC_CFG006_SEC_BUS(secondary_bus); 232 return (0); 233 } 234 if (index == PCIB_IVAR_DOMAIN) { 235 *result = sc->id; 236 return (0); 237 } 238 239 return (ENOENT); 240 } 241 242 static int 243 thunder_pem_write_ivar(device_t dev, device_t child, int index, 244 uintptr_t value) 245 { 246 247 return (ENOENT); 248 } 249 250 static int 251 thunder_pem_activate_resource(device_t dev, device_t child, int type, int rid, 252 struct resource *r) 253 { 254 int err; 255 bus_addr_t paddr; 256 bus_size_t psize; 257 bus_space_handle_t vaddr; 258 struct thunder_pem_softc *sc; 259 260 if ((err = rman_activate_resource(r)) != 0) 261 return (err); 262 263 sc = device_get_softc(dev); 264 265 /* 266 * If this is a memory resource, map it into the kernel. 267 */ 268 if (type == SYS_RES_MEMORY || type == SYS_RES_IOPORT) { 269 paddr = (bus_addr_t)rman_get_start(r); 270 psize = (bus_size_t)rman_get_size(r); 271 272 paddr = range_addr_pci_to_phys(sc->ranges, paddr); 273 274 err = bus_space_map(&memmap_bus, paddr, psize, 0, &vaddr); 275 if (err != 0) { 276 rman_deactivate_resource(r); 277 return (err); 278 } 279 rman_set_bustag(r, &memmap_bus); 280 rman_set_virtual(r, (void *)vaddr); 281 rman_set_bushandle(r, vaddr); 282 } 283 return (0); 284 } 285 286 /* 287 * This function is an exact copy of nexus_deactivate_resource() 288 * Keep it up-to-date with all changes in nexus. To be removed 289 * once bus-mapping interface is developed. 290 */ 291 static int 292 thunder_pem_deactivate_resource(device_t bus, device_t child, int type, int rid, 293 struct resource *r) 294 { 295 bus_size_t psize; 296 bus_space_handle_t vaddr; 297 298 psize = (bus_size_t)rman_get_size(r); 299 vaddr = rman_get_bushandle(r); 300 301 if (vaddr != 0) { 302 bus_space_unmap(&memmap_bus, vaddr, psize); 303 rman_set_virtual(r, NULL); 304 rman_set_bushandle(r, 0); 305 } 306 307 return (rman_deactivate_resource(r)); 308 } 309 310 static int 311 thunder_pem_adjust_resource(device_t dev, device_t child, int type, 312 struct resource *res, rman_res_t start, rman_res_t end) 313 { 314 struct thunder_pem_softc *sc; 315 struct rman *rm; 316 317 sc = device_get_softc(dev); 318 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 319 if (type == PCI_RES_BUS) 320 return (pci_domain_adjust_bus(sc->id, child, res, start, end)); 321 #endif 322 323 rm = thunder_pem_rman(sc, type); 324 if (rm == NULL) 325 return (bus_generic_adjust_resource(dev, child, type, res, 326 start, end)); 327 if (!rman_is_region_manager(res, rm)) 328 /* 329 * This means a child device has a memory or I/O 330 * resource not from you which shouldn't happen. 331 */ 332 return (EINVAL); 333 return (rman_adjust_resource(res, start, end)); 334 } 335 336 static bus_dma_tag_t 337 thunder_pem_get_dma_tag(device_t dev, device_t child) 338 { 339 struct thunder_pem_softc *sc; 340 341 sc = device_get_softc(dev); 342 return (sc->dmat); 343 } 344 345 static int 346 thunder_pem_alloc_msi(device_t pci, device_t child, int count, int maxcount, 347 int *irqs) 348 { 349 device_t bus; 350 351 bus = device_get_parent(pci); 352 return (PCIB_ALLOC_MSI(device_get_parent(bus), child, count, maxcount, 353 irqs)); 354 } 355 356 static int 357 thunder_pem_release_msi(device_t pci, device_t child, int count, int *irqs) 358 { 359 device_t bus; 360 361 bus = device_get_parent(pci); 362 return (PCIB_RELEASE_MSI(device_get_parent(bus), child, count, irqs)); 363 } 364 365 static int 366 thunder_pem_alloc_msix(device_t pci, device_t child, int *irq) 367 { 368 device_t bus; 369 370 bus = device_get_parent(pci); 371 return (PCIB_ALLOC_MSIX(device_get_parent(bus), child, irq)); 372 } 373 374 static int 375 thunder_pem_release_msix(device_t pci, device_t child, int irq) 376 { 377 device_t bus; 378 379 bus = device_get_parent(pci); 380 return (PCIB_RELEASE_MSIX(device_get_parent(bus), child, irq)); 381 } 382 383 static int 384 thunder_pem_map_msi(device_t pci, device_t child, int irq, uint64_t *addr, 385 uint32_t *data) 386 { 387 device_t bus; 388 389 bus = device_get_parent(pci); 390 return (PCIB_MAP_MSI(device_get_parent(bus), child, irq, addr, data)); 391 } 392 393 static int 394 thunder_pem_get_id(device_t pci, device_t child, enum pci_id_type type, 395 uintptr_t *id) 396 { 397 int bsf; 398 int pem; 399 400 if (type != PCI_ID_MSI) 401 return (pcib_get_id(pci, child, type, id)); 402 403 bsf = pci_get_rid(child); 404 405 /* PEM (PCIe MAC/root complex) number is equal to domain */ 406 pem = pci_get_domain(child); 407 408 /* 409 * Set appropriate device ID (passed by the HW along with 410 * the transaction to memory) for different root complex 411 * numbers using hard-coded domain portion for each group. 412 */ 413 if (pem < 3) 414 *id = (0x1 << PCI_RID_DOMAIN_SHIFT) | bsf; 415 else if (pem < 6) 416 *id = (0x3 << PCI_RID_DOMAIN_SHIFT) | bsf; 417 else if (pem < 9) 418 *id = (0x9 << PCI_RID_DOMAIN_SHIFT) | bsf; 419 else if (pem < 12) 420 *id = (0xB << PCI_RID_DOMAIN_SHIFT) | bsf; 421 else 422 return (ENXIO); 423 424 return (0); 425 } 426 427 static int 428 thunder_pem_identify(device_t dev) 429 { 430 struct thunder_pem_softc *sc; 431 rman_res_t start; 432 433 sc = device_get_softc(dev); 434 start = rman_get_start(sc->reg); 435 436 /* Calculate PEM designations from its address */ 437 sc->node = (start >> SLI_NODE_SHIFT) & SLI_NODE_MASK; 438 sc->id = ((start >> SLI_ID_SHIFT) & SLI_ID_MASK) + 439 (SLI_PEMS_PER_NODE * sc->node); 440 sc->sli = sc->id % SLI_PEMS_PER_GROUP; 441 sc->sli_group = (sc->id / SLI_PEMS_PER_GROUP) % SLI_GROUPS_PER_NODE; 442 sc->sli_window_base = SLI_BASE | 443 (((uint64_t)sc->node) << SLI_NODE_SHIFT) | 444 ((uint64_t)sc->sli_group << SLI_GROUP_SHIFT); 445 sc->sli_window_base += SLI_WINDOW_SPACING * sc->sli; 446 447 return (0); 448 } 449 450 static void 451 thunder_pem_slix_s2m_regx_acc_modify(struct thunder_pem_softc *sc, 452 int sli_group, int slix) 453 { 454 uint64_t regval; 455 bus_space_handle_t handle = 0; 456 457 KASSERT(slix >= 0 && slix <= SLI_ACC_REG_CNT, ("Invalid SLI index")); 458 459 if (sli_group == 0) 460 handle = sli0_s2m_regx_base; 461 else if (sli_group == 1) 462 handle = sli1_s2m_regx_base; 463 else 464 device_printf(sc->dev, "SLI group is not correct\n"); 465 466 if (handle) { 467 /* Clear lower 32-bits of the SLIx register */ 468 regval = bus_space_read_8(sc->reg_bst, handle, 469 PEM_CFG_SLIX_TO_REG(slix)); 470 regval &= ~(0xFFFFFFFFUL); 471 bus_space_write_8(sc->reg_bst, handle, 472 PEM_CFG_SLIX_TO_REG(slix), regval); 473 } 474 } 475 476 static int 477 thunder_pem_link_init(struct thunder_pem_softc *sc) 478 { 479 uint64_t regval; 480 481 /* check whether PEM is safe to access. */ 482 regval = bus_space_read_8(sc->reg_bst, sc->reg_bsh, PEM_ON_REG); 483 if ((regval & PEM_CFG_LINK_MASK) != PEM_CFG_LINK_RDY) { 484 device_printf(sc->dev, "PEM%d is not ON\n", sc->id); 485 return (ENXIO); 486 } 487 488 regval = bus_space_read_8(sc->reg_bst, sc->reg_bsh, PEM_CTL_STATUS); 489 regval |= PEM_LINK_ENABLE; 490 bus_space_write_8(sc->reg_bst, sc->reg_bsh, PEM_CTL_STATUS, regval); 491 492 /* Wait 1ms as per Cavium specification */ 493 DELAY(1000); 494 495 regval = thunder_pem_config_reg_read(sc, PCIERC_CFG032); 496 497 if (((regval & PEM_LINK_DLLA) == 0) || ((regval & PEM_LINK_LT) != 0)) { 498 device_printf(sc->dev, "PCIe RC: Port %d Link Timeout\n", 499 sc->id); 500 return (ENXIO); 501 } 502 503 return (0); 504 } 505 506 static int 507 thunder_pem_init(struct thunder_pem_softc *sc) 508 { 509 int i, retval = 0; 510 511 retval = thunder_pem_link_init(sc); 512 if (retval) { 513 device_printf(sc->dev, "%s failed\n", __func__); 514 return retval; 515 } 516 517 /* To support 32-bit PCIe devices, set S2M_REGx_ACC[BA]=0x0 */ 518 for (i = 0; i < SLI_ACC_REG_CNT; i++) { 519 thunder_pem_slix_s2m_regx_acc_modify(sc, sc->sli_group, i); 520 } 521 522 return (retval); 523 } 524 525 static uint64_t 526 thunder_pem_config_reg_read(struct thunder_pem_softc *sc, int reg) 527 { 528 uint64_t data; 529 530 /* Write to ADDR register */ 531 bus_space_write_8(sc->reg_bst, sc->reg_bsh, PEM_CFG_RD, 532 PEM_CFG_RD_REG_ALIGN(reg)); 533 bus_space_barrier(sc->reg_bst, sc->reg_bsh, PEM_CFG_RD, 8, 534 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 535 /* Read from DATA register */ 536 data = PEM_CFG_RD_REG_DATA(bus_space_read_8(sc->reg_bst, sc->reg_bsh, 537 PEM_CFG_RD)); 538 539 return (data); 540 } 541 542 static uint32_t 543 thunder_pem_read_config(device_t dev, u_int bus, u_int slot, 544 u_int func, u_int reg, int bytes) 545 { 546 uint64_t offset; 547 uint32_t data; 548 struct thunder_pem_softc *sc; 549 bus_space_tag_t t; 550 bus_space_handle_t h; 551 552 if ((bus > PCI_BUSMAX) || (slot > PCI_SLOTMAX) || 553 (func > PCI_FUNCMAX) || (reg > PCIE_REGMAX)) 554 return (~0U); 555 556 sc = device_get_softc(dev); 557 558 /* Calculate offset */ 559 offset = (bus << PEM_BUS_SHIFT) | (slot << PEM_SLOT_SHIFT) | 560 (func << PEM_FUNC_SHIFT); 561 t = sc->reg_bst; 562 h = sc->pem_sli_base; 563 564 bus_space_map(sc->reg_bst, sc->sli_window_base + offset, 565 PCIE_REGMAX, 0, &h); 566 567 switch (bytes) { 568 case 1: 569 data = bus_space_read_1(t, h, reg); 570 break; 571 case 2: 572 data = le16toh(bus_space_read_2(t, h, reg)); 573 break; 574 case 4: 575 data = le32toh(bus_space_read_4(t, h, reg)); 576 break; 577 default: 578 data = ~0U; 579 break; 580 } 581 582 bus_space_unmap(sc->reg_bst, h, PCIE_REGMAX); 583 584 return (data); 585 } 586 587 static void 588 thunder_pem_write_config(device_t dev, u_int bus, u_int slot, 589 u_int func, u_int reg, uint32_t val, int bytes) 590 { 591 uint64_t offset; 592 struct thunder_pem_softc *sc; 593 bus_space_tag_t t; 594 bus_space_handle_t h; 595 596 if ((bus > PCI_BUSMAX) || (slot > PCI_SLOTMAX) || 597 (func > PCI_FUNCMAX) || (reg > PCIE_REGMAX)) 598 return; 599 600 sc = device_get_softc(dev); 601 602 /* Calculate offset */ 603 offset = (bus << PEM_BUS_SHIFT) | (slot << PEM_SLOT_SHIFT) | 604 (func << PEM_FUNC_SHIFT); 605 t = sc->reg_bst; 606 h = sc->pem_sli_base; 607 608 bus_space_map(sc->reg_bst, sc->sli_window_base + offset, 609 PCIE_REGMAX, 0, &h); 610 611 switch (bytes) { 612 case 1: 613 bus_space_write_1(t, h, reg, val); 614 break; 615 case 2: 616 bus_space_write_2(t, h, reg, htole16(val)); 617 break; 618 case 4: 619 bus_space_write_4(t, h, reg, htole32(val)); 620 break; 621 default: 622 break; 623 } 624 625 bus_space_unmap(sc->reg_bst, h, PCIE_REGMAX); 626 } 627 628 static struct resource * 629 thunder_pem_alloc_resource(device_t dev, device_t child, int type, int *rid, 630 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 631 { 632 struct thunder_pem_softc *sc = device_get_softc(dev); 633 struct rman *rm = NULL; 634 struct resource *res; 635 device_t parent_dev; 636 637 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 638 if (type == PCI_RES_BUS) 639 return (pci_domain_alloc_bus(sc->id, child, rid, start, end, 640 count, flags)); 641 #endif 642 rm = thunder_pem_rman(sc, type); 643 if (rm == NULL) { 644 /* Find parent device. On ThunderX we know an exact path. */ 645 parent_dev = device_get_parent(device_get_parent(dev)); 646 return (BUS_ALLOC_RESOURCE(parent_dev, dev, type, rid, start, 647 end, count, flags)); 648 } 649 650 if (!RMAN_IS_DEFAULT_RANGE(start, end)) { 651 /* 652 * We might get PHYS addresses here inherited from EFI. 653 * Convert to PCI if necessary. 654 */ 655 if (range_addr_is_phys(sc->ranges, start, count)) { 656 start = range_addr_phys_to_pci(sc->ranges, start); 657 end = start + count - 1; 658 } 659 } 660 661 if (bootverbose) { 662 device_printf(dev, 663 "thunder_pem_alloc_resource: start=%#lx, end=%#lx, count=%#lx\n", 664 start, end, count); 665 } 666 667 res = rman_reserve_resource(rm, start, end, count, flags, child); 668 if (res == NULL) 669 goto fail; 670 671 rman_set_rid(res, *rid); 672 673 if (flags & RF_ACTIVE) 674 if (bus_activate_resource(child, type, *rid, res)) { 675 rman_release_resource(res); 676 goto fail; 677 } 678 679 return (res); 680 681 fail: 682 if (bootverbose) { 683 device_printf(dev, "%s FAIL: type=%d, rid=%d, " 684 "start=%016lx, end=%016lx, count=%016lx, flags=%x\n", 685 __func__, type, *rid, start, end, count, flags); 686 } 687 688 return (NULL); 689 } 690 691 static int 692 thunder_pem_release_resource(device_t dev, device_t child, int type, int rid, 693 struct resource *res) 694 { 695 device_t parent_dev; 696 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 697 struct thunder_pem_softc *sc = device_get_softc(dev); 698 699 if (type == PCI_RES_BUS) 700 return (pci_domain_release_bus(sc->id, child, rid, res)); 701 #endif 702 /* Find parent device. On ThunderX we know an exact path. */ 703 parent_dev = device_get_parent(device_get_parent(dev)); 704 705 if ((type != SYS_RES_MEMORY) && (type != SYS_RES_IOPORT)) 706 return (BUS_RELEASE_RESOURCE(parent_dev, child, 707 type, rid, res)); 708 709 return (rman_release_resource(res)); 710 } 711 712 static struct rman * 713 thunder_pem_rman(struct thunder_pem_softc *sc, int type) 714 { 715 716 switch (type) { 717 case SYS_RES_IOPORT: 718 return (&sc->io_rman); 719 case SYS_RES_MEMORY: 720 return (&sc->mem_rman); 721 default: 722 break; 723 } 724 725 return (NULL); 726 } 727 728 static int 729 thunder_pem_probe(device_t dev) 730 { 731 uint16_t pci_vendor_id; 732 uint16_t pci_device_id; 733 734 pci_vendor_id = pci_get_vendor(dev); 735 pci_device_id = pci_get_device(dev); 736 737 if ((pci_vendor_id == THUNDER_PEM_VENDOR_ID) && 738 (pci_device_id == THUNDER_PEM_DEVICE_ID)) { 739 device_set_desc_copy(dev, THUNDER_PEM_DESC); 740 return (0); 741 } 742 743 return (ENXIO); 744 } 745 746 static int 747 thunder_pem_attach(device_t dev) 748 { 749 devclass_t pci_class; 750 device_t parent; 751 struct thunder_pem_softc *sc; 752 int error; 753 int rid; 754 int tuple; 755 uint64_t base, size; 756 struct rman *rman; 757 758 sc = device_get_softc(dev); 759 sc->dev = dev; 760 761 /* Allocate memory for resource */ 762 pci_class = devclass_find("pci"); 763 parent = device_get_parent(dev); 764 if (device_get_devclass(parent) == pci_class) 765 rid = PCIR_BAR(0); 766 else 767 rid = RID_PEM_SPACE; 768 769 sc->reg = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 770 &rid, RF_ACTIVE); 771 if (sc->reg == NULL) { 772 device_printf(dev, "Failed to allocate resource\n"); 773 return (ENXIO); 774 } 775 sc->reg_bst = rman_get_bustag(sc->reg); 776 sc->reg_bsh = rman_get_bushandle(sc->reg); 777 778 /* Create the parent DMA tag to pass down the coherent flag */ 779 error = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 780 1, 0, /* alignment, bounds */ 781 BUS_SPACE_MAXADDR, /* lowaddr */ 782 BUS_SPACE_MAXADDR, /* highaddr */ 783 NULL, NULL, /* filter, filterarg */ 784 BUS_SPACE_MAXSIZE, /* maxsize */ 785 BUS_SPACE_UNRESTRICTED, /* nsegments */ 786 BUS_SPACE_MAXSIZE, /* maxsegsize */ 787 BUS_DMA_COHERENT, /* flags */ 788 NULL, NULL, /* lockfunc, lockarg */ 789 &sc->dmat); 790 if (error != 0) 791 return (error); 792 793 /* Map SLI, do it only once */ 794 if (!sli0_s2m_regx_base) { 795 bus_space_map(sc->reg_bst, SLIX_S2M_REGX_ACC, 796 SLIX_S2M_REGX_ACC_SIZE, 0, &sli0_s2m_regx_base); 797 } 798 if (!sli1_s2m_regx_base) { 799 bus_space_map(sc->reg_bst, SLIX_S2M_REGX_ACC + 800 SLIX_S2M_REGX_ACC_SPACING, SLIX_S2M_REGX_ACC_SIZE, 0, 801 &sli1_s2m_regx_base); 802 } 803 804 if ((sli0_s2m_regx_base == 0) || (sli1_s2m_regx_base == 0)) { 805 device_printf(dev, 806 "bus_space_map failed to map slix_s2m_regx_base\n"); 807 goto fail; 808 } 809 810 /* Identify PEM */ 811 if (thunder_pem_identify(dev) != 0) 812 goto fail; 813 814 /* Initialize rman and allocate regions */ 815 sc->mem_rman.rm_type = RMAN_ARRAY; 816 sc->mem_rman.rm_descr = "PEM PCIe Memory"; 817 error = rman_init(&sc->mem_rman); 818 if (error != 0) { 819 device_printf(dev, "memory rman_init() failed. error = %d\n", 820 error); 821 goto fail; 822 } 823 sc->io_rman.rm_type = RMAN_ARRAY; 824 sc->io_rman.rm_descr = "PEM PCIe IO"; 825 error = rman_init(&sc->io_rman); 826 if (error != 0) { 827 device_printf(dev, "IO rman_init() failed. error = %d\n", 828 error); 829 goto fail_mem; 830 } 831 832 /* 833 * We ignore the values that may have been provided in FDT 834 * and configure ranges according to the below formula 835 * for all types of devices. This is because some DTBs provided 836 * by EFI do not have proper ranges property or don't have them 837 * at all. 838 */ 839 /* Fill memory window */ 840 sc->ranges[0].pci_base = PCI_MEMORY_BASE; 841 sc->ranges[0].size = PCI_MEMORY_SIZE; 842 sc->ranges[0].phys_base = sc->sli_window_base + SLI_PCI_OFFSET + 843 sc->ranges[0].pci_base; 844 sc->ranges[0].flags = SYS_RES_MEMORY; 845 846 /* Fill IO window */ 847 sc->ranges[1].pci_base = PCI_IO_BASE; 848 sc->ranges[1].size = PCI_IO_SIZE; 849 sc->ranges[1].phys_base = sc->sli_window_base + SLI_PCI_OFFSET + 850 sc->ranges[1].pci_base; 851 sc->ranges[1].flags = SYS_RES_IOPORT; 852 853 for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) { 854 base = sc->ranges[tuple].pci_base; 855 size = sc->ranges[tuple].size; 856 if (size == 0) 857 continue; /* empty range element */ 858 859 rman = thunder_pem_rman(sc, sc->ranges[tuple].flags); 860 if (rman != NULL) 861 error = rman_manage_region(rman, base, 862 base + size - 1); 863 else 864 error = EINVAL; 865 if (error) { 866 device_printf(dev, 867 "rman_manage_region() failed. error = %d\n", error); 868 rman_fini(&sc->mem_rman); 869 return (error); 870 } 871 if (bootverbose) { 872 device_printf(dev, 873 "\tPCI addr: 0x%jx, CPU addr: 0x%jx, Size: 0x%jx, Flags:0x%jx\n", 874 sc->ranges[tuple].pci_base, 875 sc->ranges[tuple].phys_base, 876 sc->ranges[tuple].size, 877 sc->ranges[tuple].flags); 878 } 879 } 880 881 if (thunder_pem_init(sc)) { 882 device_printf(dev, "Failure during PEM init\n"); 883 goto fail_io; 884 } 885 886 device_add_child(dev, "pci", -1); 887 888 return (bus_generic_attach(dev)); 889 890 fail_io: 891 rman_fini(&sc->io_rman); 892 fail_mem: 893 rman_fini(&sc->mem_rman); 894 fail: 895 bus_free_resource(dev, SYS_RES_MEMORY, sc->reg); 896 return (ENXIO); 897 } 898 899 static void 900 thunder_pem_release_all(device_t dev) 901 { 902 struct thunder_pem_softc *sc; 903 904 sc = device_get_softc(dev); 905 906 rman_fini(&sc->io_rman); 907 rman_fini(&sc->mem_rman); 908 909 if (sc->reg != NULL) 910 bus_free_resource(dev, SYS_RES_MEMORY, sc->reg); 911 } 912 913 static int 914 thunder_pem_detach(device_t dev) 915 { 916 917 thunder_pem_release_all(dev); 918 919 return (0); 920 } 921