1 /*- 2 * Copyright (c) 2015 The FreeBSD Foundation 3 * All rights reserved. 4 * 5 * This software was developed by Semihalf under 6 * the sponsorship of the FreeBSD Foundation. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* PCIe external MAC root complex driver (PEM) for Cavium Thunder SOC */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include "opt_platform.h" 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/bus.h> 40 #include <sys/kernel.h> 41 #include <sys/malloc.h> 42 #include <sys/module.h> 43 #include <sys/rman.h> 44 #include <sys/endian.h> 45 46 #ifdef FDT 47 #include <dev/ofw/openfirm.h> 48 #include <dev/ofw/ofw_bus.h> 49 #include <dev/ofw/ofw_bus_subr.h> 50 #include <dev/ofw/ofw_pci.h> 51 #endif 52 53 #include <dev/pci/pcivar.h> 54 #include <dev/pci/pcireg.h> 55 #include <dev/pci/pci_host_generic.h> 56 57 #include <machine/bus.h> 58 #include <machine/resource.h> 59 #include <machine/smp.h> 60 #include <machine/intr.h> 61 62 #include <arm64/cavium/thunder_pcie_common.h> 63 #include <arm64/cavium/thunder_pcie_pem.h> 64 #include "pcib_if.h" 65 66 #define THUNDER_PEM_DEVICE_ID 0xa020 67 #define THUNDER_PEM_VENDOR_ID 0x177d 68 69 /* ThunderX specific defines */ 70 #define THUNDER_PEMn_REG_BASE(unit) (0x87e0c0000000UL | ((unit) << 24)) 71 #define PCIERC_CFG002 0x08 72 #define PCIERC_CFG006 0x18 73 #define PCIERC_CFG032 0x80 74 #define PCIERC_CFG006_SEC_BUS(reg) (((reg) >> 8) & 0xFF) 75 #define PEM_CFG_RD_REG_ALIGN(reg) ((reg) & ~0x3) 76 #define PEM_CFG_RD_REG_DATA(val) (((val) >> 32) & 0xFFFFFFFF) 77 #define PEM_CFG_RD 0x30 78 #define PEM_CFG_LINK_MASK 0x3 79 #define PEM_CFG_LINK_RDY 0x3 80 #define PEM_CFG_SLIX_TO_REG(slix) ((slix) << 4) 81 #define SBNUM_OFFSET 0x8 82 #define SBNUM_MASK 0xFF 83 #define PEM_ON_REG 0x420 84 #define PEM_CTL_STATUS 0x0 85 #define PEM_LINK_ENABLE (1 << 4) 86 #define PEM_LINK_DLLA (1 << 29) 87 #define PEM_LINK_LT (1 << 27) 88 #define PEM_BUS_SHIFT (24) 89 #define PEM_SLOT_SHIFT (19) 90 #define PEM_FUNC_SHIFT (16) 91 #define SLIX_S2M_REGX_ACC 0x874001000000UL 92 #define SLIX_S2M_REGX_ACC_SIZE 0x1000 93 #define SLIX_S2M_REGX_ACC_SPACING 0x001000000000UL 94 #define SLI_BASE 0x880000000000UL 95 #define SLI_WINDOW_SPACING 0x004000000000UL 96 #define SLI_PCI_OFFSET 0x001000000000UL 97 #define SLI_NODE_SHIFT (44) 98 #define SLI_NODE_MASK (3) 99 #define SLI_GROUP_SHIFT (40) 100 #define SLI_ID_SHIFT (24) 101 #define SLI_ID_MASK (7) 102 #define SLI_PEMS_PER_GROUP (3) 103 #define SLI_GROUPS_PER_NODE (2) 104 #define SLI_PEMS_PER_NODE (SLI_PEMS_PER_GROUP * SLI_GROUPS_PER_NODE) 105 #define SLI_ACC_REG_CNT (256) 106 107 /* 108 * Each PEM device creates its own bus with 109 * own address translation, so we can adjust bus addresses 110 * as we want. To support 32-bit cards let's assume 111 * PCI window assignment looks as following: 112 * 113 * 0x00000000 - 0x000FFFFF IO 114 * 0x00100000 - 0xFFFFFFFF Memory 115 */ 116 #define PCI_IO_BASE 0x00000000UL 117 #define PCI_IO_SIZE 0x00100000UL 118 #define PCI_MEMORY_BASE PCI_IO_SIZE 119 #define PCI_MEMORY_SIZE 0xFFF00000UL 120 121 #define RID_PEM_SPACE 1 122 123 static int thunder_pem_activate_resource(device_t, device_t, int, int, 124 struct resource *); 125 static int thunder_pem_adjust_resource(device_t, device_t, int, 126 struct resource *, rman_res_t, rman_res_t); 127 static struct resource * thunder_pem_alloc_resource(device_t, device_t, int, 128 int *, rman_res_t, rman_res_t, rman_res_t, u_int); 129 static int thunder_pem_attach(device_t); 130 static int thunder_pem_deactivate_resource(device_t, device_t, int, int, 131 struct resource *); 132 static int thunder_pem_detach(device_t); 133 static uint64_t thunder_pem_config_reg_read(struct thunder_pem_softc *, int); 134 static int thunder_pem_link_init(struct thunder_pem_softc *); 135 static int thunder_pem_maxslots(device_t); 136 static int thunder_pem_probe(device_t); 137 static uint32_t thunder_pem_read_config(device_t, u_int, u_int, u_int, u_int, 138 int); 139 static int thunder_pem_read_ivar(device_t, device_t, int, uintptr_t *); 140 static void thunder_pem_release_all(device_t); 141 static int thunder_pem_release_resource(device_t, device_t, int, int, 142 struct resource *); 143 static struct rman * thunder_pem_rman(struct thunder_pem_softc *, int); 144 static void thunder_pem_slix_s2m_regx_acc_modify(struct thunder_pem_softc *, 145 int, int); 146 static void thunder_pem_write_config(device_t, u_int, u_int, u_int, u_int, 147 uint32_t, int); 148 static int thunder_pem_write_ivar(device_t, device_t, int, uintptr_t); 149 150 /* Global handlers for SLI interface */ 151 static bus_space_handle_t sli0_s2m_regx_base = 0; 152 static bus_space_handle_t sli1_s2m_regx_base = 0; 153 154 static device_method_t thunder_pem_methods[] = { 155 /* Device interface */ 156 DEVMETHOD(device_probe, thunder_pem_probe), 157 DEVMETHOD(device_attach, thunder_pem_attach), 158 DEVMETHOD(device_detach, thunder_pem_detach), 159 DEVMETHOD(pcib_maxslots, thunder_pem_maxslots), 160 DEVMETHOD(pcib_read_config, thunder_pem_read_config), 161 DEVMETHOD(pcib_write_config, thunder_pem_write_config), 162 DEVMETHOD(bus_read_ivar, thunder_pem_read_ivar), 163 DEVMETHOD(bus_write_ivar, thunder_pem_write_ivar), 164 DEVMETHOD(bus_alloc_resource, thunder_pem_alloc_resource), 165 DEVMETHOD(bus_release_resource, thunder_pem_release_resource), 166 DEVMETHOD(bus_adjust_resource, thunder_pem_adjust_resource), 167 DEVMETHOD(bus_activate_resource, thunder_pem_activate_resource), 168 DEVMETHOD(bus_deactivate_resource, thunder_pem_deactivate_resource), 169 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 170 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 171 172 DEVMETHOD(pcib_map_msi, arm_map_msi), 173 DEVMETHOD(pcib_alloc_msix, arm_alloc_msix), 174 DEVMETHOD(pcib_release_msix, arm_release_msix), 175 DEVMETHOD(pcib_alloc_msi, arm_alloc_msi), 176 DEVMETHOD(pcib_release_msi, arm_release_msi), 177 DEVMETHOD_END 178 }; 179 180 DEFINE_CLASS_0(pcib, thunder_pem_driver, thunder_pem_methods, 181 sizeof(struct thunder_pem_softc)); 182 183 static devclass_t thunder_pem_devclass; 184 extern struct bus_space memmap_bus; 185 186 DRIVER_MODULE(thunder_pem, pci, thunder_pem_driver, thunder_pem_devclass, 0, 0); 187 MODULE_DEPEND(thunder_pem, pci, 1, 1, 1); 188 189 static int 190 thunder_pem_maxslots(device_t dev) 191 { 192 193 #if 0 194 /* max slots per bus acc. to standard */ 195 return (PCI_SLOTMAX); 196 #else 197 /* 198 * ARM64TODO Workaround - otherwise an em(4) interface appears to be 199 * present on every PCI function on the bus to which it is connected 200 */ 201 return (0); 202 #endif 203 } 204 205 static int 206 thunder_pem_read_ivar(device_t dev, device_t child, int index, 207 uintptr_t *result) 208 { 209 struct thunder_pem_softc *sc; 210 int secondary_bus = 0; 211 212 sc = device_get_softc(dev); 213 214 if (index == PCIB_IVAR_BUS) { 215 secondary_bus = thunder_pem_config_reg_read(sc, PCIERC_CFG006); 216 *result = PCIERC_CFG006_SEC_BUS(secondary_bus); 217 return (0); 218 } 219 if (index == PCIB_IVAR_DOMAIN) { 220 *result = sc->id; 221 return (0); 222 } 223 224 return (ENOENT); 225 } 226 227 static int 228 thunder_pem_write_ivar(device_t dev, device_t child, int index, 229 uintptr_t value) 230 { 231 232 return (ENOENT); 233 } 234 235 static int 236 thunder_pem_activate_resource(device_t dev, device_t child, int type, int rid, 237 struct resource *r) 238 { 239 int err; 240 bus_addr_t paddr; 241 bus_size_t psize; 242 bus_space_handle_t vaddr; 243 struct thunder_pem_softc *sc; 244 245 if ((err = rman_activate_resource(r)) != 0) 246 return (err); 247 248 sc = device_get_softc(dev); 249 250 /* 251 * If this is a memory resource, map it into the kernel. 252 */ 253 if (type == SYS_RES_MEMORY || type == SYS_RES_IOPORT) { 254 paddr = (bus_addr_t)rman_get_start(r); 255 psize = (bus_size_t)rman_get_size(r); 256 257 paddr = range_addr_pci_to_phys(sc->ranges, paddr); 258 259 err = bus_space_map(&memmap_bus, paddr, psize, 0, &vaddr); 260 if (err != 0) { 261 rman_deactivate_resource(r); 262 return (err); 263 } 264 rman_set_bustag(r, &memmap_bus); 265 rman_set_virtual(r, (void *)vaddr); 266 rman_set_bushandle(r, vaddr); 267 } 268 return (0); 269 } 270 271 /* 272 * This function is an exact copy of nexus_deactivate_resource() 273 * Keep it up-to-date with all changes in nexus. To be removed 274 * once bus-mapping interface is developed. 275 */ 276 static int 277 thunder_pem_deactivate_resource(device_t bus, device_t child, int type, int rid, 278 struct resource *r) 279 { 280 bus_size_t psize; 281 bus_space_handle_t vaddr; 282 283 psize = (bus_size_t)rman_get_size(r); 284 vaddr = rman_get_bushandle(r); 285 286 if (vaddr != 0) { 287 bus_space_unmap(&memmap_bus, vaddr, psize); 288 rman_set_virtual(r, NULL); 289 rman_set_bushandle(r, 0); 290 } 291 292 return (rman_deactivate_resource(r)); 293 } 294 295 static int 296 thunder_pem_adjust_resource(device_t dev, device_t child, int type, 297 struct resource *res, rman_res_t start, rman_res_t end) 298 { 299 struct thunder_pem_softc *sc; 300 struct rman *rm; 301 302 sc = device_get_softc(dev); 303 304 rm = thunder_pem_rman(sc, type); 305 if (rm == NULL) 306 return (bus_generic_adjust_resource(dev, child, type, res, 307 start, end)); 308 if (!rman_is_region_manager(res, rm)) 309 /* 310 * This means a child device has a memory or I/O 311 * resource not from you which shouldn't happen. 312 */ 313 return (EINVAL); 314 return (rman_adjust_resource(res, start, end)); 315 } 316 317 static int 318 thunder_pem_identify(device_t dev) 319 { 320 struct thunder_pem_softc *sc; 321 rman_res_t start; 322 323 sc = device_get_softc(dev); 324 start = rman_get_start(sc->reg); 325 326 /* Calculate PEM designations from its address */ 327 sc->node = (start >> SLI_NODE_SHIFT) & SLI_NODE_MASK; 328 sc->id = ((start >> SLI_ID_SHIFT) & SLI_ID_MASK) + 329 (SLI_PEMS_PER_NODE * sc->node); 330 sc->sli = sc->id % SLI_PEMS_PER_GROUP; 331 sc->sli_group = (sc->id / SLI_PEMS_PER_GROUP) % SLI_GROUPS_PER_NODE; 332 sc->sli_window_base = SLI_BASE | 333 (((uint64_t)sc->node) << SLI_NODE_SHIFT) | 334 ((uint64_t)sc->sli_group << SLI_GROUP_SHIFT); 335 sc->sli_window_base += SLI_WINDOW_SPACING * sc->sli; 336 337 return (0); 338 } 339 340 static void 341 thunder_pem_slix_s2m_regx_acc_modify(struct thunder_pem_softc *sc, 342 int sli_group, int slix) 343 { 344 uint64_t regval; 345 bus_space_handle_t handle = 0; 346 347 KASSERT(slix >= 0 && slix <= SLI_ACC_REG_CNT, ("Invalid SLI index")); 348 349 if (sli_group == 0) 350 handle = sli0_s2m_regx_base; 351 else if (sli_group == 1) 352 handle = sli1_s2m_regx_base; 353 else 354 device_printf(sc->dev, "SLI group is not correct\n"); 355 356 if (handle) { 357 /* Clear lower 32-bits of the SLIx register */ 358 regval = bus_space_read_8(sc->reg_bst, handle, 359 PEM_CFG_SLIX_TO_REG(slix)); 360 regval &= ~(0xFFFFFFFFUL); 361 bus_space_write_8(sc->reg_bst, handle, 362 PEM_CFG_SLIX_TO_REG(slix), regval); 363 } 364 } 365 366 static int 367 thunder_pem_link_init(struct thunder_pem_softc *sc) 368 { 369 uint64_t regval; 370 371 /* check whether PEM is safe to access. */ 372 regval = bus_space_read_8(sc->reg_bst, sc->reg_bsh, PEM_ON_REG); 373 if ((regval & PEM_CFG_LINK_MASK) != PEM_CFG_LINK_RDY) { 374 device_printf(sc->dev, "PEM%d is not ON\n", sc->id); 375 return (ENXIO); 376 } 377 378 regval = bus_space_read_8(sc->reg_bst, sc->reg_bsh, PEM_CTL_STATUS); 379 regval |= PEM_LINK_ENABLE; 380 bus_space_write_8(sc->reg_bst, sc->reg_bsh, PEM_CTL_STATUS, regval); 381 382 /* Wait 1ms as per Cavium specification */ 383 DELAY(1000); 384 385 regval = thunder_pem_config_reg_read(sc, PCIERC_CFG032); 386 387 if (((regval & PEM_LINK_DLLA) == 0) || ((regval & PEM_LINK_LT) != 0)) { 388 device_printf(sc->dev, "PCIe RC: Port %d Link Timeout\n", 389 sc->id); 390 return (ENXIO); 391 } 392 393 return (0); 394 } 395 396 static int 397 thunder_pem_init(struct thunder_pem_softc *sc) 398 { 399 int i, retval = 0; 400 401 retval = thunder_pem_link_init(sc); 402 if (retval) { 403 device_printf(sc->dev, "%s failed\n", __func__); 404 return retval; 405 } 406 407 /* To support 32-bit PCIe devices, set S2M_REGx_ACC[BA]=0x0 */ 408 for (i = 0; i < SLI_ACC_REG_CNT; i++) { 409 thunder_pem_slix_s2m_regx_acc_modify(sc, sc->sli_group, i); 410 } 411 412 return (retval); 413 } 414 415 static uint64_t 416 thunder_pem_config_reg_read(struct thunder_pem_softc *sc, int reg) 417 { 418 uint64_t data; 419 420 /* Write to ADDR register */ 421 bus_space_write_8(sc->reg_bst, sc->reg_bsh, PEM_CFG_RD, 422 PEM_CFG_RD_REG_ALIGN(reg)); 423 bus_space_barrier(sc->reg_bst, sc->reg_bsh, PEM_CFG_RD, 8, 424 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 425 /* Read from DATA register */ 426 data = PEM_CFG_RD_REG_DATA(bus_space_read_8(sc->reg_bst, sc->reg_bsh, 427 PEM_CFG_RD)); 428 429 return (data); 430 } 431 432 static uint32_t 433 thunder_pem_read_config(device_t dev, u_int bus, u_int slot, 434 u_int func, u_int reg, int bytes) 435 { 436 uint64_t offset; 437 uint32_t data; 438 struct thunder_pem_softc *sc; 439 bus_space_tag_t t; 440 bus_space_handle_t h; 441 442 if ((bus > PCI_BUSMAX) || (slot > PCI_SLOTMAX) || 443 (func > PCI_FUNCMAX) || (reg > PCIE_REGMAX)) 444 return (~0U); 445 446 sc = device_get_softc(dev); 447 448 /* Calculate offset */ 449 offset = (bus << PEM_BUS_SHIFT) | (slot << PEM_SLOT_SHIFT) | 450 (func << PEM_FUNC_SHIFT); 451 t = sc->reg_bst; 452 h = sc->pem_sli_base; 453 454 bus_space_map(sc->reg_bst, sc->sli_window_base + offset, 455 PCIE_REGMAX, 0, &h); 456 457 switch (bytes) { 458 case 1: 459 data = bus_space_read_1(t, h, reg); 460 break; 461 case 2: 462 data = le16toh(bus_space_read_2(t, h, reg)); 463 break; 464 case 4: 465 data = le32toh(bus_space_read_4(t, h, reg)); 466 break; 467 default: 468 data = ~0U; 469 break; 470 } 471 472 bus_space_unmap(sc->reg_bst, h, PCIE_REGMAX); 473 474 return (data); 475 } 476 477 static void 478 thunder_pem_write_config(device_t dev, u_int bus, u_int slot, 479 u_int func, u_int reg, uint32_t val, int bytes) 480 { 481 uint64_t offset; 482 struct thunder_pem_softc *sc; 483 bus_space_tag_t t; 484 bus_space_handle_t h; 485 486 if ((bus > PCI_BUSMAX) || (slot > PCI_SLOTMAX) || 487 (func > PCI_FUNCMAX) || (reg > PCIE_REGMAX)) 488 return; 489 490 sc = device_get_softc(dev); 491 492 /* Calculate offset */ 493 offset = (bus << PEM_BUS_SHIFT) | (slot << PEM_SLOT_SHIFT) | 494 (func << PEM_FUNC_SHIFT); 495 t = sc->reg_bst; 496 h = sc->pem_sli_base; 497 498 bus_space_map(sc->reg_bst, sc->sli_window_base + offset, 499 PCIE_REGMAX, 0, &h); 500 501 switch (bytes) { 502 case 1: 503 bus_space_write_1(t, h, reg, val); 504 break; 505 case 2: 506 bus_space_write_2(t, h, reg, htole16(val)); 507 break; 508 case 4: 509 bus_space_write_4(t, h, reg, htole32(val)); 510 break; 511 default: 512 break; 513 } 514 515 bus_space_unmap(sc->reg_bst, h, PCIE_REGMAX); 516 } 517 518 static struct resource * 519 thunder_pem_alloc_resource(device_t dev, device_t child, int type, int *rid, 520 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 521 { 522 struct thunder_pem_softc *sc = device_get_softc(dev); 523 struct rman *rm = NULL; 524 struct resource *res; 525 device_t parent_dev; 526 527 rm = thunder_pem_rman(sc, type); 528 if (rm == NULL) { 529 /* Find parent device. On ThunderX we know an exact path. */ 530 parent_dev = device_get_parent(device_get_parent(dev)); 531 return (BUS_ALLOC_RESOURCE(parent_dev, dev, type, rid, start, 532 end, count, flags)); 533 } 534 535 536 if (!RMAN_IS_DEFAULT_RANGE(start, end)) { 537 /* 538 * We might get PHYS addresses here inherited from EFI. 539 * Convert to PCI if necessary. 540 */ 541 if (range_addr_is_phys(sc->ranges, start, count)) { 542 start = range_addr_phys_to_pci(sc->ranges, start); 543 end = start + count - 1; 544 } 545 546 } 547 548 if (bootverbose) { 549 device_printf(dev, 550 "thunder_pem_alloc_resource: start=%#lx, end=%#lx, count=%#lx\n", 551 start, end, count); 552 } 553 554 res = rman_reserve_resource(rm, start, end, count, flags, child); 555 if (res == NULL) 556 goto fail; 557 558 rman_set_rid(res, *rid); 559 560 if (flags & RF_ACTIVE) 561 if (bus_activate_resource(child, type, *rid, res)) { 562 rman_release_resource(res); 563 goto fail; 564 } 565 566 return (res); 567 568 fail: 569 if (bootverbose) { 570 device_printf(dev, "%s FAIL: type=%d, rid=%d, " 571 "start=%016lx, end=%016lx, count=%016lx, flags=%x\n", 572 __func__, type, *rid, start, end, count, flags); 573 } 574 575 return (NULL); 576 } 577 578 static int 579 thunder_pem_release_resource(device_t dev, device_t child, int type, int rid, 580 struct resource *res) 581 { 582 device_t parent_dev; 583 584 /* Find parent device. On ThunderX we know an exact path. */ 585 parent_dev = device_get_parent(device_get_parent(dev)); 586 587 if ((type != SYS_RES_MEMORY) && (type != SYS_RES_IOPORT)) 588 return (BUS_RELEASE_RESOURCE(parent_dev, child, 589 type, rid, res)); 590 591 return (rman_release_resource(res)); 592 } 593 594 static struct rman * 595 thunder_pem_rman(struct thunder_pem_softc *sc, int type) 596 { 597 598 switch (type) { 599 case SYS_RES_IOPORT: 600 return (&sc->io_rman); 601 case SYS_RES_MEMORY: 602 return (&sc->mem_rman); 603 default: 604 break; 605 } 606 607 return (NULL); 608 } 609 610 static int 611 thunder_pem_probe(device_t dev) 612 { 613 uint16_t pci_vendor_id; 614 uint16_t pci_device_id; 615 616 pci_vendor_id = pci_get_vendor(dev); 617 pci_device_id = pci_get_device(dev); 618 619 if ((pci_vendor_id == THUNDER_PEM_VENDOR_ID) && 620 (pci_device_id == THUNDER_PEM_DEVICE_ID)) { 621 device_set_desc_copy(dev, THUNDER_PEM_DESC); 622 return (0); 623 } 624 625 return (ENXIO); 626 } 627 628 static int 629 thunder_pem_attach(device_t dev) 630 { 631 devclass_t pci_class; 632 device_t parent; 633 struct thunder_pem_softc *sc; 634 int error; 635 int rid; 636 int tuple; 637 uint64_t base, size; 638 struct rman *rman; 639 640 sc = device_get_softc(dev); 641 sc->dev = dev; 642 643 /* Allocate memory for resource */ 644 pci_class = devclass_find("pci"); 645 parent = device_get_parent(dev); 646 if (device_get_devclass(parent) == pci_class) 647 rid = PCIR_BAR(0); 648 else 649 rid = RID_PEM_SPACE; 650 651 sc->reg = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 652 &rid, RF_ACTIVE); 653 if (sc->reg == NULL) { 654 device_printf(dev, "Failed to allocate resource\n"); 655 return (ENXIO); 656 } 657 sc->reg_bst = rman_get_bustag(sc->reg); 658 sc->reg_bsh = rman_get_bushandle(sc->reg); 659 660 /* Map SLI, do it only once */ 661 if (!sli0_s2m_regx_base) { 662 bus_space_map(sc->reg_bst, SLIX_S2M_REGX_ACC, 663 SLIX_S2M_REGX_ACC_SIZE, 0, &sli0_s2m_regx_base); 664 } 665 if (!sli1_s2m_regx_base) { 666 bus_space_map(sc->reg_bst, SLIX_S2M_REGX_ACC + 667 SLIX_S2M_REGX_ACC_SPACING, SLIX_S2M_REGX_ACC_SIZE, 0, 668 &sli1_s2m_regx_base); 669 } 670 671 if ((sli0_s2m_regx_base == 0) || (sli1_s2m_regx_base == 0)) { 672 device_printf(dev, 673 "bus_space_map failed to map slix_s2m_regx_base\n"); 674 goto fail; 675 } 676 677 /* Identify PEM */ 678 if (thunder_pem_identify(dev) != 0) 679 goto fail; 680 681 /* Initialize rman and allocate regions */ 682 sc->mem_rman.rm_type = RMAN_ARRAY; 683 sc->mem_rman.rm_descr = "PEM PCIe Memory"; 684 error = rman_init(&sc->mem_rman); 685 if (error != 0) { 686 device_printf(dev, "memory rman_init() failed. error = %d\n", 687 error); 688 goto fail; 689 } 690 sc->io_rman.rm_type = RMAN_ARRAY; 691 sc->io_rman.rm_descr = "PEM PCIe IO"; 692 error = rman_init(&sc->io_rman); 693 if (error != 0) { 694 device_printf(dev, "IO rman_init() failed. error = %d\n", 695 error); 696 goto fail_mem; 697 } 698 699 /* 700 * We ignore the values that may have been provided in FDT 701 * and configure ranges according to the below formula 702 * for all types of devices. This is because some DTBs provided 703 * by EFI do not have proper ranges property or don't have them 704 * at all. 705 */ 706 /* Fill memory window */ 707 sc->ranges[0].pci_base = PCI_MEMORY_BASE; 708 sc->ranges[0].size = PCI_MEMORY_SIZE; 709 sc->ranges[0].phys_base = sc->sli_window_base + SLI_PCI_OFFSET + 710 sc->ranges[0].pci_base; 711 sc->ranges[0].flags = SYS_RES_MEMORY; 712 713 /* Fill IO window */ 714 sc->ranges[1].pci_base = PCI_IO_BASE; 715 sc->ranges[1].size = PCI_IO_SIZE; 716 sc->ranges[1].phys_base = sc->sli_window_base + SLI_PCI_OFFSET + 717 sc->ranges[1].pci_base; 718 sc->ranges[1].flags = SYS_RES_IOPORT; 719 720 for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) { 721 base = sc->ranges[tuple].pci_base; 722 size = sc->ranges[tuple].size; 723 if (size == 0) 724 continue; /* empty range element */ 725 726 rman = thunder_pem_rman(sc, sc->ranges[tuple].flags); 727 if (rman != NULL) 728 error = rman_manage_region(rman, base, 729 base + size - 1); 730 else 731 error = EINVAL; 732 if (error) { 733 device_printf(dev, 734 "rman_manage_region() failed. error = %d\n", error); 735 rman_fini(&sc->mem_rman); 736 return (error); 737 } 738 if (bootverbose) { 739 device_printf(dev, 740 "\tPCI addr: 0x%jx, CPU addr: 0x%jx, Size: 0x%jx, Flags:0x%jx\n", 741 sc->ranges[tuple].pci_base, 742 sc->ranges[tuple].phys_base, 743 sc->ranges[tuple].size, 744 sc->ranges[tuple].flags); 745 } 746 } 747 748 if (thunder_pem_init(sc)) { 749 device_printf(dev, "Failure during PEM init\n"); 750 goto fail_io; 751 } 752 753 device_add_child(dev, "pci", -1); 754 755 return (bus_generic_attach(dev)); 756 757 fail_io: 758 rman_fini(&sc->io_rman); 759 fail_mem: 760 rman_fini(&sc->mem_rman); 761 fail: 762 bus_free_resource(dev, SYS_RES_MEMORY, sc->reg); 763 return (ENXIO); 764 } 765 766 static void 767 thunder_pem_release_all(device_t dev) 768 { 769 struct thunder_pem_softc *sc; 770 771 sc = device_get_softc(dev); 772 773 rman_fini(&sc->io_rman); 774 rman_fini(&sc->mem_rman); 775 776 if (sc->reg != NULL) 777 bus_free_resource(dev, SYS_RES_MEMORY, sc->reg); 778 } 779 780 static int 781 thunder_pem_detach(device_t dev) 782 { 783 784 thunder_pem_release_all(dev); 785 786 return (0); 787 } 788