1 /*- 2 * Copyright (c) 2015 The FreeBSD Foundation 3 * All rights reserved. 4 * 5 * This software was developed by Semihalf under 6 * the sponsorship of the FreeBSD Foundation. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* PCIe external MAC root complex driver (PEM) for Cavium Thunder SOC */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include "opt_platform.h" 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/bus.h> 40 #include <sys/kernel.h> 41 #include <sys/malloc.h> 42 #include <sys/module.h> 43 #include <sys/rman.h> 44 #include <sys/endian.h> 45 46 #ifdef FDT 47 #include <dev/ofw/openfirm.h> 48 #include <dev/ofw/ofw_bus.h> 49 #include <dev/ofw/ofw_bus_subr.h> 50 #include <dev/ofw/ofw_pci.h> 51 #endif 52 53 #include <dev/pci/pcivar.h> 54 #include <dev/pci/pcireg.h> 55 #include <dev/pci/pci_host_generic.h> 56 57 #include <machine/bus.h> 58 #include <machine/resource.h> 59 #include <machine/smp.h> 60 #include <machine/intr.h> 61 62 #include <arm64/cavium/thunder_pcie_common.h> 63 #include <arm64/cavium/thunder_pcie_pem.h> 64 #include "pcib_if.h" 65 66 #define THUNDER_PEM_DEVICE_ID 0xa020 67 #define THUNDER_PEM_VENDOR_ID 0x177d 68 69 /* ThunderX specific defines */ 70 #define THUNDER_PEMn_REG_BASE(unit) (0x87e0c0000000UL | ((unit) << 24)) 71 #define PCIERC_CFG002 0x08 72 #define PCIERC_CFG006 0x18 73 #define PCIERC_CFG032 0x80 74 #define PCIERC_CFG006_SEC_BUS(reg) (((reg) >> 8) & 0xFF) 75 #define PEM_CFG_RD_REG_ALIGN(reg) ((reg) & ~0x3) 76 #define PEM_CFG_RD_REG_DATA(val) (((val) >> 32) & 0xFFFFFFFF) 77 #define PEM_CFG_RD 0x30 78 #define PEM_CFG_LINK_MASK 0x3 79 #define PEM_CFG_LINK_RDY 0x3 80 #define PEM_CFG_SLIX_TO_REG(slix) ((slix) << 4) 81 #define SBNUM_OFFSET 0x8 82 #define SBNUM_MASK 0xFF 83 #define PEM_ON_REG 0x420 84 #define PEM_CTL_STATUS 0x0 85 #define PEM_LINK_ENABLE (1 << 4) 86 #define PEM_LINK_DLLA (1 << 29) 87 #define PEM_LINK_LT (1 << 27) 88 #define PEM_BUS_SHIFT (24) 89 #define PEM_SLOT_SHIFT (19) 90 #define PEM_FUNC_SHIFT (16) 91 #define SLIX_S2M_REGX_ACC 0x874001000000UL 92 #define SLIX_S2M_REGX_ACC_SIZE 0x1000 93 #define SLIX_S2M_REGX_ACC_SPACING 0x001000000000UL 94 #define SLI_BASE 0x880000000000UL 95 #define SLI_WINDOW_SPACING 0x004000000000UL 96 #define SLI_PCI_OFFSET 0x001000000000UL 97 #define SLI_NODE_SHIFT (44) 98 #define SLI_NODE_MASK (3) 99 #define SLI_GROUP_SHIFT (40) 100 #define SLI_ID_SHIFT (24) 101 #define SLI_ID_MASK (7) 102 #define SLI_PEMS_PER_GROUP (3) 103 #define SLI_GROUPS_PER_NODE (2) 104 #define SLI_PEMS_PER_NODE (SLI_PEMS_PER_GROUP * SLI_GROUPS_PER_NODE) 105 #define SLI_ACC_REG_CNT (256) 106 107 /* 108 * Each PEM device creates its own bus with 109 * own address translation, so we can adjust bus addresses 110 * as we want. To support 32-bit cards let's assume 111 * PCI window assignment looks as following: 112 * 113 * 0x00000000 - 0x000FFFFF IO 114 * 0x00100000 - 0xFFFFFFFF Memory 115 */ 116 #define PCI_IO_BASE 0x00000000UL 117 #define PCI_IO_SIZE 0x00100000UL 118 #define PCI_MEMORY_BASE PCI_IO_SIZE 119 #define PCI_MEMORY_SIZE 0xFFF00000UL 120 121 #define RID_PEM_SPACE 1 122 123 static int thunder_pem_activate_resource(device_t, device_t, int, int, 124 struct resource *); 125 static int thunder_pem_adjust_resource(device_t, device_t, int, 126 struct resource *, rman_res_t, rman_res_t); 127 static struct resource * thunder_pem_alloc_resource(device_t, device_t, int, 128 int *, rman_res_t, rman_res_t, rman_res_t, u_int); 129 static int thunder_pem_alloc_msi(device_t, device_t, int, int, int *); 130 static int thunder_pem_release_msi(device_t, device_t, int, int *); 131 static int thunder_pem_map_msi(device_t, device_t, int, uint64_t *, uint32_t *); 132 static int thunder_pem_alloc_msix(device_t, device_t, int *); 133 static int thunder_pem_release_msix(device_t, device_t, int); 134 static int thunder_pem_attach(device_t); 135 static int thunder_pem_deactivate_resource(device_t, device_t, int, int, 136 struct resource *); 137 static int thunder_pem_detach(device_t); 138 static uint64_t thunder_pem_config_reg_read(struct thunder_pem_softc *, int); 139 static int thunder_pem_link_init(struct thunder_pem_softc *); 140 static int thunder_pem_maxslots(device_t); 141 static int thunder_pem_probe(device_t); 142 static uint32_t thunder_pem_read_config(device_t, u_int, u_int, u_int, u_int, 143 int); 144 static int thunder_pem_read_ivar(device_t, device_t, int, uintptr_t *); 145 static void thunder_pem_release_all(device_t); 146 static int thunder_pem_release_resource(device_t, device_t, int, int, 147 struct resource *); 148 static struct rman * thunder_pem_rman(struct thunder_pem_softc *, int); 149 static void thunder_pem_slix_s2m_regx_acc_modify(struct thunder_pem_softc *, 150 int, int); 151 static void thunder_pem_write_config(device_t, u_int, u_int, u_int, u_int, 152 uint32_t, int); 153 static int thunder_pem_write_ivar(device_t, device_t, int, uintptr_t); 154 155 /* Global handlers for SLI interface */ 156 static bus_space_handle_t sli0_s2m_regx_base = 0; 157 static bus_space_handle_t sli1_s2m_regx_base = 0; 158 159 static device_method_t thunder_pem_methods[] = { 160 /* Device interface */ 161 DEVMETHOD(device_probe, thunder_pem_probe), 162 DEVMETHOD(device_attach, thunder_pem_attach), 163 DEVMETHOD(device_detach, thunder_pem_detach), 164 165 /* Bus interface */ 166 DEVMETHOD(bus_read_ivar, thunder_pem_read_ivar), 167 DEVMETHOD(bus_write_ivar, thunder_pem_write_ivar), 168 DEVMETHOD(bus_alloc_resource, thunder_pem_alloc_resource), 169 DEVMETHOD(bus_release_resource, thunder_pem_release_resource), 170 DEVMETHOD(bus_adjust_resource, thunder_pem_adjust_resource), 171 DEVMETHOD(bus_activate_resource, thunder_pem_activate_resource), 172 DEVMETHOD(bus_deactivate_resource, thunder_pem_deactivate_resource), 173 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 174 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 175 176 /* pcib interface */ 177 DEVMETHOD(pcib_maxslots, thunder_pem_maxslots), 178 DEVMETHOD(pcib_read_config, thunder_pem_read_config), 179 DEVMETHOD(pcib_write_config, thunder_pem_write_config), 180 DEVMETHOD(pcib_map_msi, thunder_pem_map_msi), 181 DEVMETHOD(pcib_alloc_msix, thunder_pem_alloc_msix), 182 DEVMETHOD(pcib_release_msix, thunder_pem_release_msix), 183 DEVMETHOD(pcib_alloc_msi, thunder_pem_alloc_msi), 184 DEVMETHOD(pcib_release_msi, thunder_pem_release_msi), 185 186 DEVMETHOD_END 187 }; 188 189 DEFINE_CLASS_0(pcib, thunder_pem_driver, thunder_pem_methods, 190 sizeof(struct thunder_pem_softc)); 191 192 static devclass_t thunder_pem_devclass; 193 extern struct bus_space memmap_bus; 194 195 DRIVER_MODULE(thunder_pem, pci, thunder_pem_driver, thunder_pem_devclass, 0, 0); 196 MODULE_DEPEND(thunder_pem, pci, 1, 1, 1); 197 198 static int 199 thunder_pem_maxslots(device_t dev) 200 { 201 202 #if 0 203 /* max slots per bus acc. to standard */ 204 return (PCI_SLOTMAX); 205 #else 206 /* 207 * ARM64TODO Workaround - otherwise an em(4) interface appears to be 208 * present on every PCI function on the bus to which it is connected 209 */ 210 return (0); 211 #endif 212 } 213 214 static int 215 thunder_pem_read_ivar(device_t dev, device_t child, int index, 216 uintptr_t *result) 217 { 218 struct thunder_pem_softc *sc; 219 int secondary_bus = 0; 220 221 sc = device_get_softc(dev); 222 223 if (index == PCIB_IVAR_BUS) { 224 secondary_bus = thunder_pem_config_reg_read(sc, PCIERC_CFG006); 225 *result = PCIERC_CFG006_SEC_BUS(secondary_bus); 226 return (0); 227 } 228 if (index == PCIB_IVAR_DOMAIN) { 229 *result = sc->id; 230 return (0); 231 } 232 233 return (ENOENT); 234 } 235 236 static int 237 thunder_pem_write_ivar(device_t dev, device_t child, int index, 238 uintptr_t value) 239 { 240 241 return (ENOENT); 242 } 243 244 static int 245 thunder_pem_activate_resource(device_t dev, device_t child, int type, int rid, 246 struct resource *r) 247 { 248 int err; 249 bus_addr_t paddr; 250 bus_size_t psize; 251 bus_space_handle_t vaddr; 252 struct thunder_pem_softc *sc; 253 254 if ((err = rman_activate_resource(r)) != 0) 255 return (err); 256 257 sc = device_get_softc(dev); 258 259 /* 260 * If this is a memory resource, map it into the kernel. 261 */ 262 if (type == SYS_RES_MEMORY || type == SYS_RES_IOPORT) { 263 paddr = (bus_addr_t)rman_get_start(r); 264 psize = (bus_size_t)rman_get_size(r); 265 266 paddr = range_addr_pci_to_phys(sc->ranges, paddr); 267 268 err = bus_space_map(&memmap_bus, paddr, psize, 0, &vaddr); 269 if (err != 0) { 270 rman_deactivate_resource(r); 271 return (err); 272 } 273 rman_set_bustag(r, &memmap_bus); 274 rman_set_virtual(r, (void *)vaddr); 275 rman_set_bushandle(r, vaddr); 276 } 277 return (0); 278 } 279 280 /* 281 * This function is an exact copy of nexus_deactivate_resource() 282 * Keep it up-to-date with all changes in nexus. To be removed 283 * once bus-mapping interface is developed. 284 */ 285 static int 286 thunder_pem_deactivate_resource(device_t bus, device_t child, int type, int rid, 287 struct resource *r) 288 { 289 bus_size_t psize; 290 bus_space_handle_t vaddr; 291 292 psize = (bus_size_t)rman_get_size(r); 293 vaddr = rman_get_bushandle(r); 294 295 if (vaddr != 0) { 296 bus_space_unmap(&memmap_bus, vaddr, psize); 297 rman_set_virtual(r, NULL); 298 rman_set_bushandle(r, 0); 299 } 300 301 return (rman_deactivate_resource(r)); 302 } 303 304 static int 305 thunder_pem_adjust_resource(device_t dev, device_t child, int type, 306 struct resource *res, rman_res_t start, rman_res_t end) 307 { 308 struct thunder_pem_softc *sc; 309 struct rman *rm; 310 311 sc = device_get_softc(dev); 312 313 rm = thunder_pem_rman(sc, type); 314 if (rm == NULL) 315 return (bus_generic_adjust_resource(dev, child, type, res, 316 start, end)); 317 if (!rman_is_region_manager(res, rm)) 318 /* 319 * This means a child device has a memory or I/O 320 * resource not from you which shouldn't happen. 321 */ 322 return (EINVAL); 323 return (rman_adjust_resource(res, start, end)); 324 } 325 326 static int 327 thunder_pem_alloc_msi(device_t pci, device_t child, int count, int maxcount, 328 int *irqs) 329 { 330 331 return (arm_alloc_msi(pci, child, count, maxcount, irqs)); 332 } 333 334 static int 335 thunder_pem_release_msi(device_t pci, device_t child, int count, int *irqs) 336 { 337 338 return (arm_release_msi(pci, child, count, irqs)); 339 } 340 341 static int 342 thunder_pem_map_msi(device_t pci, device_t child, int irq, uint64_t *addr, 343 uint32_t *data) 344 { 345 346 return (arm_map_msi(pci, child, irq, addr, data)); 347 } 348 349 static int 350 thunder_pem_alloc_msix(device_t pci, device_t child, int *irq) 351 { 352 353 return (arm_alloc_msix(pci, child, irq)); 354 } 355 356 static int 357 thunder_pem_release_msix(device_t pci, device_t child, int irq) 358 { 359 360 return (arm_release_msix(pci, child, irq)); 361 } 362 363 static int 364 thunder_pem_identify(device_t dev) 365 { 366 struct thunder_pem_softc *sc; 367 rman_res_t start; 368 369 sc = device_get_softc(dev); 370 start = rman_get_start(sc->reg); 371 372 /* Calculate PEM designations from its address */ 373 sc->node = (start >> SLI_NODE_SHIFT) & SLI_NODE_MASK; 374 sc->id = ((start >> SLI_ID_SHIFT) & SLI_ID_MASK) + 375 (SLI_PEMS_PER_NODE * sc->node); 376 sc->sli = sc->id % SLI_PEMS_PER_GROUP; 377 sc->sli_group = (sc->id / SLI_PEMS_PER_GROUP) % SLI_GROUPS_PER_NODE; 378 sc->sli_window_base = SLI_BASE | 379 (((uint64_t)sc->node) << SLI_NODE_SHIFT) | 380 ((uint64_t)sc->sli_group << SLI_GROUP_SHIFT); 381 sc->sli_window_base += SLI_WINDOW_SPACING * sc->sli; 382 383 return (0); 384 } 385 386 static void 387 thunder_pem_slix_s2m_regx_acc_modify(struct thunder_pem_softc *sc, 388 int sli_group, int slix) 389 { 390 uint64_t regval; 391 bus_space_handle_t handle = 0; 392 393 KASSERT(slix >= 0 && slix <= SLI_ACC_REG_CNT, ("Invalid SLI index")); 394 395 if (sli_group == 0) 396 handle = sli0_s2m_regx_base; 397 else if (sli_group == 1) 398 handle = sli1_s2m_regx_base; 399 else 400 device_printf(sc->dev, "SLI group is not correct\n"); 401 402 if (handle) { 403 /* Clear lower 32-bits of the SLIx register */ 404 regval = bus_space_read_8(sc->reg_bst, handle, 405 PEM_CFG_SLIX_TO_REG(slix)); 406 regval &= ~(0xFFFFFFFFUL); 407 bus_space_write_8(sc->reg_bst, handle, 408 PEM_CFG_SLIX_TO_REG(slix), regval); 409 } 410 } 411 412 static int 413 thunder_pem_link_init(struct thunder_pem_softc *sc) 414 { 415 uint64_t regval; 416 417 /* check whether PEM is safe to access. */ 418 regval = bus_space_read_8(sc->reg_bst, sc->reg_bsh, PEM_ON_REG); 419 if ((regval & PEM_CFG_LINK_MASK) != PEM_CFG_LINK_RDY) { 420 device_printf(sc->dev, "PEM%d is not ON\n", sc->id); 421 return (ENXIO); 422 } 423 424 regval = bus_space_read_8(sc->reg_bst, sc->reg_bsh, PEM_CTL_STATUS); 425 regval |= PEM_LINK_ENABLE; 426 bus_space_write_8(sc->reg_bst, sc->reg_bsh, PEM_CTL_STATUS, regval); 427 428 /* Wait 1ms as per Cavium specification */ 429 DELAY(1000); 430 431 regval = thunder_pem_config_reg_read(sc, PCIERC_CFG032); 432 433 if (((regval & PEM_LINK_DLLA) == 0) || ((regval & PEM_LINK_LT) != 0)) { 434 device_printf(sc->dev, "PCIe RC: Port %d Link Timeout\n", 435 sc->id); 436 return (ENXIO); 437 } 438 439 return (0); 440 } 441 442 static int 443 thunder_pem_init(struct thunder_pem_softc *sc) 444 { 445 int i, retval = 0; 446 447 retval = thunder_pem_link_init(sc); 448 if (retval) { 449 device_printf(sc->dev, "%s failed\n", __func__); 450 return retval; 451 } 452 453 /* To support 32-bit PCIe devices, set S2M_REGx_ACC[BA]=0x0 */ 454 for (i = 0; i < SLI_ACC_REG_CNT; i++) { 455 thunder_pem_slix_s2m_regx_acc_modify(sc, sc->sli_group, i); 456 } 457 458 return (retval); 459 } 460 461 static uint64_t 462 thunder_pem_config_reg_read(struct thunder_pem_softc *sc, int reg) 463 { 464 uint64_t data; 465 466 /* Write to ADDR register */ 467 bus_space_write_8(sc->reg_bst, sc->reg_bsh, PEM_CFG_RD, 468 PEM_CFG_RD_REG_ALIGN(reg)); 469 bus_space_barrier(sc->reg_bst, sc->reg_bsh, PEM_CFG_RD, 8, 470 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 471 /* Read from DATA register */ 472 data = PEM_CFG_RD_REG_DATA(bus_space_read_8(sc->reg_bst, sc->reg_bsh, 473 PEM_CFG_RD)); 474 475 return (data); 476 } 477 478 static uint32_t 479 thunder_pem_read_config(device_t dev, u_int bus, u_int slot, 480 u_int func, u_int reg, int bytes) 481 { 482 uint64_t offset; 483 uint32_t data; 484 struct thunder_pem_softc *sc; 485 bus_space_tag_t t; 486 bus_space_handle_t h; 487 488 if ((bus > PCI_BUSMAX) || (slot > PCI_SLOTMAX) || 489 (func > PCI_FUNCMAX) || (reg > PCIE_REGMAX)) 490 return (~0U); 491 492 sc = device_get_softc(dev); 493 494 /* Calculate offset */ 495 offset = (bus << PEM_BUS_SHIFT) | (slot << PEM_SLOT_SHIFT) | 496 (func << PEM_FUNC_SHIFT); 497 t = sc->reg_bst; 498 h = sc->pem_sli_base; 499 500 bus_space_map(sc->reg_bst, sc->sli_window_base + offset, 501 PCIE_REGMAX, 0, &h); 502 503 switch (bytes) { 504 case 1: 505 data = bus_space_read_1(t, h, reg); 506 break; 507 case 2: 508 data = le16toh(bus_space_read_2(t, h, reg)); 509 break; 510 case 4: 511 data = le32toh(bus_space_read_4(t, h, reg)); 512 break; 513 default: 514 data = ~0U; 515 break; 516 } 517 518 bus_space_unmap(sc->reg_bst, h, PCIE_REGMAX); 519 520 return (data); 521 } 522 523 static void 524 thunder_pem_write_config(device_t dev, u_int bus, u_int slot, 525 u_int func, u_int reg, uint32_t val, int bytes) 526 { 527 uint64_t offset; 528 struct thunder_pem_softc *sc; 529 bus_space_tag_t t; 530 bus_space_handle_t h; 531 532 if ((bus > PCI_BUSMAX) || (slot > PCI_SLOTMAX) || 533 (func > PCI_FUNCMAX) || (reg > PCIE_REGMAX)) 534 return; 535 536 sc = device_get_softc(dev); 537 538 /* Calculate offset */ 539 offset = (bus << PEM_BUS_SHIFT) | (slot << PEM_SLOT_SHIFT) | 540 (func << PEM_FUNC_SHIFT); 541 t = sc->reg_bst; 542 h = sc->pem_sli_base; 543 544 bus_space_map(sc->reg_bst, sc->sli_window_base + offset, 545 PCIE_REGMAX, 0, &h); 546 547 switch (bytes) { 548 case 1: 549 bus_space_write_1(t, h, reg, val); 550 break; 551 case 2: 552 bus_space_write_2(t, h, reg, htole16(val)); 553 break; 554 case 4: 555 bus_space_write_4(t, h, reg, htole32(val)); 556 break; 557 default: 558 break; 559 } 560 561 bus_space_unmap(sc->reg_bst, h, PCIE_REGMAX); 562 } 563 564 static struct resource * 565 thunder_pem_alloc_resource(device_t dev, device_t child, int type, int *rid, 566 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 567 { 568 struct thunder_pem_softc *sc = device_get_softc(dev); 569 struct rman *rm = NULL; 570 struct resource *res; 571 device_t parent_dev; 572 573 rm = thunder_pem_rman(sc, type); 574 if (rm == NULL) { 575 /* Find parent device. On ThunderX we know an exact path. */ 576 parent_dev = device_get_parent(device_get_parent(dev)); 577 return (BUS_ALLOC_RESOURCE(parent_dev, dev, type, rid, start, 578 end, count, flags)); 579 } 580 581 582 if (!RMAN_IS_DEFAULT_RANGE(start, end)) { 583 /* 584 * We might get PHYS addresses here inherited from EFI. 585 * Convert to PCI if necessary. 586 */ 587 if (range_addr_is_phys(sc->ranges, start, count)) { 588 start = range_addr_phys_to_pci(sc->ranges, start); 589 end = start + count - 1; 590 } 591 592 } 593 594 if (bootverbose) { 595 device_printf(dev, 596 "thunder_pem_alloc_resource: start=%#lx, end=%#lx, count=%#lx\n", 597 start, end, count); 598 } 599 600 res = rman_reserve_resource(rm, start, end, count, flags, child); 601 if (res == NULL) 602 goto fail; 603 604 rman_set_rid(res, *rid); 605 606 if (flags & RF_ACTIVE) 607 if (bus_activate_resource(child, type, *rid, res)) { 608 rman_release_resource(res); 609 goto fail; 610 } 611 612 return (res); 613 614 fail: 615 if (bootverbose) { 616 device_printf(dev, "%s FAIL: type=%d, rid=%d, " 617 "start=%016lx, end=%016lx, count=%016lx, flags=%x\n", 618 __func__, type, *rid, start, end, count, flags); 619 } 620 621 return (NULL); 622 } 623 624 static int 625 thunder_pem_release_resource(device_t dev, device_t child, int type, int rid, 626 struct resource *res) 627 { 628 device_t parent_dev; 629 630 /* Find parent device. On ThunderX we know an exact path. */ 631 parent_dev = device_get_parent(device_get_parent(dev)); 632 633 if ((type != SYS_RES_MEMORY) && (type != SYS_RES_IOPORT)) 634 return (BUS_RELEASE_RESOURCE(parent_dev, child, 635 type, rid, res)); 636 637 return (rman_release_resource(res)); 638 } 639 640 static struct rman * 641 thunder_pem_rman(struct thunder_pem_softc *sc, int type) 642 { 643 644 switch (type) { 645 case SYS_RES_IOPORT: 646 return (&sc->io_rman); 647 case SYS_RES_MEMORY: 648 return (&sc->mem_rman); 649 default: 650 break; 651 } 652 653 return (NULL); 654 } 655 656 static int 657 thunder_pem_probe(device_t dev) 658 { 659 uint16_t pci_vendor_id; 660 uint16_t pci_device_id; 661 662 pci_vendor_id = pci_get_vendor(dev); 663 pci_device_id = pci_get_device(dev); 664 665 if ((pci_vendor_id == THUNDER_PEM_VENDOR_ID) && 666 (pci_device_id == THUNDER_PEM_DEVICE_ID)) { 667 device_set_desc_copy(dev, THUNDER_PEM_DESC); 668 return (0); 669 } 670 671 return (ENXIO); 672 } 673 674 static int 675 thunder_pem_attach(device_t dev) 676 { 677 devclass_t pci_class; 678 device_t parent; 679 struct thunder_pem_softc *sc; 680 int error; 681 int rid; 682 int tuple; 683 uint64_t base, size; 684 struct rman *rman; 685 686 sc = device_get_softc(dev); 687 sc->dev = dev; 688 689 /* Allocate memory for resource */ 690 pci_class = devclass_find("pci"); 691 parent = device_get_parent(dev); 692 if (device_get_devclass(parent) == pci_class) 693 rid = PCIR_BAR(0); 694 else 695 rid = RID_PEM_SPACE; 696 697 sc->reg = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 698 &rid, RF_ACTIVE); 699 if (sc->reg == NULL) { 700 device_printf(dev, "Failed to allocate resource\n"); 701 return (ENXIO); 702 } 703 sc->reg_bst = rman_get_bustag(sc->reg); 704 sc->reg_bsh = rman_get_bushandle(sc->reg); 705 706 /* Map SLI, do it only once */ 707 if (!sli0_s2m_regx_base) { 708 bus_space_map(sc->reg_bst, SLIX_S2M_REGX_ACC, 709 SLIX_S2M_REGX_ACC_SIZE, 0, &sli0_s2m_regx_base); 710 } 711 if (!sli1_s2m_regx_base) { 712 bus_space_map(sc->reg_bst, SLIX_S2M_REGX_ACC + 713 SLIX_S2M_REGX_ACC_SPACING, SLIX_S2M_REGX_ACC_SIZE, 0, 714 &sli1_s2m_regx_base); 715 } 716 717 if ((sli0_s2m_regx_base == 0) || (sli1_s2m_regx_base == 0)) { 718 device_printf(dev, 719 "bus_space_map failed to map slix_s2m_regx_base\n"); 720 goto fail; 721 } 722 723 /* Identify PEM */ 724 if (thunder_pem_identify(dev) != 0) 725 goto fail; 726 727 /* Initialize rman and allocate regions */ 728 sc->mem_rman.rm_type = RMAN_ARRAY; 729 sc->mem_rman.rm_descr = "PEM PCIe Memory"; 730 error = rman_init(&sc->mem_rman); 731 if (error != 0) { 732 device_printf(dev, "memory rman_init() failed. error = %d\n", 733 error); 734 goto fail; 735 } 736 sc->io_rman.rm_type = RMAN_ARRAY; 737 sc->io_rman.rm_descr = "PEM PCIe IO"; 738 error = rman_init(&sc->io_rman); 739 if (error != 0) { 740 device_printf(dev, "IO rman_init() failed. error = %d\n", 741 error); 742 goto fail_mem; 743 } 744 745 /* 746 * We ignore the values that may have been provided in FDT 747 * and configure ranges according to the below formula 748 * for all types of devices. This is because some DTBs provided 749 * by EFI do not have proper ranges property or don't have them 750 * at all. 751 */ 752 /* Fill memory window */ 753 sc->ranges[0].pci_base = PCI_MEMORY_BASE; 754 sc->ranges[0].size = PCI_MEMORY_SIZE; 755 sc->ranges[0].phys_base = sc->sli_window_base + SLI_PCI_OFFSET + 756 sc->ranges[0].pci_base; 757 sc->ranges[0].flags = SYS_RES_MEMORY; 758 759 /* Fill IO window */ 760 sc->ranges[1].pci_base = PCI_IO_BASE; 761 sc->ranges[1].size = PCI_IO_SIZE; 762 sc->ranges[1].phys_base = sc->sli_window_base + SLI_PCI_OFFSET + 763 sc->ranges[1].pci_base; 764 sc->ranges[1].flags = SYS_RES_IOPORT; 765 766 for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) { 767 base = sc->ranges[tuple].pci_base; 768 size = sc->ranges[tuple].size; 769 if (size == 0) 770 continue; /* empty range element */ 771 772 rman = thunder_pem_rman(sc, sc->ranges[tuple].flags); 773 if (rman != NULL) 774 error = rman_manage_region(rman, base, 775 base + size - 1); 776 else 777 error = EINVAL; 778 if (error) { 779 device_printf(dev, 780 "rman_manage_region() failed. error = %d\n", error); 781 rman_fini(&sc->mem_rman); 782 return (error); 783 } 784 if (bootverbose) { 785 device_printf(dev, 786 "\tPCI addr: 0x%jx, CPU addr: 0x%jx, Size: 0x%jx, Flags:0x%jx\n", 787 sc->ranges[tuple].pci_base, 788 sc->ranges[tuple].phys_base, 789 sc->ranges[tuple].size, 790 sc->ranges[tuple].flags); 791 } 792 } 793 794 if (thunder_pem_init(sc)) { 795 device_printf(dev, "Failure during PEM init\n"); 796 goto fail_io; 797 } 798 799 device_add_child(dev, "pci", -1); 800 801 return (bus_generic_attach(dev)); 802 803 fail_io: 804 rman_fini(&sc->io_rman); 805 fail_mem: 806 rman_fini(&sc->mem_rman); 807 fail: 808 bus_free_resource(dev, SYS_RES_MEMORY, sc->reg); 809 return (ENXIO); 810 } 811 812 static void 813 thunder_pem_release_all(device_t dev) 814 { 815 struct thunder_pem_softc *sc; 816 817 sc = device_get_softc(dev); 818 819 rman_fini(&sc->io_rman); 820 rman_fini(&sc->mem_rman); 821 822 if (sc->reg != NULL) 823 bus_free_resource(dev, SYS_RES_MEMORY, sc->reg); 824 } 825 826 static int 827 thunder_pem_detach(device_t dev) 828 { 829 830 thunder_pem_release_all(dev); 831 832 return (0); 833 } 834