1 /*- 2 * Copyright (c) 2015 The FreeBSD Foundation 3 * 4 * This software was developed by Semihalf under 5 * the sponsorship of the FreeBSD Foundation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* PCIe external MAC root complex driver (PEM) for Cavium Thunder SOC */ 30 31 #include <sys/cdefs.h> 32 #include "opt_platform.h" 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 #include <sys/kernel.h> 38 #include <sys/malloc.h> 39 #include <sys/module.h> 40 #include <sys/rman.h> 41 #include <sys/endian.h> 42 43 #include <vm/vm.h> 44 45 #ifdef FDT 46 #include <dev/ofw/openfirm.h> 47 #include <dev/ofw/ofw_bus.h> 48 #include <dev/ofw/ofw_bus_subr.h> 49 #include <dev/ofw/ofw_pci.h> 50 #endif 51 52 #include <dev/pci/pcivar.h> 53 #include <dev/pci/pcireg.h> 54 #include <dev/pci/pci_host_generic.h> 55 #include <dev/pci/pcib_private.h> 56 57 #include <machine/bus.h> 58 #include <machine/resource.h> 59 #include <machine/smp.h> 60 #include <machine/intr.h> 61 62 #include <arm64/cavium/thunder_pcie_common.h> 63 #include <arm64/cavium/thunder_pcie_pem.h> 64 #include "pcib_if.h" 65 66 #define THUNDER_PEM_DEVICE_ID 0xa020 67 #define THUNDER_PEM_VENDOR_ID 0x177d 68 69 /* ThunderX specific defines */ 70 #define THUNDER_PEMn_REG_BASE(unit) (0x87e0c0000000UL | ((unit) << 24)) 71 #define PCIERC_CFG002 0x08 72 #define PCIERC_CFG006 0x18 73 #define PCIERC_CFG032 0x80 74 #define PCIERC_CFG006_SEC_BUS(reg) (((reg) >> 8) & 0xFF) 75 #define PEM_CFG_RD_REG_ALIGN(reg) ((reg) & ~0x3) 76 #define PEM_CFG_RD_REG_DATA(val) (((val) >> 32) & 0xFFFFFFFF) 77 #define PEM_CFG_RD 0x30 78 #define PEM_CFG_LINK_MASK 0x3 79 #define PEM_CFG_LINK_RDY 0x3 80 #define PEM_CFG_SLIX_TO_REG(slix) ((slix) << 4) 81 #define SBNUM_OFFSET 0x8 82 #define SBNUM_MASK 0xFF 83 #define PEM_ON_REG 0x420 84 #define PEM_CTL_STATUS 0x0 85 #define PEM_LINK_ENABLE (1 << 4) 86 #define PEM_LINK_DLLA (1 << 29) 87 #define PEM_LINK_LT (1 << 27) 88 #define PEM_BUS_SHIFT (24) 89 #define PEM_SLOT_SHIFT (19) 90 #define PEM_FUNC_SHIFT (16) 91 #define SLIX_S2M_REGX_ACC 0x874001000000UL 92 #define SLIX_S2M_REGX_ACC_SIZE 0x1000 93 #define SLIX_S2M_REGX_ACC_SPACING 0x001000000000UL 94 #define SLI_BASE 0x880000000000UL 95 #define SLI_WINDOW_SPACING 0x004000000000UL 96 #define SLI_PCI_OFFSET 0x001000000000UL 97 #define SLI_NODE_SHIFT (44) 98 #define SLI_NODE_MASK (3) 99 #define SLI_GROUP_SHIFT (40) 100 #define SLI_ID_SHIFT (24) 101 #define SLI_ID_MASK (7) 102 #define SLI_PEMS_PER_GROUP (3) 103 #define SLI_GROUPS_PER_NODE (2) 104 #define SLI_PEMS_PER_NODE (SLI_PEMS_PER_GROUP * SLI_GROUPS_PER_NODE) 105 #define SLI_ACC_REG_CNT (256) 106 107 /* 108 * Each PEM device creates its own bus with 109 * own address translation, so we can adjust bus addresses 110 * as we want. To support 32-bit cards let's assume 111 * PCI window assignment looks as following: 112 * 113 * 0x00000000 - 0x000FFFFF IO 114 * 0x00100000 - 0xFFFFFFFF Memory 115 */ 116 #define PCI_IO_BASE 0x00000000UL 117 #define PCI_IO_SIZE 0x00100000UL 118 #define PCI_MEMORY_BASE PCI_IO_SIZE 119 #define PCI_MEMORY_SIZE 0xFFF00000UL 120 121 #define RID_PEM_SPACE 1 122 123 static int thunder_pem_activate_resource(device_t, device_t, int, int, 124 struct resource *); 125 static int thunder_pem_adjust_resource(device_t, device_t, int, 126 struct resource *, rman_res_t, rman_res_t); 127 static struct resource * thunder_pem_alloc_resource(device_t, device_t, int, 128 int *, rman_res_t, rman_res_t, rman_res_t, u_int); 129 static int thunder_pem_alloc_msi(device_t, device_t, int, int, int *); 130 static int thunder_pem_release_msi(device_t, device_t, int, int *); 131 static int thunder_pem_alloc_msix(device_t, device_t, int *); 132 static int thunder_pem_release_msix(device_t, device_t, int); 133 static int thunder_pem_map_msi(device_t, device_t, int, uint64_t *, uint32_t *); 134 static int thunder_pem_get_id(device_t, device_t, enum pci_id_type, 135 uintptr_t *); 136 static int thunder_pem_attach(device_t); 137 static int thunder_pem_deactivate_resource(device_t, device_t, int, int, 138 struct resource *); 139 static int thunder_pem_map_resource(device_t, device_t, int, struct resource *, 140 struct resource_map_request *, struct resource_map *); 141 static int thunder_pem_unmap_resource(device_t, device_t, int, 142 struct resource *, struct resource_map *); 143 static bus_dma_tag_t thunder_pem_get_dma_tag(device_t, device_t); 144 static int thunder_pem_detach(device_t); 145 static uint64_t thunder_pem_config_reg_read(struct thunder_pem_softc *, int); 146 static int thunder_pem_link_init(struct thunder_pem_softc *); 147 static int thunder_pem_maxslots(device_t); 148 static int thunder_pem_probe(device_t); 149 static uint32_t thunder_pem_read_config(device_t, u_int, u_int, u_int, u_int, 150 int); 151 static int thunder_pem_read_ivar(device_t, device_t, int, uintptr_t *); 152 static void thunder_pem_release_all(device_t); 153 static int thunder_pem_release_resource(device_t, device_t, int, int, 154 struct resource *); 155 static struct rman * thunder_pem_get_rman(device_t, int, u_int); 156 static void thunder_pem_slix_s2m_regx_acc_modify(struct thunder_pem_softc *, 157 int, int); 158 static void thunder_pem_write_config(device_t, u_int, u_int, u_int, u_int, 159 uint32_t, int); 160 static int thunder_pem_write_ivar(device_t, device_t, int, uintptr_t); 161 162 /* Global handlers for SLI interface */ 163 static bus_space_handle_t sli0_s2m_regx_base = 0; 164 static bus_space_handle_t sli1_s2m_regx_base = 0; 165 166 static device_method_t thunder_pem_methods[] = { 167 /* Device interface */ 168 DEVMETHOD(device_probe, thunder_pem_probe), 169 DEVMETHOD(device_attach, thunder_pem_attach), 170 DEVMETHOD(device_detach, thunder_pem_detach), 171 172 /* Bus interface */ 173 DEVMETHOD(bus_read_ivar, thunder_pem_read_ivar), 174 DEVMETHOD(bus_write_ivar, thunder_pem_write_ivar), 175 DEVMETHOD(bus_get_rman, thunder_pem_get_rman), 176 DEVMETHOD(bus_alloc_resource, thunder_pem_alloc_resource), 177 DEVMETHOD(bus_release_resource, thunder_pem_release_resource), 178 DEVMETHOD(bus_adjust_resource, thunder_pem_adjust_resource), 179 DEVMETHOD(bus_activate_resource, thunder_pem_activate_resource), 180 DEVMETHOD(bus_deactivate_resource, thunder_pem_deactivate_resource), 181 DEVMETHOD(bus_map_resource, thunder_pem_map_resource), 182 DEVMETHOD(bus_unmap_resource, thunder_pem_unmap_resource), 183 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 184 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 185 186 DEVMETHOD(bus_get_dma_tag, thunder_pem_get_dma_tag), 187 188 /* pcib interface */ 189 DEVMETHOD(pcib_maxslots, thunder_pem_maxslots), 190 DEVMETHOD(pcib_read_config, thunder_pem_read_config), 191 DEVMETHOD(pcib_write_config, thunder_pem_write_config), 192 DEVMETHOD(pcib_alloc_msix, thunder_pem_alloc_msix), 193 DEVMETHOD(pcib_release_msix, thunder_pem_release_msix), 194 DEVMETHOD(pcib_alloc_msi, thunder_pem_alloc_msi), 195 DEVMETHOD(pcib_release_msi, thunder_pem_release_msi), 196 DEVMETHOD(pcib_map_msi, thunder_pem_map_msi), 197 DEVMETHOD(pcib_get_id, thunder_pem_get_id), 198 199 DEVMETHOD_END 200 }; 201 202 DEFINE_CLASS_0(pcib, thunder_pem_driver, thunder_pem_methods, 203 sizeof(struct thunder_pem_softc)); 204 205 extern struct bus_space memmap_bus; 206 207 DRIVER_MODULE(thunder_pem, pci, thunder_pem_driver, 0, 0); 208 MODULE_DEPEND(thunder_pem, pci, 1, 1, 1); 209 210 static int 211 thunder_pem_maxslots(device_t dev) 212 { 213 214 #if 0 215 /* max slots per bus acc. to standard */ 216 return (PCI_SLOTMAX); 217 #else 218 /* 219 * ARM64TODO Workaround - otherwise an em(4) interface appears to be 220 * present on every PCI function on the bus to which it is connected 221 */ 222 return (0); 223 #endif 224 } 225 226 static int 227 thunder_pem_read_ivar(device_t dev, device_t child, int index, 228 uintptr_t *result) 229 { 230 struct thunder_pem_softc *sc; 231 int secondary_bus = 0; 232 233 sc = device_get_softc(dev); 234 235 if (index == PCIB_IVAR_BUS) { 236 secondary_bus = thunder_pem_config_reg_read(sc, PCIERC_CFG006); 237 *result = PCIERC_CFG006_SEC_BUS(secondary_bus); 238 return (0); 239 } 240 if (index == PCIB_IVAR_DOMAIN) { 241 *result = sc->id; 242 return (0); 243 } 244 245 return (ENOENT); 246 } 247 248 static int 249 thunder_pem_write_ivar(device_t dev, device_t child, int index, 250 uintptr_t value) 251 { 252 253 return (ENOENT); 254 } 255 256 static int 257 thunder_pem_activate_resource(device_t dev, device_t child, int type, int rid, 258 struct resource *r) 259 { 260 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 261 struct thunder_pem_softc *sc; 262 263 sc = device_get_softc(dev); 264 #endif 265 switch (type) { 266 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 267 case PCI_RES_BUS: 268 return (pci_domain_activate_bus(sc->id, child, rid, r)); 269 #endif 270 case SYS_RES_MEMORY: 271 case SYS_RES_IOPORT: 272 return (bus_generic_rman_activate_resource(dev, child, type, 273 rid, r)); 274 default: 275 return (bus_generic_activate_resource(dev, child, type, rid, 276 r)); 277 } 278 } 279 280 static int 281 thunder_pem_deactivate_resource(device_t dev, device_t child, int type, int rid, 282 struct resource *r) 283 { 284 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 285 struct thunder_pem_softc *sc; 286 287 sc = device_get_softc(dev); 288 #endif 289 switch (type) { 290 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 291 case PCI_RES_BUS: 292 return (pci_domain_deactivate_bus(sc->id, child, rid, r)); 293 #endif 294 case SYS_RES_MEMORY: 295 case SYS_RES_IOPORT: 296 return (bus_generic_rman_deactivate_resource(dev, child, type, 297 rid, r)); 298 default: 299 return (bus_generic_deactivate_resource(dev, child, type, rid, 300 r)); 301 } 302 } 303 304 static int 305 thunder_pem_map_resource(device_t dev, device_t child, int type, 306 struct resource *r, struct resource_map_request *argsp, 307 struct resource_map *map) 308 { 309 struct resource_map_request args; 310 struct thunder_pem_softc *sc; 311 rman_res_t length, start; 312 int error; 313 314 /* Resources must be active to be mapped. */ 315 if (!(rman_get_flags(r) & RF_ACTIVE)) 316 return (ENXIO); 317 318 switch (type) { 319 case SYS_RES_MEMORY: 320 case SYS_RES_IOPORT: 321 break; 322 default: 323 return (EINVAL); 324 } 325 326 resource_init_map_request(&args); 327 error = resource_validate_map_request(r, argsp, &args, &start, &length); 328 if (error) 329 return (error); 330 331 sc = device_get_softc(dev); 332 start = range_addr_pci_to_phys(sc->ranges, start); 333 error = bus_space_map(&memmap_bus, start, length, 0, &map->r_bushandle); 334 if (error) 335 return (error); 336 map->r_bustag = &memmap_bus; 337 map->r_vaddr = (void *)map->r_bushandle; 338 map->r_size = length; 339 return (0); 340 } 341 342 static int 343 thunder_pem_unmap_resource(device_t dev, device_t child, int type, 344 struct resource *r, struct resource_map *map) 345 { 346 347 switch (type) { 348 case SYS_RES_MEMORY: 349 case SYS_RES_IOPORT: 350 bus_space_unmap(map->r_bustag, map->r_bushandle, map->r_size); 351 return (0); 352 default: 353 return (EINVAL); 354 } 355 } 356 357 static int 358 thunder_pem_adjust_resource(device_t dev, device_t child, int type, 359 struct resource *res, rman_res_t start, rman_res_t end) 360 { 361 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 362 struct thunder_pem_softc *sc; 363 364 sc = device_get_softc(dev); 365 #endif 366 switch (type) { 367 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 368 case PCI_RES_BUS: 369 return (pci_domain_adjust_bus(sc->id, child, res, start, end)); 370 #endif 371 case SYS_RES_MEMORY: 372 case SYS_RES_IOPORT: 373 return (bus_generic_rman_adjust_resource(dev, child, type, res, 374 start, end)); 375 default: 376 return (bus_generic_adjust_resource(dev, child, type, res, 377 start, end)); 378 } 379 } 380 381 static bus_dma_tag_t 382 thunder_pem_get_dma_tag(device_t dev, device_t child) 383 { 384 struct thunder_pem_softc *sc; 385 386 sc = device_get_softc(dev); 387 return (sc->dmat); 388 } 389 390 static int 391 thunder_pem_alloc_msi(device_t pci, device_t child, int count, int maxcount, 392 int *irqs) 393 { 394 device_t bus; 395 396 bus = device_get_parent(pci); 397 return (PCIB_ALLOC_MSI(device_get_parent(bus), child, count, maxcount, 398 irqs)); 399 } 400 401 static int 402 thunder_pem_release_msi(device_t pci, device_t child, int count, int *irqs) 403 { 404 device_t bus; 405 406 bus = device_get_parent(pci); 407 return (PCIB_RELEASE_MSI(device_get_parent(bus), child, count, irqs)); 408 } 409 410 static int 411 thunder_pem_alloc_msix(device_t pci, device_t child, int *irq) 412 { 413 device_t bus; 414 415 bus = device_get_parent(pci); 416 return (PCIB_ALLOC_MSIX(device_get_parent(bus), child, irq)); 417 } 418 419 static int 420 thunder_pem_release_msix(device_t pci, device_t child, int irq) 421 { 422 device_t bus; 423 424 bus = device_get_parent(pci); 425 return (PCIB_RELEASE_MSIX(device_get_parent(bus), child, irq)); 426 } 427 428 static int 429 thunder_pem_map_msi(device_t pci, device_t child, int irq, uint64_t *addr, 430 uint32_t *data) 431 { 432 device_t bus; 433 434 bus = device_get_parent(pci); 435 return (PCIB_MAP_MSI(device_get_parent(bus), child, irq, addr, data)); 436 } 437 438 static int 439 thunder_pem_get_id(device_t pci, device_t child, enum pci_id_type type, 440 uintptr_t *id) 441 { 442 int bsf; 443 int pem; 444 445 if (type != PCI_ID_MSI) 446 return (pcib_get_id(pci, child, type, id)); 447 448 bsf = pci_get_rid(child); 449 450 /* PEM (PCIe MAC/root complex) number is equal to domain */ 451 pem = pci_get_domain(child); 452 453 /* 454 * Set appropriate device ID (passed by the HW along with 455 * the transaction to memory) for different root complex 456 * numbers using hard-coded domain portion for each group. 457 */ 458 if (pem < 3) 459 *id = (0x1 << PCI_RID_DOMAIN_SHIFT) | bsf; 460 else if (pem < 6) 461 *id = (0x3 << PCI_RID_DOMAIN_SHIFT) | bsf; 462 else if (pem < 9) 463 *id = (0x9 << PCI_RID_DOMAIN_SHIFT) | bsf; 464 else if (pem < 12) 465 *id = (0xB << PCI_RID_DOMAIN_SHIFT) | bsf; 466 else 467 return (ENXIO); 468 469 return (0); 470 } 471 472 static int 473 thunder_pem_identify(device_t dev) 474 { 475 struct thunder_pem_softc *sc; 476 rman_res_t start; 477 478 sc = device_get_softc(dev); 479 start = rman_get_start(sc->reg); 480 481 /* Calculate PEM designations from its address */ 482 sc->node = (start >> SLI_NODE_SHIFT) & SLI_NODE_MASK; 483 sc->id = ((start >> SLI_ID_SHIFT) & SLI_ID_MASK) + 484 (SLI_PEMS_PER_NODE * sc->node); 485 sc->sli = sc->id % SLI_PEMS_PER_GROUP; 486 sc->sli_group = (sc->id / SLI_PEMS_PER_GROUP) % SLI_GROUPS_PER_NODE; 487 sc->sli_window_base = SLI_BASE | 488 (((uint64_t)sc->node) << SLI_NODE_SHIFT) | 489 ((uint64_t)sc->sli_group << SLI_GROUP_SHIFT); 490 sc->sli_window_base += SLI_WINDOW_SPACING * sc->sli; 491 492 return (0); 493 } 494 495 static void 496 thunder_pem_slix_s2m_regx_acc_modify(struct thunder_pem_softc *sc, 497 int sli_group, int slix) 498 { 499 uint64_t regval; 500 bus_space_handle_t handle = 0; 501 502 KASSERT(slix >= 0 && slix <= SLI_ACC_REG_CNT, ("Invalid SLI index")); 503 504 if (sli_group == 0) 505 handle = sli0_s2m_regx_base; 506 else if (sli_group == 1) 507 handle = sli1_s2m_regx_base; 508 else 509 device_printf(sc->dev, "SLI group is not correct\n"); 510 511 if (handle) { 512 /* Clear lower 32-bits of the SLIx register */ 513 regval = bus_space_read_8(sc->reg_bst, handle, 514 PEM_CFG_SLIX_TO_REG(slix)); 515 regval &= ~(0xFFFFFFFFUL); 516 bus_space_write_8(sc->reg_bst, handle, 517 PEM_CFG_SLIX_TO_REG(slix), regval); 518 } 519 } 520 521 static int 522 thunder_pem_link_init(struct thunder_pem_softc *sc) 523 { 524 uint64_t regval; 525 526 /* check whether PEM is safe to access. */ 527 regval = bus_space_read_8(sc->reg_bst, sc->reg_bsh, PEM_ON_REG); 528 if ((regval & PEM_CFG_LINK_MASK) != PEM_CFG_LINK_RDY) { 529 device_printf(sc->dev, "PEM%d is not ON\n", sc->id); 530 return (ENXIO); 531 } 532 533 regval = bus_space_read_8(sc->reg_bst, sc->reg_bsh, PEM_CTL_STATUS); 534 regval |= PEM_LINK_ENABLE; 535 bus_space_write_8(sc->reg_bst, sc->reg_bsh, PEM_CTL_STATUS, regval); 536 537 /* Wait 1ms as per Cavium specification */ 538 DELAY(1000); 539 540 regval = thunder_pem_config_reg_read(sc, PCIERC_CFG032); 541 542 if (((regval & PEM_LINK_DLLA) == 0) || ((regval & PEM_LINK_LT) != 0)) { 543 device_printf(sc->dev, "PCIe RC: Port %d Link Timeout\n", 544 sc->id); 545 return (ENXIO); 546 } 547 548 return (0); 549 } 550 551 static int 552 thunder_pem_init(struct thunder_pem_softc *sc) 553 { 554 int i, retval = 0; 555 556 retval = thunder_pem_link_init(sc); 557 if (retval) { 558 device_printf(sc->dev, "%s failed\n", __func__); 559 return retval; 560 } 561 562 /* To support 32-bit PCIe devices, set S2M_REGx_ACC[BA]=0x0 */ 563 for (i = 0; i < SLI_ACC_REG_CNT; i++) { 564 thunder_pem_slix_s2m_regx_acc_modify(sc, sc->sli_group, i); 565 } 566 567 return (retval); 568 } 569 570 static uint64_t 571 thunder_pem_config_reg_read(struct thunder_pem_softc *sc, int reg) 572 { 573 uint64_t data; 574 575 /* Write to ADDR register */ 576 bus_space_write_8(sc->reg_bst, sc->reg_bsh, PEM_CFG_RD, 577 PEM_CFG_RD_REG_ALIGN(reg)); 578 bus_space_barrier(sc->reg_bst, sc->reg_bsh, PEM_CFG_RD, 8, 579 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 580 /* Read from DATA register */ 581 data = PEM_CFG_RD_REG_DATA(bus_space_read_8(sc->reg_bst, sc->reg_bsh, 582 PEM_CFG_RD)); 583 584 return (data); 585 } 586 587 static uint32_t 588 thunder_pem_read_config(device_t dev, u_int bus, u_int slot, 589 u_int func, u_int reg, int bytes) 590 { 591 uint64_t offset; 592 uint32_t data; 593 struct thunder_pem_softc *sc; 594 bus_space_tag_t t; 595 bus_space_handle_t h; 596 597 if ((bus > PCI_BUSMAX) || (slot > PCI_SLOTMAX) || 598 (func > PCI_FUNCMAX) || (reg > PCIE_REGMAX)) 599 return (~0U); 600 601 sc = device_get_softc(dev); 602 603 /* Calculate offset */ 604 offset = (bus << PEM_BUS_SHIFT) | (slot << PEM_SLOT_SHIFT) | 605 (func << PEM_FUNC_SHIFT); 606 t = sc->reg_bst; 607 h = sc->pem_sli_base; 608 609 bus_space_map(sc->reg_bst, sc->sli_window_base + offset, 610 PCIE_REGMAX, 0, &h); 611 612 switch (bytes) { 613 case 1: 614 data = bus_space_read_1(t, h, reg); 615 break; 616 case 2: 617 data = le16toh(bus_space_read_2(t, h, reg)); 618 break; 619 case 4: 620 data = le32toh(bus_space_read_4(t, h, reg)); 621 break; 622 default: 623 data = ~0U; 624 break; 625 } 626 627 bus_space_unmap(sc->reg_bst, h, PCIE_REGMAX); 628 629 return (data); 630 } 631 632 static void 633 thunder_pem_write_config(device_t dev, u_int bus, u_int slot, 634 u_int func, u_int reg, uint32_t val, int bytes) 635 { 636 uint64_t offset; 637 struct thunder_pem_softc *sc; 638 bus_space_tag_t t; 639 bus_space_handle_t h; 640 641 if ((bus > PCI_BUSMAX) || (slot > PCI_SLOTMAX) || 642 (func > PCI_FUNCMAX) || (reg > PCIE_REGMAX)) 643 return; 644 645 sc = device_get_softc(dev); 646 647 /* Calculate offset */ 648 offset = (bus << PEM_BUS_SHIFT) | (slot << PEM_SLOT_SHIFT) | 649 (func << PEM_FUNC_SHIFT); 650 t = sc->reg_bst; 651 h = sc->pem_sli_base; 652 653 bus_space_map(sc->reg_bst, sc->sli_window_base + offset, 654 PCIE_REGMAX, 0, &h); 655 656 switch (bytes) { 657 case 1: 658 bus_space_write_1(t, h, reg, val); 659 break; 660 case 2: 661 bus_space_write_2(t, h, reg, htole16(val)); 662 break; 663 case 4: 664 bus_space_write_4(t, h, reg, htole32(val)); 665 break; 666 default: 667 break; 668 } 669 670 bus_space_unmap(sc->reg_bst, h, PCIE_REGMAX); 671 } 672 673 static struct resource * 674 thunder_pem_alloc_resource(device_t dev, device_t child, int type, int *rid, 675 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 676 { 677 struct thunder_pem_softc *sc = device_get_softc(dev); 678 struct resource *res; 679 device_t parent_dev; 680 681 switch (type) { 682 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 683 case PCI_RES_BUS: 684 return (pci_domain_alloc_bus(sc->id, child, rid, start, end, 685 count, flags)); 686 #endif 687 case SYS_RES_IOPORT: 688 case SYS_RES_MEMORY: 689 break; 690 default: 691 /* Find parent device. On ThunderX we know an exact path. */ 692 parent_dev = device_get_parent(device_get_parent(dev)); 693 return (BUS_ALLOC_RESOURCE(parent_dev, dev, type, rid, start, 694 end, count, flags)); 695 } 696 697 if (!RMAN_IS_DEFAULT_RANGE(start, end)) { 698 /* 699 * We might get PHYS addresses here inherited from EFI. 700 * Convert to PCI if necessary. 701 */ 702 if (range_addr_is_phys(sc->ranges, start, count)) { 703 start = range_addr_phys_to_pci(sc->ranges, start); 704 end = start + count - 1; 705 } 706 } 707 708 if (bootverbose) { 709 device_printf(dev, 710 "thunder_pem_alloc_resource: start=%#lx, end=%#lx, count=%#lx\n", 711 start, end, count); 712 } 713 714 res = bus_generic_rman_alloc_resource(dev, child, type, rid, start, 715 end, count, flags); 716 if (res == NULL && bootverbose) { 717 device_printf(dev, "%s FAIL: type=%d, rid=%d, " 718 "start=%016lx, end=%016lx, count=%016lx, flags=%x\n", 719 __func__, type, *rid, start, end, count, flags); 720 } 721 722 return (res); 723 } 724 725 static int 726 thunder_pem_release_resource(device_t dev, device_t child, int type, int rid, 727 struct resource *res) 728 { 729 device_t parent_dev; 730 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 731 struct thunder_pem_softc *sc = device_get_softc(dev); 732 #endif 733 734 switch (type) { 735 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 736 case PCI_RES_BUS: 737 return (pci_domain_release_bus(sc->id, child, rid, res)); 738 #endif 739 case SYS_RES_MEMORY: 740 case SYS_RES_IOPORT: 741 return (bus_generic_rman_release_resource(dev, child, type, 742 rid, res)); 743 default: 744 /* Find parent device. On ThunderX we know an exact path. */ 745 parent_dev = device_get_parent(device_get_parent(dev)); 746 return (BUS_RELEASE_RESOURCE(parent_dev, child, 747 type, rid, res)); 748 } 749 } 750 751 static struct rman * 752 thunder_pem_get_rman(device_t bus, int type, u_int flags) 753 { 754 struct thunder_pem_softc *sc; 755 756 sc = device_get_softc(bus); 757 switch (type) { 758 case SYS_RES_IOPORT: 759 return (&sc->io_rman); 760 case SYS_RES_MEMORY: 761 return (&sc->mem_rman); 762 default: 763 break; 764 } 765 766 return (NULL); 767 } 768 769 static int 770 thunder_pem_probe(device_t dev) 771 { 772 uint16_t pci_vendor_id; 773 uint16_t pci_device_id; 774 775 pci_vendor_id = pci_get_vendor(dev); 776 pci_device_id = pci_get_device(dev); 777 778 if ((pci_vendor_id == THUNDER_PEM_VENDOR_ID) && 779 (pci_device_id == THUNDER_PEM_DEVICE_ID)) { 780 device_set_desc_copy(dev, THUNDER_PEM_DESC); 781 return (0); 782 } 783 784 return (ENXIO); 785 } 786 787 static int 788 thunder_pem_attach(device_t dev) 789 { 790 struct resource_map_request req; 791 struct resource_map map; 792 devclass_t pci_class; 793 device_t parent; 794 struct thunder_pem_softc *sc; 795 int error; 796 int rid; 797 int tuple; 798 uint64_t base, size; 799 struct rman *rman; 800 801 sc = device_get_softc(dev); 802 sc->dev = dev; 803 804 /* Allocate memory for resource */ 805 pci_class = devclass_find("pci"); 806 parent = device_get_parent(dev); 807 if (device_get_devclass(parent) == pci_class) 808 rid = PCIR_BAR(0); 809 else 810 rid = RID_PEM_SPACE; 811 812 sc->reg = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 813 &rid, RF_ACTIVE | RF_UNMAPPED); 814 if (sc->reg == NULL) { 815 device_printf(dev, "Failed to allocate resource\n"); 816 return (ENXIO); 817 } 818 resource_init_map_request(&req); 819 req.memattr = VM_MEMATTR_DEVICE_NP; 820 error = bus_map_resource(dev, SYS_RES_MEMORY, sc->reg, &req, &map); 821 if (error != 0) { 822 device_printf(dev, "could not map memory.\n"); 823 return (error); 824 } 825 rman_set_mapping(sc->reg, &map); 826 827 sc->reg_bst = rman_get_bustag(sc->reg); 828 sc->reg_bsh = rman_get_bushandle(sc->reg); 829 830 /* Create the parent DMA tag to pass down the coherent flag */ 831 error = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 832 1, 0, /* alignment, bounds */ 833 BUS_SPACE_MAXADDR, /* lowaddr */ 834 BUS_SPACE_MAXADDR, /* highaddr */ 835 NULL, NULL, /* filter, filterarg */ 836 BUS_SPACE_MAXSIZE, /* maxsize */ 837 BUS_SPACE_UNRESTRICTED, /* nsegments */ 838 BUS_SPACE_MAXSIZE, /* maxsegsize */ 839 BUS_DMA_COHERENT, /* flags */ 840 NULL, NULL, /* lockfunc, lockarg */ 841 &sc->dmat); 842 if (error != 0) 843 return (error); 844 845 /* Map SLI, do it only once */ 846 if (!sli0_s2m_regx_base) { 847 bus_space_map(sc->reg_bst, SLIX_S2M_REGX_ACC, 848 SLIX_S2M_REGX_ACC_SIZE, 0, &sli0_s2m_regx_base); 849 } 850 if (!sli1_s2m_regx_base) { 851 bus_space_map(sc->reg_bst, SLIX_S2M_REGX_ACC + 852 SLIX_S2M_REGX_ACC_SPACING, SLIX_S2M_REGX_ACC_SIZE, 0, 853 &sli1_s2m_regx_base); 854 } 855 856 if ((sli0_s2m_regx_base == 0) || (sli1_s2m_regx_base == 0)) { 857 device_printf(dev, 858 "bus_space_map failed to map slix_s2m_regx_base\n"); 859 goto fail; 860 } 861 862 /* Identify PEM */ 863 if (thunder_pem_identify(dev) != 0) 864 goto fail; 865 866 /* Initialize rman and allocate regions */ 867 sc->mem_rman.rm_type = RMAN_ARRAY; 868 sc->mem_rman.rm_descr = "PEM PCIe Memory"; 869 error = rman_init(&sc->mem_rman); 870 if (error != 0) { 871 device_printf(dev, "memory rman_init() failed. error = %d\n", 872 error); 873 goto fail; 874 } 875 sc->io_rman.rm_type = RMAN_ARRAY; 876 sc->io_rman.rm_descr = "PEM PCIe IO"; 877 error = rman_init(&sc->io_rman); 878 if (error != 0) { 879 device_printf(dev, "IO rman_init() failed. error = %d\n", 880 error); 881 goto fail_mem; 882 } 883 884 /* 885 * We ignore the values that may have been provided in FDT 886 * and configure ranges according to the below formula 887 * for all types of devices. This is because some DTBs provided 888 * by EFI do not have proper ranges property or don't have them 889 * at all. 890 */ 891 /* Fill memory window */ 892 sc->ranges[0].pci_base = PCI_MEMORY_BASE; 893 sc->ranges[0].size = PCI_MEMORY_SIZE; 894 sc->ranges[0].phys_base = sc->sli_window_base + SLI_PCI_OFFSET + 895 sc->ranges[0].pci_base; 896 sc->ranges[0].flags = SYS_RES_MEMORY; 897 898 /* Fill IO window */ 899 sc->ranges[1].pci_base = PCI_IO_BASE; 900 sc->ranges[1].size = PCI_IO_SIZE; 901 sc->ranges[1].phys_base = sc->sli_window_base + SLI_PCI_OFFSET + 902 sc->ranges[1].pci_base; 903 sc->ranges[1].flags = SYS_RES_IOPORT; 904 905 for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) { 906 base = sc->ranges[tuple].pci_base; 907 size = sc->ranges[tuple].size; 908 if (size == 0) 909 continue; /* empty range element */ 910 911 rman = thunder_pem_get_rman(dev, sc->ranges[tuple].flags, 0); 912 if (rman != NULL) 913 error = rman_manage_region(rman, base, 914 base + size - 1); 915 else 916 error = EINVAL; 917 if (error) { 918 device_printf(dev, 919 "rman_manage_region() failed. error = %d\n", error); 920 rman_fini(&sc->mem_rman); 921 return (error); 922 } 923 if (bootverbose) { 924 device_printf(dev, 925 "\tPCI addr: 0x%jx, CPU addr: 0x%jx, Size: 0x%jx, Flags:0x%jx\n", 926 sc->ranges[tuple].pci_base, 927 sc->ranges[tuple].phys_base, 928 sc->ranges[tuple].size, 929 sc->ranges[tuple].flags); 930 } 931 } 932 933 if (thunder_pem_init(sc)) { 934 device_printf(dev, "Failure during PEM init\n"); 935 goto fail_io; 936 } 937 938 device_add_child(dev, "pci", -1); 939 940 return (bus_generic_attach(dev)); 941 942 fail_io: 943 rman_fini(&sc->io_rman); 944 fail_mem: 945 rman_fini(&sc->mem_rman); 946 fail: 947 bus_free_resource(dev, SYS_RES_MEMORY, sc->reg); 948 return (ENXIO); 949 } 950 951 static void 952 thunder_pem_release_all(device_t dev) 953 { 954 struct thunder_pem_softc *sc; 955 956 sc = device_get_softc(dev); 957 958 rman_fini(&sc->io_rman); 959 rman_fini(&sc->mem_rman); 960 961 if (sc->reg != NULL) 962 bus_free_resource(dev, SYS_RES_MEMORY, sc->reg); 963 } 964 965 static int 966 thunder_pem_detach(device_t dev) 967 { 968 969 thunder_pem_release_all(dev); 970 971 return (0); 972 } 973