1 /*- 2 * Copyright (c) 2015 The FreeBSD Foundation 3 * All rights reserved. 4 * 5 * This software was developed by Semihalf under 6 * the sponsorship of the FreeBSD Foundation. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* PCIe external MAC root complex driver (PEM) for Cavium Thunder SOC */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include "opt_platform.h" 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/bus.h> 40 #include <sys/kernel.h> 41 #include <sys/malloc.h> 42 #include <sys/module.h> 43 #include <sys/rman.h> 44 #include <sys/endian.h> 45 46 #ifdef FDT 47 #include <dev/ofw/openfirm.h> 48 #include <dev/ofw/ofw_bus.h> 49 #include <dev/ofw/ofw_bus_subr.h> 50 #include <dev/ofw/ofw_pci.h> 51 #endif 52 53 #include <dev/pci/pcivar.h> 54 #include <dev/pci/pcireg.h> 55 #include <dev/pci/pci_host_generic.h> 56 #include <dev/pci/pcib_private.h> 57 58 #include <machine/bus.h> 59 #include <machine/resource.h> 60 #include <machine/smp.h> 61 #include <machine/intr.h> 62 63 #include <arm64/cavium/thunder_pcie_common.h> 64 #include <arm64/cavium/thunder_pcie_pem.h> 65 #include "pcib_if.h" 66 67 #define THUNDER_PEM_DEVICE_ID 0xa020 68 #define THUNDER_PEM_VENDOR_ID 0x177d 69 70 /* ThunderX specific defines */ 71 #define THUNDER_PEMn_REG_BASE(unit) (0x87e0c0000000UL | ((unit) << 24)) 72 #define PCIERC_CFG002 0x08 73 #define PCIERC_CFG006 0x18 74 #define PCIERC_CFG032 0x80 75 #define PCIERC_CFG006_SEC_BUS(reg) (((reg) >> 8) & 0xFF) 76 #define PEM_CFG_RD_REG_ALIGN(reg) ((reg) & ~0x3) 77 #define PEM_CFG_RD_REG_DATA(val) (((val) >> 32) & 0xFFFFFFFF) 78 #define PEM_CFG_RD 0x30 79 #define PEM_CFG_LINK_MASK 0x3 80 #define PEM_CFG_LINK_RDY 0x3 81 #define PEM_CFG_SLIX_TO_REG(slix) ((slix) << 4) 82 #define SBNUM_OFFSET 0x8 83 #define SBNUM_MASK 0xFF 84 #define PEM_ON_REG 0x420 85 #define PEM_CTL_STATUS 0x0 86 #define PEM_LINK_ENABLE (1 << 4) 87 #define PEM_LINK_DLLA (1 << 29) 88 #define PEM_LINK_LT (1 << 27) 89 #define PEM_BUS_SHIFT (24) 90 #define PEM_SLOT_SHIFT (19) 91 #define PEM_FUNC_SHIFT (16) 92 #define SLIX_S2M_REGX_ACC 0x874001000000UL 93 #define SLIX_S2M_REGX_ACC_SIZE 0x1000 94 #define SLIX_S2M_REGX_ACC_SPACING 0x001000000000UL 95 #define SLI_BASE 0x880000000000UL 96 #define SLI_WINDOW_SPACING 0x004000000000UL 97 #define SLI_PCI_OFFSET 0x001000000000UL 98 #define SLI_NODE_SHIFT (44) 99 #define SLI_NODE_MASK (3) 100 #define SLI_GROUP_SHIFT (40) 101 #define SLI_ID_SHIFT (24) 102 #define SLI_ID_MASK (7) 103 #define SLI_PEMS_PER_GROUP (3) 104 #define SLI_GROUPS_PER_NODE (2) 105 #define SLI_PEMS_PER_NODE (SLI_PEMS_PER_GROUP * SLI_GROUPS_PER_NODE) 106 #define SLI_ACC_REG_CNT (256) 107 108 /* 109 * Each PEM device creates its own bus with 110 * own address translation, so we can adjust bus addresses 111 * as we want. To support 32-bit cards let's assume 112 * PCI window assignment looks as following: 113 * 114 * 0x00000000 - 0x000FFFFF IO 115 * 0x00100000 - 0xFFFFFFFF Memory 116 */ 117 #define PCI_IO_BASE 0x00000000UL 118 #define PCI_IO_SIZE 0x00100000UL 119 #define PCI_MEMORY_BASE PCI_IO_SIZE 120 #define PCI_MEMORY_SIZE 0xFFF00000UL 121 122 #define RID_PEM_SPACE 1 123 124 static int thunder_pem_activate_resource(device_t, device_t, int, int, 125 struct resource *); 126 static int thunder_pem_adjust_resource(device_t, device_t, int, 127 struct resource *, rman_res_t, rman_res_t); 128 static struct resource * thunder_pem_alloc_resource(device_t, device_t, int, 129 int *, rman_res_t, rman_res_t, rman_res_t, u_int); 130 static int thunder_pem_alloc_msi(device_t, device_t, int, int, int *); 131 static int thunder_pem_release_msi(device_t, device_t, int, int *); 132 static int thunder_pem_alloc_msix(device_t, device_t, int *); 133 static int thunder_pem_release_msix(device_t, device_t, int); 134 static int thunder_pem_map_msi(device_t, device_t, int, uint64_t *, uint32_t *); 135 static int thunder_pem_get_id(device_t, device_t, enum pci_id_type, 136 uintptr_t *); 137 static int thunder_pem_attach(device_t); 138 static int thunder_pem_deactivate_resource(device_t, device_t, int, int, 139 struct resource *); 140 static int thunder_pem_detach(device_t); 141 static uint64_t thunder_pem_config_reg_read(struct thunder_pem_softc *, int); 142 static int thunder_pem_link_init(struct thunder_pem_softc *); 143 static int thunder_pem_maxslots(device_t); 144 static int thunder_pem_probe(device_t); 145 static uint32_t thunder_pem_read_config(device_t, u_int, u_int, u_int, u_int, 146 int); 147 static int thunder_pem_read_ivar(device_t, device_t, int, uintptr_t *); 148 static void thunder_pem_release_all(device_t); 149 static int thunder_pem_release_resource(device_t, device_t, int, int, 150 struct resource *); 151 static struct rman * thunder_pem_rman(struct thunder_pem_softc *, int); 152 static void thunder_pem_slix_s2m_regx_acc_modify(struct thunder_pem_softc *, 153 int, int); 154 static void thunder_pem_write_config(device_t, u_int, u_int, u_int, u_int, 155 uint32_t, int); 156 static int thunder_pem_write_ivar(device_t, device_t, int, uintptr_t); 157 158 /* Global handlers for SLI interface */ 159 static bus_space_handle_t sli0_s2m_regx_base = 0; 160 static bus_space_handle_t sli1_s2m_regx_base = 0; 161 162 static device_method_t thunder_pem_methods[] = { 163 /* Device interface */ 164 DEVMETHOD(device_probe, thunder_pem_probe), 165 DEVMETHOD(device_attach, thunder_pem_attach), 166 DEVMETHOD(device_detach, thunder_pem_detach), 167 168 /* Bus interface */ 169 DEVMETHOD(bus_read_ivar, thunder_pem_read_ivar), 170 DEVMETHOD(bus_write_ivar, thunder_pem_write_ivar), 171 DEVMETHOD(bus_alloc_resource, thunder_pem_alloc_resource), 172 DEVMETHOD(bus_release_resource, thunder_pem_release_resource), 173 DEVMETHOD(bus_adjust_resource, thunder_pem_adjust_resource), 174 DEVMETHOD(bus_activate_resource, thunder_pem_activate_resource), 175 DEVMETHOD(bus_deactivate_resource, thunder_pem_deactivate_resource), 176 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 177 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 178 179 /* pcib interface */ 180 DEVMETHOD(pcib_maxslots, thunder_pem_maxslots), 181 DEVMETHOD(pcib_read_config, thunder_pem_read_config), 182 DEVMETHOD(pcib_write_config, thunder_pem_write_config), 183 DEVMETHOD(pcib_alloc_msix, thunder_pem_alloc_msix), 184 DEVMETHOD(pcib_release_msix, thunder_pem_release_msix), 185 DEVMETHOD(pcib_alloc_msi, thunder_pem_alloc_msi), 186 DEVMETHOD(pcib_release_msi, thunder_pem_release_msi), 187 DEVMETHOD(pcib_map_msi, thunder_pem_map_msi), 188 DEVMETHOD(pcib_get_id, thunder_pem_get_id), 189 190 DEVMETHOD_END 191 }; 192 193 DEFINE_CLASS_0(pcib, thunder_pem_driver, thunder_pem_methods, 194 sizeof(struct thunder_pem_softc)); 195 196 static devclass_t thunder_pem_devclass; 197 extern struct bus_space memmap_bus; 198 199 DRIVER_MODULE(thunder_pem, pci, thunder_pem_driver, thunder_pem_devclass, 0, 0); 200 MODULE_DEPEND(thunder_pem, pci, 1, 1, 1); 201 202 static int 203 thunder_pem_maxslots(device_t dev) 204 { 205 206 #if 0 207 /* max slots per bus acc. to standard */ 208 return (PCI_SLOTMAX); 209 #else 210 /* 211 * ARM64TODO Workaround - otherwise an em(4) interface appears to be 212 * present on every PCI function on the bus to which it is connected 213 */ 214 return (0); 215 #endif 216 } 217 218 static int 219 thunder_pem_read_ivar(device_t dev, device_t child, int index, 220 uintptr_t *result) 221 { 222 struct thunder_pem_softc *sc; 223 int secondary_bus = 0; 224 225 sc = device_get_softc(dev); 226 227 if (index == PCIB_IVAR_BUS) { 228 secondary_bus = thunder_pem_config_reg_read(sc, PCIERC_CFG006); 229 *result = PCIERC_CFG006_SEC_BUS(secondary_bus); 230 return (0); 231 } 232 if (index == PCIB_IVAR_DOMAIN) { 233 *result = sc->id; 234 return (0); 235 } 236 237 return (ENOENT); 238 } 239 240 static int 241 thunder_pem_write_ivar(device_t dev, device_t child, int index, 242 uintptr_t value) 243 { 244 245 return (ENOENT); 246 } 247 248 static int 249 thunder_pem_activate_resource(device_t dev, device_t child, int type, int rid, 250 struct resource *r) 251 { 252 int err; 253 bus_addr_t paddr; 254 bus_size_t psize; 255 bus_space_handle_t vaddr; 256 struct thunder_pem_softc *sc; 257 258 if ((err = rman_activate_resource(r)) != 0) 259 return (err); 260 261 sc = device_get_softc(dev); 262 263 /* 264 * If this is a memory resource, map it into the kernel. 265 */ 266 if (type == SYS_RES_MEMORY || type == SYS_RES_IOPORT) { 267 paddr = (bus_addr_t)rman_get_start(r); 268 psize = (bus_size_t)rman_get_size(r); 269 270 paddr = range_addr_pci_to_phys(sc->ranges, paddr); 271 272 err = bus_space_map(&memmap_bus, paddr, psize, 0, &vaddr); 273 if (err != 0) { 274 rman_deactivate_resource(r); 275 return (err); 276 } 277 rman_set_bustag(r, &memmap_bus); 278 rman_set_virtual(r, (void *)vaddr); 279 rman_set_bushandle(r, vaddr); 280 } 281 return (0); 282 } 283 284 /* 285 * This function is an exact copy of nexus_deactivate_resource() 286 * Keep it up-to-date with all changes in nexus. To be removed 287 * once bus-mapping interface is developed. 288 */ 289 static int 290 thunder_pem_deactivate_resource(device_t bus, device_t child, int type, int rid, 291 struct resource *r) 292 { 293 bus_size_t psize; 294 bus_space_handle_t vaddr; 295 296 psize = (bus_size_t)rman_get_size(r); 297 vaddr = rman_get_bushandle(r); 298 299 if (vaddr != 0) { 300 bus_space_unmap(&memmap_bus, vaddr, psize); 301 rman_set_virtual(r, NULL); 302 rman_set_bushandle(r, 0); 303 } 304 305 return (rman_deactivate_resource(r)); 306 } 307 308 static int 309 thunder_pem_adjust_resource(device_t dev, device_t child, int type, 310 struct resource *res, rman_res_t start, rman_res_t end) 311 { 312 struct thunder_pem_softc *sc; 313 struct rman *rm; 314 315 sc = device_get_softc(dev); 316 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 317 if (type == PCI_RES_BUS) 318 return (pci_domain_adjust_bus(sc->id, child, res, start, end)); 319 #endif 320 321 rm = thunder_pem_rman(sc, type); 322 if (rm == NULL) 323 return (bus_generic_adjust_resource(dev, child, type, res, 324 start, end)); 325 if (!rman_is_region_manager(res, rm)) 326 /* 327 * This means a child device has a memory or I/O 328 * resource not from you which shouldn't happen. 329 */ 330 return (EINVAL); 331 return (rman_adjust_resource(res, start, end)); 332 } 333 334 static int 335 thunder_pem_alloc_msi(device_t pci, device_t child, int count, int maxcount, 336 int *irqs) 337 { 338 device_t bus; 339 340 bus = device_get_parent(pci); 341 return (PCIB_ALLOC_MSI(device_get_parent(bus), child, count, maxcount, 342 irqs)); 343 } 344 345 static int 346 thunder_pem_release_msi(device_t pci, device_t child, int count, int *irqs) 347 { 348 device_t bus; 349 350 bus = device_get_parent(pci); 351 return (PCIB_RELEASE_MSI(device_get_parent(bus), child, count, irqs)); 352 } 353 354 static int 355 thunder_pem_alloc_msix(device_t pci, device_t child, int *irq) 356 { 357 device_t bus; 358 359 bus = device_get_parent(pci); 360 return (PCIB_ALLOC_MSIX(device_get_parent(bus), child, irq)); 361 } 362 363 static int 364 thunder_pem_release_msix(device_t pci, device_t child, int irq) 365 { 366 device_t bus; 367 368 bus = device_get_parent(pci); 369 return (PCIB_RELEASE_MSIX(device_get_parent(bus), child, irq)); 370 } 371 372 static int 373 thunder_pem_map_msi(device_t pci, device_t child, int irq, uint64_t *addr, 374 uint32_t *data) 375 { 376 device_t bus; 377 378 bus = device_get_parent(pci); 379 return (PCIB_MAP_MSI(device_get_parent(bus), child, irq, addr, data)); 380 } 381 382 static int 383 thunder_pem_get_id(device_t pci, device_t child, enum pci_id_type type, 384 uintptr_t *id) 385 { 386 int bsf; 387 int pem; 388 389 if (type != PCI_ID_MSI) 390 return (pcib_get_id(pci, child, type, id)); 391 392 bsf = pci_get_rid(child); 393 394 /* PEM (PCIe MAC/root complex) number is equal to domain */ 395 pem = pci_get_domain(child); 396 397 /* 398 * Set appropriate device ID (passed by the HW along with 399 * the transaction to memory) for different root complex 400 * numbers using hard-coded domain portion for each group. 401 */ 402 if (pem < 3) 403 *id = (0x1 << PCI_RID_DOMAIN_SHIFT) | bsf; 404 else if (pem < 6) 405 *id = (0x3 << PCI_RID_DOMAIN_SHIFT) | bsf; 406 else if (pem < 9) 407 *id = (0x9 << PCI_RID_DOMAIN_SHIFT) | bsf; 408 else if (pem < 12) 409 *id = (0xB << PCI_RID_DOMAIN_SHIFT) | bsf; 410 else 411 return (ENXIO); 412 413 return (0); 414 } 415 416 static int 417 thunder_pem_identify(device_t dev) 418 { 419 struct thunder_pem_softc *sc; 420 rman_res_t start; 421 422 sc = device_get_softc(dev); 423 start = rman_get_start(sc->reg); 424 425 /* Calculate PEM designations from its address */ 426 sc->node = (start >> SLI_NODE_SHIFT) & SLI_NODE_MASK; 427 sc->id = ((start >> SLI_ID_SHIFT) & SLI_ID_MASK) + 428 (SLI_PEMS_PER_NODE * sc->node); 429 sc->sli = sc->id % SLI_PEMS_PER_GROUP; 430 sc->sli_group = (sc->id / SLI_PEMS_PER_GROUP) % SLI_GROUPS_PER_NODE; 431 sc->sli_window_base = SLI_BASE | 432 (((uint64_t)sc->node) << SLI_NODE_SHIFT) | 433 ((uint64_t)sc->sli_group << SLI_GROUP_SHIFT); 434 sc->sli_window_base += SLI_WINDOW_SPACING * sc->sli; 435 436 return (0); 437 } 438 439 static void 440 thunder_pem_slix_s2m_regx_acc_modify(struct thunder_pem_softc *sc, 441 int sli_group, int slix) 442 { 443 uint64_t regval; 444 bus_space_handle_t handle = 0; 445 446 KASSERT(slix >= 0 && slix <= SLI_ACC_REG_CNT, ("Invalid SLI index")); 447 448 if (sli_group == 0) 449 handle = sli0_s2m_regx_base; 450 else if (sli_group == 1) 451 handle = sli1_s2m_regx_base; 452 else 453 device_printf(sc->dev, "SLI group is not correct\n"); 454 455 if (handle) { 456 /* Clear lower 32-bits of the SLIx register */ 457 regval = bus_space_read_8(sc->reg_bst, handle, 458 PEM_CFG_SLIX_TO_REG(slix)); 459 regval &= ~(0xFFFFFFFFUL); 460 bus_space_write_8(sc->reg_bst, handle, 461 PEM_CFG_SLIX_TO_REG(slix), regval); 462 } 463 } 464 465 static int 466 thunder_pem_link_init(struct thunder_pem_softc *sc) 467 { 468 uint64_t regval; 469 470 /* check whether PEM is safe to access. */ 471 regval = bus_space_read_8(sc->reg_bst, sc->reg_bsh, PEM_ON_REG); 472 if ((regval & PEM_CFG_LINK_MASK) != PEM_CFG_LINK_RDY) { 473 device_printf(sc->dev, "PEM%d is not ON\n", sc->id); 474 return (ENXIO); 475 } 476 477 regval = bus_space_read_8(sc->reg_bst, sc->reg_bsh, PEM_CTL_STATUS); 478 regval |= PEM_LINK_ENABLE; 479 bus_space_write_8(sc->reg_bst, sc->reg_bsh, PEM_CTL_STATUS, regval); 480 481 /* Wait 1ms as per Cavium specification */ 482 DELAY(1000); 483 484 regval = thunder_pem_config_reg_read(sc, PCIERC_CFG032); 485 486 if (((regval & PEM_LINK_DLLA) == 0) || ((regval & PEM_LINK_LT) != 0)) { 487 device_printf(sc->dev, "PCIe RC: Port %d Link Timeout\n", 488 sc->id); 489 return (ENXIO); 490 } 491 492 return (0); 493 } 494 495 static int 496 thunder_pem_init(struct thunder_pem_softc *sc) 497 { 498 int i, retval = 0; 499 500 retval = thunder_pem_link_init(sc); 501 if (retval) { 502 device_printf(sc->dev, "%s failed\n", __func__); 503 return retval; 504 } 505 506 /* To support 32-bit PCIe devices, set S2M_REGx_ACC[BA]=0x0 */ 507 for (i = 0; i < SLI_ACC_REG_CNT; i++) { 508 thunder_pem_slix_s2m_regx_acc_modify(sc, sc->sli_group, i); 509 } 510 511 return (retval); 512 } 513 514 static uint64_t 515 thunder_pem_config_reg_read(struct thunder_pem_softc *sc, int reg) 516 { 517 uint64_t data; 518 519 /* Write to ADDR register */ 520 bus_space_write_8(sc->reg_bst, sc->reg_bsh, PEM_CFG_RD, 521 PEM_CFG_RD_REG_ALIGN(reg)); 522 bus_space_barrier(sc->reg_bst, sc->reg_bsh, PEM_CFG_RD, 8, 523 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 524 /* Read from DATA register */ 525 data = PEM_CFG_RD_REG_DATA(bus_space_read_8(sc->reg_bst, sc->reg_bsh, 526 PEM_CFG_RD)); 527 528 return (data); 529 } 530 531 static uint32_t 532 thunder_pem_read_config(device_t dev, u_int bus, u_int slot, 533 u_int func, u_int reg, int bytes) 534 { 535 uint64_t offset; 536 uint32_t data; 537 struct thunder_pem_softc *sc; 538 bus_space_tag_t t; 539 bus_space_handle_t h; 540 541 if ((bus > PCI_BUSMAX) || (slot > PCI_SLOTMAX) || 542 (func > PCI_FUNCMAX) || (reg > PCIE_REGMAX)) 543 return (~0U); 544 545 sc = device_get_softc(dev); 546 547 /* Calculate offset */ 548 offset = (bus << PEM_BUS_SHIFT) | (slot << PEM_SLOT_SHIFT) | 549 (func << PEM_FUNC_SHIFT); 550 t = sc->reg_bst; 551 h = sc->pem_sli_base; 552 553 bus_space_map(sc->reg_bst, sc->sli_window_base + offset, 554 PCIE_REGMAX, 0, &h); 555 556 switch (bytes) { 557 case 1: 558 data = bus_space_read_1(t, h, reg); 559 break; 560 case 2: 561 data = le16toh(bus_space_read_2(t, h, reg)); 562 break; 563 case 4: 564 data = le32toh(bus_space_read_4(t, h, reg)); 565 break; 566 default: 567 data = ~0U; 568 break; 569 } 570 571 bus_space_unmap(sc->reg_bst, h, PCIE_REGMAX); 572 573 return (data); 574 } 575 576 static void 577 thunder_pem_write_config(device_t dev, u_int bus, u_int slot, 578 u_int func, u_int reg, uint32_t val, int bytes) 579 { 580 uint64_t offset; 581 struct thunder_pem_softc *sc; 582 bus_space_tag_t t; 583 bus_space_handle_t h; 584 585 if ((bus > PCI_BUSMAX) || (slot > PCI_SLOTMAX) || 586 (func > PCI_FUNCMAX) || (reg > PCIE_REGMAX)) 587 return; 588 589 sc = device_get_softc(dev); 590 591 /* Calculate offset */ 592 offset = (bus << PEM_BUS_SHIFT) | (slot << PEM_SLOT_SHIFT) | 593 (func << PEM_FUNC_SHIFT); 594 t = sc->reg_bst; 595 h = sc->pem_sli_base; 596 597 bus_space_map(sc->reg_bst, sc->sli_window_base + offset, 598 PCIE_REGMAX, 0, &h); 599 600 switch (bytes) { 601 case 1: 602 bus_space_write_1(t, h, reg, val); 603 break; 604 case 2: 605 bus_space_write_2(t, h, reg, htole16(val)); 606 break; 607 case 4: 608 bus_space_write_4(t, h, reg, htole32(val)); 609 break; 610 default: 611 break; 612 } 613 614 bus_space_unmap(sc->reg_bst, h, PCIE_REGMAX); 615 } 616 617 static struct resource * 618 thunder_pem_alloc_resource(device_t dev, device_t child, int type, int *rid, 619 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 620 { 621 struct thunder_pem_softc *sc = device_get_softc(dev); 622 struct rman *rm = NULL; 623 struct resource *res; 624 device_t parent_dev; 625 626 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 627 if (type == PCI_RES_BUS) 628 return (pci_domain_alloc_bus(sc->id, child, rid, start, end, 629 count, flags)); 630 #endif 631 rm = thunder_pem_rman(sc, type); 632 if (rm == NULL) { 633 /* Find parent device. On ThunderX we know an exact path. */ 634 parent_dev = device_get_parent(device_get_parent(dev)); 635 return (BUS_ALLOC_RESOURCE(parent_dev, dev, type, rid, start, 636 end, count, flags)); 637 } 638 639 640 if (!RMAN_IS_DEFAULT_RANGE(start, end)) { 641 /* 642 * We might get PHYS addresses here inherited from EFI. 643 * Convert to PCI if necessary. 644 */ 645 if (range_addr_is_phys(sc->ranges, start, count)) { 646 start = range_addr_phys_to_pci(sc->ranges, start); 647 end = start + count - 1; 648 } 649 650 } 651 652 if (bootverbose) { 653 device_printf(dev, 654 "thunder_pem_alloc_resource: start=%#lx, end=%#lx, count=%#lx\n", 655 start, end, count); 656 } 657 658 res = rman_reserve_resource(rm, start, end, count, flags, child); 659 if (res == NULL) 660 goto fail; 661 662 rman_set_rid(res, *rid); 663 664 if (flags & RF_ACTIVE) 665 if (bus_activate_resource(child, type, *rid, res)) { 666 rman_release_resource(res); 667 goto fail; 668 } 669 670 return (res); 671 672 fail: 673 if (bootverbose) { 674 device_printf(dev, "%s FAIL: type=%d, rid=%d, " 675 "start=%016lx, end=%016lx, count=%016lx, flags=%x\n", 676 __func__, type, *rid, start, end, count, flags); 677 } 678 679 return (NULL); 680 } 681 682 static int 683 thunder_pem_release_resource(device_t dev, device_t child, int type, int rid, 684 struct resource *res) 685 { 686 device_t parent_dev; 687 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 688 struct thunder_pem_softc *sc = device_get_softc(dev); 689 690 if (type == PCI_RES_BUS) 691 return (pci_domain_release_bus(sc->id, child, rid, res)); 692 #endif 693 /* Find parent device. On ThunderX we know an exact path. */ 694 parent_dev = device_get_parent(device_get_parent(dev)); 695 696 if ((type != SYS_RES_MEMORY) && (type != SYS_RES_IOPORT)) 697 return (BUS_RELEASE_RESOURCE(parent_dev, child, 698 type, rid, res)); 699 700 return (rman_release_resource(res)); 701 } 702 703 static struct rman * 704 thunder_pem_rman(struct thunder_pem_softc *sc, int type) 705 { 706 707 switch (type) { 708 case SYS_RES_IOPORT: 709 return (&sc->io_rman); 710 case SYS_RES_MEMORY: 711 return (&sc->mem_rman); 712 default: 713 break; 714 } 715 716 return (NULL); 717 } 718 719 static int 720 thunder_pem_probe(device_t dev) 721 { 722 uint16_t pci_vendor_id; 723 uint16_t pci_device_id; 724 725 pci_vendor_id = pci_get_vendor(dev); 726 pci_device_id = pci_get_device(dev); 727 728 if ((pci_vendor_id == THUNDER_PEM_VENDOR_ID) && 729 (pci_device_id == THUNDER_PEM_DEVICE_ID)) { 730 device_set_desc_copy(dev, THUNDER_PEM_DESC); 731 return (0); 732 } 733 734 return (ENXIO); 735 } 736 737 static int 738 thunder_pem_attach(device_t dev) 739 { 740 devclass_t pci_class; 741 device_t parent; 742 struct thunder_pem_softc *sc; 743 int error; 744 int rid; 745 int tuple; 746 uint64_t base, size; 747 struct rman *rman; 748 749 sc = device_get_softc(dev); 750 sc->dev = dev; 751 752 /* Allocate memory for resource */ 753 pci_class = devclass_find("pci"); 754 parent = device_get_parent(dev); 755 if (device_get_devclass(parent) == pci_class) 756 rid = PCIR_BAR(0); 757 else 758 rid = RID_PEM_SPACE; 759 760 sc->reg = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 761 &rid, RF_ACTIVE); 762 if (sc->reg == NULL) { 763 device_printf(dev, "Failed to allocate resource\n"); 764 return (ENXIO); 765 } 766 sc->reg_bst = rman_get_bustag(sc->reg); 767 sc->reg_bsh = rman_get_bushandle(sc->reg); 768 769 /* Map SLI, do it only once */ 770 if (!sli0_s2m_regx_base) { 771 bus_space_map(sc->reg_bst, SLIX_S2M_REGX_ACC, 772 SLIX_S2M_REGX_ACC_SIZE, 0, &sli0_s2m_regx_base); 773 } 774 if (!sli1_s2m_regx_base) { 775 bus_space_map(sc->reg_bst, SLIX_S2M_REGX_ACC + 776 SLIX_S2M_REGX_ACC_SPACING, SLIX_S2M_REGX_ACC_SIZE, 0, 777 &sli1_s2m_regx_base); 778 } 779 780 if ((sli0_s2m_regx_base == 0) || (sli1_s2m_regx_base == 0)) { 781 device_printf(dev, 782 "bus_space_map failed to map slix_s2m_regx_base\n"); 783 goto fail; 784 } 785 786 /* Identify PEM */ 787 if (thunder_pem_identify(dev) != 0) 788 goto fail; 789 790 /* Initialize rman and allocate regions */ 791 sc->mem_rman.rm_type = RMAN_ARRAY; 792 sc->mem_rman.rm_descr = "PEM PCIe Memory"; 793 error = rman_init(&sc->mem_rman); 794 if (error != 0) { 795 device_printf(dev, "memory rman_init() failed. error = %d\n", 796 error); 797 goto fail; 798 } 799 sc->io_rman.rm_type = RMAN_ARRAY; 800 sc->io_rman.rm_descr = "PEM PCIe IO"; 801 error = rman_init(&sc->io_rman); 802 if (error != 0) { 803 device_printf(dev, "IO rman_init() failed. error = %d\n", 804 error); 805 goto fail_mem; 806 } 807 808 /* 809 * We ignore the values that may have been provided in FDT 810 * and configure ranges according to the below formula 811 * for all types of devices. This is because some DTBs provided 812 * by EFI do not have proper ranges property or don't have them 813 * at all. 814 */ 815 /* Fill memory window */ 816 sc->ranges[0].pci_base = PCI_MEMORY_BASE; 817 sc->ranges[0].size = PCI_MEMORY_SIZE; 818 sc->ranges[0].phys_base = sc->sli_window_base + SLI_PCI_OFFSET + 819 sc->ranges[0].pci_base; 820 sc->ranges[0].flags = SYS_RES_MEMORY; 821 822 /* Fill IO window */ 823 sc->ranges[1].pci_base = PCI_IO_BASE; 824 sc->ranges[1].size = PCI_IO_SIZE; 825 sc->ranges[1].phys_base = sc->sli_window_base + SLI_PCI_OFFSET + 826 sc->ranges[1].pci_base; 827 sc->ranges[1].flags = SYS_RES_IOPORT; 828 829 for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) { 830 base = sc->ranges[tuple].pci_base; 831 size = sc->ranges[tuple].size; 832 if (size == 0) 833 continue; /* empty range element */ 834 835 rman = thunder_pem_rman(sc, sc->ranges[tuple].flags); 836 if (rman != NULL) 837 error = rman_manage_region(rman, base, 838 base + size - 1); 839 else 840 error = EINVAL; 841 if (error) { 842 device_printf(dev, 843 "rman_manage_region() failed. error = %d\n", error); 844 rman_fini(&sc->mem_rman); 845 return (error); 846 } 847 if (bootverbose) { 848 device_printf(dev, 849 "\tPCI addr: 0x%jx, CPU addr: 0x%jx, Size: 0x%jx, Flags:0x%jx\n", 850 sc->ranges[tuple].pci_base, 851 sc->ranges[tuple].phys_base, 852 sc->ranges[tuple].size, 853 sc->ranges[tuple].flags); 854 } 855 } 856 857 if (thunder_pem_init(sc)) { 858 device_printf(dev, "Failure during PEM init\n"); 859 goto fail_io; 860 } 861 862 device_add_child(dev, "pci", -1); 863 864 return (bus_generic_attach(dev)); 865 866 fail_io: 867 rman_fini(&sc->io_rman); 868 fail_mem: 869 rman_fini(&sc->mem_rman); 870 fail: 871 bus_free_resource(dev, SYS_RES_MEMORY, sc->reg); 872 return (ENXIO); 873 } 874 875 static void 876 thunder_pem_release_all(device_t dev) 877 { 878 struct thunder_pem_softc *sc; 879 880 sc = device_get_softc(dev); 881 882 rman_fini(&sc->io_rman); 883 rman_fini(&sc->mem_rman); 884 885 if (sc->reg != NULL) 886 bus_free_resource(dev, SYS_RES_MEMORY, sc->reg); 887 } 888 889 static int 890 thunder_pem_detach(device_t dev) 891 { 892 893 thunder_pem_release_all(dev); 894 895 return (0); 896 } 897