1 /* 2 * Copyright (C) 2016 Cavium Inc. 3 * All rights reserved. 4 * 5 * Developed by Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 #include "opt_platform.h" 29 30 #include <sys/cdefs.h> 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/malloc.h> 34 #include <sys/types.h> 35 #include <sys/sysctl.h> 36 #include <sys/kernel.h> 37 #include <sys/rman.h> 38 #include <sys/module.h> 39 #include <sys/bus.h> 40 #include <sys/endian.h> 41 #include <sys/cpuset.h> 42 43 #include <dev/ofw/openfirm.h> 44 #include <dev/ofw/ofw_bus.h> 45 #include <dev/ofw/ofw_bus_subr.h> 46 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pci_host_generic.h> 50 #include <dev/pci/pci_host_generic_fdt.h> 51 #include <dev/pci/pcib_private.h> 52 53 #include "thunder_pcie_common.h" 54 55 #include "pcib_if.h" 56 57 #ifdef THUNDERX_PASS_1_1_ERRATA 58 static struct resource * thunder_pcie_fdt_alloc_resource(device_t, device_t, 59 int, int *, rman_res_t, rman_res_t, rman_res_t, u_int); 60 static int thunder_pcie_fdt_release_resource(device_t, device_t, 61 int, int, struct resource*); 62 #endif 63 static int thunder_pcie_fdt_attach(device_t); 64 static int thunder_pcie_fdt_probe(device_t); 65 static int thunder_pcie_fdt_get_id(device_t, device_t, enum pci_id_type, 66 uintptr_t *); 67 68 static const struct ofw_bus_devinfo *thunder_pcie_ofw_get_devinfo(device_t, 69 device_t); 70 71 /* OFW bus interface */ 72 struct thunder_pcie_ofw_devinfo { 73 struct ofw_bus_devinfo di_dinfo; 74 struct resource_list di_rl; 75 }; 76 77 static device_method_t thunder_pcie_fdt_methods[] = { 78 /* Device interface */ 79 DEVMETHOD(device_probe, thunder_pcie_fdt_probe), 80 DEVMETHOD(device_attach, thunder_pcie_fdt_attach), 81 #ifdef THUNDERX_PASS_1_1_ERRATA 82 DEVMETHOD(bus_alloc_resource, thunder_pcie_fdt_alloc_resource), 83 DEVMETHOD(bus_release_resource, thunder_pcie_fdt_release_resource), 84 #endif 85 86 /* pcib interface */ 87 DEVMETHOD(pcib_get_id, thunder_pcie_fdt_get_id), 88 89 /* ofw interface */ 90 DEVMETHOD(ofw_bus_get_devinfo, thunder_pcie_ofw_get_devinfo), 91 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), 92 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), 93 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), 94 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), 95 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), 96 97 /* End */ 98 DEVMETHOD_END 99 }; 100 101 DEFINE_CLASS_1(pcib, thunder_pcie_fdt_driver, thunder_pcie_fdt_methods, 102 sizeof(struct generic_pcie_fdt_softc), generic_pcie_fdt_driver); 103 104 DRIVER_MODULE(thunder_pcib, simplebus, thunder_pcie_fdt_driver, 0, 0); 105 DRIVER_MODULE(thunder_pcib, ofwbus, thunder_pcie_fdt_driver, 0, 0); 106 107 static const struct ofw_bus_devinfo * 108 thunder_pcie_ofw_get_devinfo(device_t bus __unused, device_t child) 109 { 110 struct thunder_pcie_ofw_devinfo *di; 111 112 di = device_get_ivars(child); 113 return (&di->di_dinfo); 114 } 115 116 static void 117 get_addr_size_cells(phandle_t node, pcell_t *addr_cells, pcell_t *size_cells) 118 { 119 120 *addr_cells = 2; 121 /* Find address cells if present */ 122 OF_getencprop(node, "#address-cells", addr_cells, sizeof(*addr_cells)); 123 124 *size_cells = 2; 125 /* Find size cells if present */ 126 OF_getencprop(node, "#size-cells", size_cells, sizeof(*size_cells)); 127 } 128 129 static int 130 thunder_pcie_ofw_bus_attach(device_t dev) 131 { 132 struct thunder_pcie_ofw_devinfo *di; 133 device_t child; 134 phandle_t parent, node; 135 pcell_t addr_cells, size_cells; 136 137 parent = ofw_bus_get_node(dev); 138 if (parent > 0) { 139 get_addr_size_cells(parent, &addr_cells, &size_cells); 140 /* Iterate through all bus subordinates */ 141 for (node = OF_child(parent); node > 0; node = OF_peer(node)) { 142 /* Allocate and populate devinfo. */ 143 di = malloc(sizeof(*di), M_DEVBUF, M_WAITOK | M_ZERO); 144 if (ofw_bus_gen_setup_devinfo(&di->di_dinfo, node) != 0) { 145 free(di, M_DEVBUF); 146 continue; 147 } 148 149 /* Initialize and populate resource list. */ 150 resource_list_init(&di->di_rl); 151 ofw_bus_reg_to_rl(dev, node, addr_cells, size_cells, 152 &di->di_rl); 153 ofw_bus_intr_to_rl(dev, node, &di->di_rl, NULL); 154 155 /* Add newbus device for this FDT node */ 156 child = device_add_child(dev, NULL, -1); 157 if (child == NULL) { 158 resource_list_free(&di->di_rl); 159 ofw_bus_gen_destroy_devinfo(&di->di_dinfo); 160 free(di, M_DEVBUF); 161 continue; 162 } 163 164 device_set_ivars(child, di); 165 } 166 } 167 168 return (0); 169 } 170 171 static int 172 thunder_pcie_fdt_probe(device_t dev) 173 { 174 175 /* Check if we're running on Cavium ThunderX */ 176 if (!CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK, 177 CPU_IMPL_CAVIUM, CPU_PART_THUNDERX, 0, 0)) 178 return (ENXIO); 179 180 if (!ofw_bus_status_okay(dev)) 181 return (ENXIO); 182 183 if (ofw_bus_is_compatible(dev, "pci-host-ecam-generic") || 184 ofw_bus_is_compatible(dev, "cavium,thunder-pcie") || 185 ofw_bus_is_compatible(dev, "cavium,pci-host-thunder-ecam")) { 186 device_set_desc(dev, "Cavium Integrated PCI/PCI-E Controller"); 187 return (BUS_PROBE_DEFAULT); 188 } 189 190 return (ENXIO); 191 } 192 193 static int 194 thunder_pcie_fdt_attach(device_t dev) 195 { 196 struct generic_pcie_fdt_softc *sc; 197 198 sc = device_get_softc(dev); 199 thunder_pcie_identify_ecam(dev, &sc->base.ecam); 200 sc->base.coherent = 1; 201 202 /* Attach OFW bus */ 203 if (thunder_pcie_ofw_bus_attach(dev) != 0) 204 return (ENXIO); 205 206 return (pci_host_generic_fdt_attach(dev)); 207 } 208 209 static int 210 thunder_pcie_fdt_get_id(device_t pci, device_t child, enum pci_id_type type, 211 uintptr_t *id) 212 { 213 phandle_t node; 214 int bsf; 215 216 if (type != PCI_ID_MSI) 217 return (pcib_get_id(pci, child, type, id)); 218 219 node = ofw_bus_get_node(pci); 220 if (OF_hasprop(node, "msi-map")) 221 return (generic_pcie_get_id(pci, child, type, id)); 222 223 bsf = pci_get_rid(child); 224 *id = (pci_get_domain(child) << PCI_RID_DOMAIN_SHIFT) | bsf; 225 226 return (0); 227 } 228 229 #ifdef THUNDERX_PASS_1_1_ERRATA 230 struct resource * 231 thunder_pcie_fdt_alloc_resource(device_t dev, device_t child, int type, 232 int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 233 { 234 struct generic_pcie_fdt_softc *sc; 235 struct thunder_pcie_ofw_devinfo *di; 236 struct resource_list_entry *rle; 237 int i; 238 239 /* 240 * For PCIe devices that do not have FDT nodes pass 241 * the request to the core driver. 242 */ 243 if ((int)ofw_bus_get_node(child) <= 0) 244 return (thunder_pcie_alloc_resource(dev, child, type, 245 rid, start, end, count, flags)); 246 247 /* For other devices use OFW method */ 248 sc = device_get_softc(dev); 249 250 if (RMAN_IS_DEFAULT_RANGE(start, end)) { 251 if ((di = device_get_ivars(child)) == NULL) 252 return (NULL); 253 if (type == SYS_RES_IOPORT) 254 type = SYS_RES_MEMORY; 255 256 /* Find defaults for this rid */ 257 rle = resource_list_find(&di->di_rl, type, *rid); 258 if (rle == NULL) 259 return (NULL); 260 261 start = rle->start; 262 end = rle->end; 263 count = rle->count; 264 } 265 266 if (type == SYS_RES_MEMORY) { 267 /* Remap through ranges property */ 268 for (i = 0; i < MAX_RANGES_TUPLES; i++) { 269 if (start >= sc->base.ranges[i].phys_base && 270 end < (sc->base.ranges[i].pci_base + 271 sc->base.ranges[i].size)) { 272 start -= sc->base.ranges[i].phys_base; 273 start += sc->base.ranges[i].pci_base; 274 end -= sc->base.ranges[i].phys_base; 275 end += sc->base.ranges[i].pci_base; 276 break; 277 } 278 } 279 280 if (i == MAX_RANGES_TUPLES) { 281 device_printf(dev, "Could not map resource " 282 "%#jx-%#jx\n", start, end); 283 return (NULL); 284 } 285 } 286 287 return (bus_generic_alloc_resource(dev, child, type, rid, start, 288 end, count, flags)); 289 } 290 291 static int 292 thunder_pcie_fdt_release_resource(device_t dev, device_t child, int type, 293 int rid, struct resource *res) 294 { 295 296 if ((int)ofw_bus_get_node(child) <= 0) 297 return (pci_host_generic_core_release_resource(dev, child, type, 298 rid, res)); 299 300 return (bus_generic_release_resource(dev, child, type, rid, res)); 301 } 302 #endif 303