1 /* $NetBSD: bcmgenetreg.h,v 1.2 2020/02/22 13:41:41 jmcneill Exp $ */ 2 3 /* derived from NetBSD's bcmgenetreg.h */ 4 5 /*- 6 * Copyright (c) 2020 Michael J Karels 7 * Copyright (c) 2020 Jared McNeill <jmcneill@invisible.ca> 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* 32 * Broadcom GENETv5 33 */ 34 35 #ifndef _BCMGENETREG_H 36 #define _BCMGENETREG_H 37 38 #define GENET_SYS_REV_CTRL 0x000 39 #define SYS_REV_MAJOR __BITS(27,24) 40 #define SYS_REV_MINOR __BITS(19,16) 41 #define REV_MAJOR 0xf000000 42 #define REV_MAJOR_SHIFT 24 43 #define REV_MAJOR_V5 6 44 #define REV_MINOR 0xf0000 45 #define REV_MINOR_SHIFT 16 46 #define REV_PHY 0xffff 47 #define GENET_SYS_PORT_CTRL 0x004 48 #define GENET_SYS_PORT_MODE_EXT_GPHY 3 49 #define GENET_SYS_RBUF_FLUSH_CTRL 0x008 50 #define GENET_SYS_RBUF_FLUSH_RESET __BIT(1) 51 #define GENET_SYS_TBUF_FLUSH_CTRL 0x00c 52 #define GENET_EXT_RGMII_OOB_CTRL 0x08c 53 #define GENET_EXT_RGMII_OOB_ID_MODE_DISABLE __BIT(16) 54 #define GENET_EXT_RGMII_OOB_RGMII_MODE_EN __BIT(6) 55 #define GENET_EXT_RGMII_OOB_OOB_DISABLE __BIT(5) 56 #define GENET_EXT_RGMII_OOB_RGMII_LINK __BIT(4) 57 #define GENET_INTRL2_CPU_STAT 0x200 58 #define GENET_INTRL2_CPU_CLEAR 0x208 59 #define GENET_INTRL2_CPU_STAT_MASK 0x20c 60 #define GENET_INTRL2_CPU_SET_MASK 0x210 61 #define GENET_INTRL2_CPU_CLEAR_MASK 0x214 62 #define GENET_IRQ_MDIO_ERROR __BIT(24) 63 #define GENET_IRQ_MDIO_DONE __BIT(23) 64 #define GENET_IRQ_TXDMA_DONE __BIT(16) 65 #define GENET_IRQ_RXDMA_DONE __BIT(13) 66 #define GENET_RBUF_CTRL 0x300 67 #define GENET_RBUF_BAD_DIS __BIT(2) 68 #define GENET_RBUF_ALIGN_2B __BIT(1) 69 #define GENET_RBUF_64B_EN __BIT(0) 70 #define GENET_RBUF_CHECK_CTRL 0x314 71 #define GENET_RBUF_CHECK_CTRL_EN __BIT(0) 72 #define GENET_RBUF_CHECK_SKIP_FCS __BIT(4) 73 #define GENET_RBUF_TBUF_SIZE_CTRL 0x3b4 74 #define GENET_TBUF_CTRL 0x600 75 #define GENET_UMAC_CMD 0x808 76 #define GENET_UMAC_CMD_LCL_LOOP_EN __BIT(15) 77 #define GENET_UMAC_CMD_SW_RESET __BIT(13) 78 #define GENET_UMAC_CMD_PROMISC __BIT(4) 79 #ifdef __BITS 80 #define GENET_UMAC_CMD_SPEED __BITS(3,2) 81 #define GENET_UMAC_CMD_SPEED_10 0 82 #define GENET_UMAC_CMD_SPEED_100 1 83 #define GENET_UMAC_CMD_SPEED_1000 2 84 #else 85 #define GENET_UMAC_CMD_SPEED (3 << 2) 86 #define GENET_UMAC_CMD_SPEED_10 (0 << 2) 87 #define GENET_UMAC_CMD_SPEED_100 (1 << 2) 88 #define GENET_UMAC_CMD_SPEED_1000 (2 << 2) 89 #define GENET_UMAC_CMD_CRC_FWD __BIT(6) 90 #endif 91 #define GENET_UMAC_CMD_RXEN __BIT(1) 92 #define GENET_UMAC_CMD_TXEN __BIT(0) 93 #define GENET_UMAC_MAC0 0x80c 94 #define GENET_UMAC_MAC1 0x810 95 #define GENET_UMAC_MAX_FRAME_LEN 0x814 96 #define GENET_UMAC_TX_FLUSH 0xb34 97 #define GENET_UMAC_MIB_CTRL 0xd80 98 #define GENET_UMAC_MIB_RESET_TX __BIT(2) 99 #define GENET_UMAC_MIB_RESET_RUNT __BIT(1) 100 #define GENET_UMAC_MIB_RESET_RX __BIT(0) 101 #define GENET_MDIO_CMD 0xe14 102 #define GENET_MDIO_START_BUSY __BIT(29) 103 #define GENET_MDIO_READ_FAILED __BIT(28) 104 #define GENET_MDIO_READ __BIT(27) 105 #define GENET_MDIO_WRITE __BIT(26) 106 #define GENET_MDIO_PMD __BITS(25,21) 107 #define GENET_MDIO_REG __BITS(20,16) 108 #define GENET_MDIO_ADDR_SHIFT 21 109 #define GENET_MDIO_REG_SHIFT 16 110 #define GENET_MDIO_VAL_MASK 0xffff 111 #define GENET_UMAC_MDF_CTRL 0xe50 112 #define GENET_UMAC_MDF_ADDR0(n) (0xe54 + (n) * 0x8) 113 #define GENET_UMAC_MDF_ADDR1(n) (0xe58 + (n) * 0x8) 114 #define GENET_MAX_MDF_FILTER 17 115 116 #define GENET_DMA_DESC_COUNT 256 117 #define GENET_DMA_DESC_SIZE 12 118 #define GENET_DMA_DEFAULT_QUEUE 16 119 120 #define GENET_DMA_RING_SIZE 0x40 121 #define GENET_DMA_RINGS_SIZE (GENET_DMA_RING_SIZE * (GENET_DMA_DEFAULT_QUEUE + 1)) 122 123 #define GENET_RX_BASE 0x2000 124 #define GENET_TX_BASE 0x4000 125 126 #define GENET_RX_DMA_RINGBASE(qid) (GENET_RX_BASE + 0xc00 + GENET_DMA_RING_SIZE * (qid)) 127 #define GENET_RX_DMA_WRITE_PTR_LO(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x00) 128 #define GENET_RX_DMA_WRITE_PTR_HI(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x04) 129 #define GENET_RX_DMA_PROD_INDEX(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x08) 130 #define GENET_RX_DMA_CONS_INDEX(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x0c) 131 #define GENET_RX_DMA_PROD_CONS_MASK 0xffff 132 #define GENET_RX_DMA_RING_BUF_SIZE(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x10) 133 #define GENET_RX_DMA_RING_BUF_SIZE_DESC_COUNT __BITS(31,16) 134 #define GENET_RX_DMA_RING_BUF_SIZE_BUF_LENGTH __BITS(15,0) 135 #define GENET_RX_DMA_RING_BUF_SIZE_DESC_SHIFT 16 136 #define GENET_RX_DMA_RING_BUF_SIZE_BUF_LEN_MASK 0xffff 137 #define GENET_RX_DMA_START_ADDR_LO(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x14) 138 #define GENET_RX_DMA_START_ADDR_HI(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x18) 139 #define GENET_RX_DMA_END_ADDR_LO(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x1c) 140 #define GENET_RX_DMA_END_ADDR_HI(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x20) 141 #define GENET_RX_DMA_XON_XOFF_THRES(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x28) 142 #define GENET_RX_DMA_XON_XOFF_THRES_LO __BITS(31,16) 143 #define GENET_RX_DMA_XON_XOFF_THRES_HI __BITS(15,0) 144 #define GENET_RX_DMA_XON_XOFF_THRES_LO_SHIFT 16 145 #define GENET_RX_DMA_READ_PTR_LO(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x2c) 146 #define GENET_RX_DMA_READ_PTR_HI(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x30) 147 148 #define GENET_TX_DMA_RINGBASE(qid) (GENET_TX_BASE + 0xc00 + GENET_DMA_RING_SIZE * (qid)) 149 #define GENET_TX_DMA_READ_PTR_LO(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x00) 150 #define GENET_TX_DMA_READ_PTR_HI(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x04) 151 #define GENET_TX_DMA_CONS_INDEX(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x08) 152 #define GENET_TX_DMA_PROD_INDEX(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x0c) 153 #define GENET_TX_DMA_PROD_CONS_MASK 0xffff 154 #define GENET_TX_DMA_RING_BUF_SIZE(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x10) 155 #define GENET_TX_DMA_RING_BUF_SIZE_DESC_COUNT __BITS(31,16) 156 #define GENET_TX_DMA_RING_BUF_SIZE_BUF_LENGTH __BITS(15,0) 157 #define GENET_TX_DMA_RING_BUF_SIZE_DESC_SHIFT 16 158 #define GENET_TX_DMA_RING_BUF_SIZE_BUF_LEN_MASK 0xffff 159 #define GENET_TX_DMA_START_ADDR_LO(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x14) 160 #define GENET_TX_DMA_START_ADDR_HI(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x18) 161 #define GENET_TX_DMA_END_ADDR_LO(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x1c) 162 #define GENET_TX_DMA_END_ADDR_HI(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x20) 163 #define GENET_TX_DMA_MBUF_DONE_THRES(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x24) 164 #define GENET_TX_DMA_FLOW_PERIOD(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x28) 165 #define GENET_TX_DMA_WRITE_PTR_LO(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x2c) 166 #define GENET_TX_DMA_WRITE_PTR_HI(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x30) 167 168 #define GENET_RX_DESC_STATUS(idx) (GENET_RX_BASE + GENET_DMA_DESC_SIZE * (idx) + 0x00) 169 #define GENET_RX_DESC_STATUS_BUFLEN __BITS(27,16) 170 #define GENET_RX_DESC_STATUS_BUFLEN_MASK 0xfff0000 171 #define GENET_RX_DESC_STATUS_BUFLEN_SHIFT 16 172 #define GENET_RX_DESC_STATUS_OWN __BIT(15) /* ??? */ 173 #define GENET_RX_DESC_STATUS_CKSUM_OK __BIT(15) 174 #define GENET_RX_DESC_STATUS_EOP __BIT(14) 175 #define GENET_RX_DESC_STATUS_SOP __BIT(13) 176 #define GENET_RX_DESC_STATUS_RX_ERROR __BIT(2) 177 #define GENET_RX_DESC_ADDRESS_LO(idx) (GENET_RX_BASE + GENET_DMA_DESC_SIZE * (idx) + 0x04) 178 #define GENET_RX_DESC_ADDRESS_HI(idx) (GENET_RX_BASE + GENET_DMA_DESC_SIZE * (idx) + 0x08) 179 180 #define GENET_TX_DESC_STATUS(idx) (GENET_TX_BASE + GENET_DMA_DESC_SIZE * (idx) + 0x00) 181 #define GENET_TX_DESC_STATUS_BUFLEN __BITS(27,16) 182 #define GENET_TX_DESC_STATUS_OWN __BIT(15) 183 #define GENET_TX_DESC_STATUS_EOP __BIT(14) 184 #define GENET_TX_DESC_STATUS_SOP __BIT(13) 185 #define GENET_TX_DESC_STATUS_QTAG __BITS(12,7) 186 #define GENET_TX_DESC_STATUS_CRC __BIT(6) 187 #define GENET_TX_DESC_STATUS_CKSUM __BIT(4) 188 #define GENET_TX_DESC_STATUS_BUFLEN_SHIFT 16 189 #define GENET_TX_DESC_STATUS_BUFLEN_MASK 0x7ff0000 190 #define GENET_TX_DESC_STATUS_QTAG_MASK 0x1f80 191 #define GENET_TX_DESC_ADDRESS_LO(idx) (GENET_TX_BASE + GENET_DMA_DESC_SIZE * (idx) + 0x04) 192 #define GENET_TX_DESC_ADDRESS_HI(idx) (GENET_TX_BASE + GENET_DMA_DESC_SIZE * (idx) + 0x08) 193 194 /* Status block prepended to tx/rx packets (optional) */ 195 struct statusblock { 196 u_int32_t status_buflen; 197 u_int32_t extstatus; 198 u_int32_t rxcsum; 199 u_int32_t spare1[9]; 200 u_int32_t txcsuminfo; 201 u_int32_t spare2[3]; 202 }; 203 204 /* bits in txcsuminfo */ 205 #define TXCSUM_LEN_VALID __BIT(31) 206 #define TXCSUM_OFF_SHIFT 16 207 #define TXCSUM_UDP __BIT(15) 208 209 #define GENET_RX_DMA_RING_CFG (GENET_RX_BASE + 0x1040 + 0x00) 210 #define GENET_RX_DMA_CTRL (GENET_RX_BASE + 0x1040 + 0x04) 211 #define GENET_RX_DMA_CTRL_RBUF_EN(qid) __BIT((qid) + 1) 212 #define GENET_RX_DMA_CTRL_EN __BIT(0) 213 #define GENET_RX_SCB_BURST_SIZE (GENET_RX_BASE + 0x1040 + 0x0c) 214 215 #define GENET_TX_DMA_RING_CFG (GENET_TX_BASE + 0x1040 + 0x00) 216 #define GENET_TX_DMA_CTRL (GENET_TX_BASE + 0x1040 + 0x04) 217 #define GENET_TX_DMA_CTRL_RBUF_EN(qid) __BIT((qid) + 1) 218 #define GENET_TX_DMA_CTRL_EN __BIT(0) 219 #define GENET_TX_SCB_BURST_SIZE (GENET_TX_BASE + 0x1040 + 0x0c) 220 221 #endif /* !_BCMGENETREG_H */ 222