1 /*- 2 * Copyright (c) 2019 Juniper Networks, Inc. 3 * Copyright (c) 2019 Semihalf. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/param.h> 32 #include <sys/bus.h> 33 #include <sys/kernel.h> 34 #include <sys/module.h> 35 #include <sys/rman.h> 36 #include <sys/systm.h> 37 38 #include <dev/fdt/simplebus.h> 39 #include <dev/ofw/ofw_bus_subr.h> 40 #include <dev/ofw/ofw_bus.h> 41 42 #include <machine/bus.h> 43 #include <machine/resource.h> 44 45 #include "mdio_if.h" 46 47 #define BLK_ADDR_REG_OFFSET 0x1f 48 #define PLL_AFE1_100MHZ_BLK 0x2100 49 #define PLL_CLK_AMP_OFFSET 0x03 50 #define PLL_CLK_AMP_2P05V 0x2b18 51 52 struct ns2_pcie_phy_softc { 53 uint32_t phy_id; 54 }; 55 56 static device_probe_t ns2_pcie_phy_fdt_probe; 57 static device_attach_t ns2_pcie_phy_fdt_attach; 58 59 static int ns2_pci_phy_init(device_t dev); 60 61 static device_method_t ns2_pcie_phy_fdt_methods[] = { 62 /* Device interface */ 63 DEVMETHOD(device_probe, ns2_pcie_phy_fdt_probe), 64 DEVMETHOD(device_attach, ns2_pcie_phy_fdt_attach), 65 66 DEVMETHOD_END 67 }; 68 69 DEFINE_CLASS_0(ns2_pcie_phy, ns2_pcie_phy_fdt_driver, ns2_pcie_phy_fdt_methods, 70 sizeof(struct ns2_pcie_phy_softc)); 71 72 static devclass_t ns2_pcie_phy_fdt_devclass; 73 74 static driver_t ns2_pcie_phy_driver = { 75 "ns2_pcie_phy", 76 ns2_pcie_phy_fdt_methods, 77 sizeof(struct ns2_pcie_phy_softc) 78 }; 79 EARLY_DRIVER_MODULE(ns2_pcie_phy, brcm_mdionexus, ns2_pcie_phy_driver, 80 ns2_pcie_phy_fdt_devclass, NULL, NULL, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); 81 82 static int 83 ns2_pci_phy_init(device_t dev) 84 { 85 struct ns2_pcie_phy_softc *sc; 86 int err; 87 88 sc = device_get_softc(dev); 89 90 /* select the AFE 100MHz block page */ 91 err = MDIO_WRITEREG(device_get_parent(dev), sc->phy_id, 92 BLK_ADDR_REG_OFFSET, PLL_AFE1_100MHZ_BLK); 93 if (err) 94 goto err; 95 96 /* set the 100 MHz reference clock amplitude to 2.05 v */ 97 err = MDIO_WRITEREG(device_get_parent(dev), sc->phy_id, 98 PLL_CLK_AMP_OFFSET, PLL_CLK_AMP_2P05V); 99 if (err) 100 goto err; 101 102 return 0; 103 104 err: 105 device_printf(dev, "Error %d writing to phy\n", err); 106 return (err); 107 } 108 109 static __inline void 110 get_addr_size_cells(phandle_t node, pcell_t *addr_cells, pcell_t *size_cells) 111 { 112 113 *addr_cells = 2; 114 /* Find address cells if present */ 115 OF_getencprop(node, "#address-cells", addr_cells, sizeof(*addr_cells)); 116 117 *size_cells = 2; 118 /* Find size cells if present */ 119 OF_getencprop(node, "#size-cells", size_cells, sizeof(*size_cells)); 120 } 121 122 static int 123 ns2_pcie_phy_fdt_probe(device_t dev) 124 { 125 126 if (!ofw_bus_status_okay(dev)) 127 return (ENXIO); 128 129 if (!ofw_bus_is_compatible(dev, "brcm,ns2-pcie-phy")) 130 return (ENXIO); 131 132 device_set_desc(dev, "Broadcom NS2 PCIe PHY"); 133 return (BUS_PROBE_SPECIFIC); 134 } 135 136 static int 137 ns2_pcie_phy_fdt_attach(device_t dev) 138 { 139 struct ns2_pcie_phy_softc *sc; 140 pcell_t addr_cells, size_cells, buf[2]; 141 phandle_t node; 142 143 sc = device_get_softc(dev); 144 145 node = ofw_bus_get_node(dev); 146 get_addr_size_cells(OF_parent(node), &addr_cells, &size_cells); 147 if ((addr_cells != 1) || (size_cells != 0)) { 148 device_printf(dev, 149 "Only addr_cells=1 and size_cells=0 are supported\n"); 150 return (EINVAL); 151 } 152 153 if (OF_getencprop(node, "reg", buf, sizeof(pcell_t)) < 0) 154 return (ENXIO); 155 156 sc->phy_id = buf[0]; 157 158 if (ns2_pci_phy_init(dev) < 0) 159 return (EINVAL); 160 161 return (bus_generic_attach(dev)); 162 } 163