1 /*- 2 * Copyright (c) 2019 Juniper Networks, Inc. 3 * Copyright (c) 2019 Semihalf. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/param.h> 32 #include <sys/bus.h> 33 #include <sys/kernel.h> 34 #include <sys/module.h> 35 #include <sys/rman.h> 36 #include <sys/systm.h> 37 38 #include <dev/fdt/simplebus.h> 39 #include <dev/ofw/ofw_bus_subr.h> 40 #include <dev/ofw/ofw_bus.h> 41 42 #include <machine/bus.h> 43 #include <machine/resource.h> 44 45 #include "mdio_if.h" 46 47 #define BLK_ADDR_REG_OFFSET 0x1f 48 #define PLL_AFE1_100MHZ_BLK 0x2100 49 #define PLL_CLK_AMP_OFFSET 0x03 50 #define PLL_CLK_AMP_2P05V 0x2b18 51 52 struct ns2_pcie_phy_softc { 53 uint32_t phy_id; 54 }; 55 56 static device_probe_t ns2_pcie_phy_fdt_probe; 57 static device_attach_t ns2_pcie_phy_fdt_attach; 58 59 static int ns2_pci_phy_init(device_t dev); 60 61 static device_method_t ns2_pcie_phy_fdt_methods[] = { 62 /* Device interface */ 63 DEVMETHOD(device_probe, ns2_pcie_phy_fdt_probe), 64 DEVMETHOD(device_attach, ns2_pcie_phy_fdt_attach), 65 66 DEVMETHOD_END 67 }; 68 69 DEFINE_CLASS_0(ns2_pcie_phy, ns2_pcie_phy_fdt_driver, ns2_pcie_phy_fdt_methods, 70 sizeof(struct ns2_pcie_phy_softc)); 71 72 static driver_t ns2_pcie_phy_driver = { 73 "ns2_pcie_phy", 74 ns2_pcie_phy_fdt_methods, 75 sizeof(struct ns2_pcie_phy_softc) 76 }; 77 78 EARLY_DRIVER_MODULE(ns2_pcie_phy, brcm_mdionexus, ns2_pcie_phy_driver, 79 NULL, NULL, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); 80 81 static int 82 ns2_pci_phy_init(device_t dev) 83 { 84 struct ns2_pcie_phy_softc *sc; 85 int err; 86 87 sc = device_get_softc(dev); 88 89 /* select the AFE 100MHz block page */ 90 err = MDIO_WRITEREG(device_get_parent(dev), sc->phy_id, 91 BLK_ADDR_REG_OFFSET, PLL_AFE1_100MHZ_BLK); 92 if (err) 93 goto err; 94 95 /* set the 100 MHz reference clock amplitude to 2.05 v */ 96 err = MDIO_WRITEREG(device_get_parent(dev), sc->phy_id, 97 PLL_CLK_AMP_OFFSET, PLL_CLK_AMP_2P05V); 98 if (err) 99 goto err; 100 101 return 0; 102 103 err: 104 device_printf(dev, "Error %d writing to phy\n", err); 105 return (err); 106 } 107 108 static __inline void 109 get_addr_size_cells(phandle_t node, pcell_t *addr_cells, pcell_t *size_cells) 110 { 111 112 *addr_cells = 2; 113 /* Find address cells if present */ 114 OF_getencprop(node, "#address-cells", addr_cells, sizeof(*addr_cells)); 115 116 *size_cells = 2; 117 /* Find size cells if present */ 118 OF_getencprop(node, "#size-cells", size_cells, sizeof(*size_cells)); 119 } 120 121 static int 122 ns2_pcie_phy_fdt_probe(device_t dev) 123 { 124 125 if (!ofw_bus_status_okay(dev)) 126 return (ENXIO); 127 128 if (!ofw_bus_is_compatible(dev, "brcm,ns2-pcie-phy")) 129 return (ENXIO); 130 131 device_set_desc(dev, "Broadcom NS2 PCIe PHY"); 132 return (BUS_PROBE_SPECIFIC); 133 } 134 135 static int 136 ns2_pcie_phy_fdt_attach(device_t dev) 137 { 138 struct ns2_pcie_phy_softc *sc; 139 pcell_t addr_cells, size_cells, buf[2]; 140 phandle_t node; 141 142 sc = device_get_softc(dev); 143 144 node = ofw_bus_get_node(dev); 145 get_addr_size_cells(OF_parent(node), &addr_cells, &size_cells); 146 if ((addr_cells != 1) || (size_cells != 0)) { 147 device_printf(dev, 148 "Only addr_cells=1 and size_cells=0 are supported\n"); 149 return (EINVAL); 150 } 151 152 if (OF_getencprop(node, "reg", buf, sizeof(pcell_t)) < 0) 153 return (ENXIO); 154 155 sc->phy_id = buf[0]; 156 157 if (ns2_pci_phy_init(dev) < 0) 158 return (EINVAL); 159 160 return (bus_generic_attach(dev)); 161 } 162