1 /*- 2 * Copyright (c) 2019 Juniper Networks, Inc. 3 * Copyright (c) 2019 Semihalf. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/param.h> 29 #include <sys/bus.h> 30 #include <sys/kernel.h> 31 #include <sys/module.h> 32 #include <sys/rman.h> 33 #include <sys/systm.h> 34 35 #include <dev/fdt/simplebus.h> 36 #include <dev/ofw/ofw_bus_subr.h> 37 #include <dev/ofw/ofw_bus.h> 38 39 #include <machine/bus.h> 40 #include <machine/resource.h> 41 42 #include "mdio_if.h" 43 44 #define BLK_ADDR_REG_OFFSET 0x1f 45 #define PLL_AFE1_100MHZ_BLK 0x2100 46 #define PLL_CLK_AMP_OFFSET 0x03 47 #define PLL_CLK_AMP_2P05V 0x2b18 48 49 struct ns2_pcie_phy_softc { 50 uint32_t phy_id; 51 }; 52 53 static device_probe_t ns2_pcie_phy_fdt_probe; 54 static device_attach_t ns2_pcie_phy_fdt_attach; 55 56 static int ns2_pci_phy_init(device_t dev); 57 58 static device_method_t ns2_pcie_phy_fdt_methods[] = { 59 /* Device interface */ 60 DEVMETHOD(device_probe, ns2_pcie_phy_fdt_probe), 61 DEVMETHOD(device_attach, ns2_pcie_phy_fdt_attach), 62 63 DEVMETHOD_END 64 }; 65 66 DEFINE_CLASS_0(ns2_pcie_phy, ns2_pcie_phy_fdt_driver, ns2_pcie_phy_fdt_methods, 67 sizeof(struct ns2_pcie_phy_softc)); 68 69 static driver_t ns2_pcie_phy_driver = { 70 "ns2_pcie_phy", 71 ns2_pcie_phy_fdt_methods, 72 sizeof(struct ns2_pcie_phy_softc) 73 }; 74 75 EARLY_DRIVER_MODULE(ns2_pcie_phy, brcm_mdionexus, ns2_pcie_phy_driver, 76 NULL, NULL, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); 77 78 static int 79 ns2_pci_phy_init(device_t dev) 80 { 81 struct ns2_pcie_phy_softc *sc; 82 int err; 83 84 sc = device_get_softc(dev); 85 86 /* select the AFE 100MHz block page */ 87 err = MDIO_WRITEREG(device_get_parent(dev), sc->phy_id, 88 BLK_ADDR_REG_OFFSET, PLL_AFE1_100MHZ_BLK); 89 if (err) 90 goto err; 91 92 /* set the 100 MHz reference clock amplitude to 2.05 v */ 93 err = MDIO_WRITEREG(device_get_parent(dev), sc->phy_id, 94 PLL_CLK_AMP_OFFSET, PLL_CLK_AMP_2P05V); 95 if (err) 96 goto err; 97 98 return 0; 99 100 err: 101 device_printf(dev, "Error %d writing to phy\n", err); 102 return (err); 103 } 104 105 static __inline void 106 get_addr_size_cells(phandle_t node, pcell_t *addr_cells, pcell_t *size_cells) 107 { 108 109 *addr_cells = 2; 110 /* Find address cells if present */ 111 OF_getencprop(node, "#address-cells", addr_cells, sizeof(*addr_cells)); 112 113 *size_cells = 2; 114 /* Find size cells if present */ 115 OF_getencprop(node, "#size-cells", size_cells, sizeof(*size_cells)); 116 } 117 118 static int 119 ns2_pcie_phy_fdt_probe(device_t dev) 120 { 121 122 if (!ofw_bus_status_okay(dev)) 123 return (ENXIO); 124 125 if (!ofw_bus_is_compatible(dev, "brcm,ns2-pcie-phy")) 126 return (ENXIO); 127 128 device_set_desc(dev, "Broadcom NS2 PCIe PHY"); 129 return (BUS_PROBE_SPECIFIC); 130 } 131 132 static int 133 ns2_pcie_phy_fdt_attach(device_t dev) 134 { 135 struct ns2_pcie_phy_softc *sc; 136 pcell_t addr_cells, size_cells, buf[2]; 137 phandle_t node; 138 139 sc = device_get_softc(dev); 140 141 node = ofw_bus_get_node(dev); 142 get_addr_size_cells(OF_parent(node), &addr_cells, &size_cells); 143 if ((addr_cells != 1) || (size_cells != 0)) { 144 device_printf(dev, 145 "Only addr_cells=1 and size_cells=0 are supported\n"); 146 return (EINVAL); 147 } 148 149 if (OF_getencprop(node, "reg", buf, sizeof(pcell_t)) < 0) 150 return (ENXIO); 151 152 sc->phy_id = buf[0]; 153 154 if (ns2_pci_phy_init(dev) < 0) 155 return (EINVAL); 156 157 return (bus_generic_attach(dev)); 158 } 159