1 /*- 2 * Copyright (c) 2019 Juniper Networks, Inc. 3 * Copyright (c) 2019 Semihalf. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 #include <sys/param.h> 30 #include <sys/bus.h> 31 #include <sys/kernel.h> 32 #include <sys/module.h> 33 #include <sys/rman.h> 34 #include <sys/systm.h> 35 36 #include <dev/fdt/simplebus.h> 37 #include <dev/ofw/ofw_bus_subr.h> 38 #include <dev/ofw/ofw_bus.h> 39 40 #include <machine/bus.h> 41 #include <machine/resource.h> 42 43 #include "mdio_if.h" 44 45 #define BLK_ADDR_REG_OFFSET 0x1f 46 #define PLL_AFE1_100MHZ_BLK 0x2100 47 #define PLL_CLK_AMP_OFFSET 0x03 48 #define PLL_CLK_AMP_2P05V 0x2b18 49 50 struct ns2_pcie_phy_softc { 51 uint32_t phy_id; 52 }; 53 54 static device_probe_t ns2_pcie_phy_fdt_probe; 55 static device_attach_t ns2_pcie_phy_fdt_attach; 56 57 static int ns2_pci_phy_init(device_t dev); 58 59 static device_method_t ns2_pcie_phy_fdt_methods[] = { 60 /* Device interface */ 61 DEVMETHOD(device_probe, ns2_pcie_phy_fdt_probe), 62 DEVMETHOD(device_attach, ns2_pcie_phy_fdt_attach), 63 64 DEVMETHOD_END 65 }; 66 67 DEFINE_CLASS_0(ns2_pcie_phy, ns2_pcie_phy_fdt_driver, ns2_pcie_phy_fdt_methods, 68 sizeof(struct ns2_pcie_phy_softc)); 69 70 static driver_t ns2_pcie_phy_driver = { 71 "ns2_pcie_phy", 72 ns2_pcie_phy_fdt_methods, 73 sizeof(struct ns2_pcie_phy_softc) 74 }; 75 76 EARLY_DRIVER_MODULE(ns2_pcie_phy, brcm_mdionexus, ns2_pcie_phy_driver, 77 NULL, NULL, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); 78 79 static int 80 ns2_pci_phy_init(device_t dev) 81 { 82 struct ns2_pcie_phy_softc *sc; 83 int err; 84 85 sc = device_get_softc(dev); 86 87 /* select the AFE 100MHz block page */ 88 err = MDIO_WRITEREG(device_get_parent(dev), sc->phy_id, 89 BLK_ADDR_REG_OFFSET, PLL_AFE1_100MHZ_BLK); 90 if (err) 91 goto err; 92 93 /* set the 100 MHz reference clock amplitude to 2.05 v */ 94 err = MDIO_WRITEREG(device_get_parent(dev), sc->phy_id, 95 PLL_CLK_AMP_OFFSET, PLL_CLK_AMP_2P05V); 96 if (err) 97 goto err; 98 99 return 0; 100 101 err: 102 device_printf(dev, "Error %d writing to phy\n", err); 103 return (err); 104 } 105 106 static __inline void 107 get_addr_size_cells(phandle_t node, pcell_t *addr_cells, pcell_t *size_cells) 108 { 109 110 *addr_cells = 2; 111 /* Find address cells if present */ 112 OF_getencprop(node, "#address-cells", addr_cells, sizeof(*addr_cells)); 113 114 *size_cells = 2; 115 /* Find size cells if present */ 116 OF_getencprop(node, "#size-cells", size_cells, sizeof(*size_cells)); 117 } 118 119 static int 120 ns2_pcie_phy_fdt_probe(device_t dev) 121 { 122 123 if (!ofw_bus_status_okay(dev)) 124 return (ENXIO); 125 126 if (!ofw_bus_is_compatible(dev, "brcm,ns2-pcie-phy")) 127 return (ENXIO); 128 129 device_set_desc(dev, "Broadcom NS2 PCIe PHY"); 130 return (BUS_PROBE_SPECIFIC); 131 } 132 133 static int 134 ns2_pcie_phy_fdt_attach(device_t dev) 135 { 136 struct ns2_pcie_phy_softc *sc; 137 pcell_t addr_cells, size_cells, buf[2]; 138 phandle_t node; 139 140 sc = device_get_softc(dev); 141 142 node = ofw_bus_get_node(dev); 143 get_addr_size_cells(OF_parent(node), &addr_cells, &size_cells); 144 if ((addr_cells != 1) || (size_cells != 0)) { 145 device_printf(dev, 146 "Only addr_cells=1 and size_cells=0 are supported\n"); 147 return (EINVAL); 148 } 149 150 if (OF_getencprop(node, "reg", buf, sizeof(pcell_t)) < 0) 151 return (ENXIO); 152 153 sc->phy_id = buf[0]; 154 155 if (ns2_pci_phy_init(dev) < 0) 156 return (EINVAL); 157 158 return (bus_generic_attach(dev)); 159 } 160