1 /*- 2 * Copyright (c) 2019 Juniper Networks, Inc. 3 * Copyright (c) 2019 Semihalf. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/param.h> 29 #include <sys/bus.h> 30 #include <sys/kernel.h> 31 #include <sys/module.h> 32 #include <sys/rman.h> 33 #include <sys/systm.h> 34 35 #include <dev/fdt/simplebus.h> 36 #include <dev/ofw/ofw_bus_subr.h> 37 #include <dev/ofw/ofw_bus.h> 38 39 #include <machine/bus.h> 40 #include <machine/resource.h> 41 42 #include "mdio_if.h" 43 44 #define REG_BASE_RID 0 45 46 #define MDIO_RATE_ADJ_EXT_OFFSET 0x000 47 #define MDIO_RATE_ADJ_INT_OFFSET 0x004 48 #define MDIO_RATE_ADJ_DIVIDENT_SHIFT 16 49 50 #define MDIO_SCAN_CTRL_OFFSET 0x008 51 #define MDIO_SCAN_CTRL_OVRIDE_EXT_MSTR 28 52 53 #define MDIO_PARAM_OFFSET 0x23c 54 #define MDIO_PARAM_MIIM_CYCLE 29 55 #define MDIO_PARAM_INTERNAL_SEL 25 56 #define MDIO_PARAM_BUS_ID 22 57 #define MDIO_PARAM_C45_SEL 21 58 #define MDIO_PARAM_PHY_ID 16 59 #define MDIO_PARAM_PHY_DATA 0 60 61 #define MDIO_READ_OFFSET 0x240 62 #define MDIO_READ_DATA_MASK 0xffff 63 #define MDIO_ADDR_OFFSET 0x244 64 65 #define MDIO_CTRL_OFFSET 0x248 66 #define MDIO_CTRL_WRITE_OP 0x1 67 #define MDIO_CTRL_READ_OP 0x2 68 69 #define MDIO_STAT_OFFSET 0x24c 70 #define MDIO_STAT_DONE 1 71 72 #define BUS_MAX_ADDR 32 73 #define EXT_BUS_START_ADDR 16 74 75 #define MDIO_REG_ADDR_SPACE_SIZE 0x250 76 77 #define MDIO_OPERATING_FREQUENCY 11000000 78 #define MDIO_RATE_ADJ_DIVIDENT 1 79 80 #define MII_ADDR_C45 (1<<30) 81 82 static int brcm_iproc_mdio_probe(device_t); 83 static int brcm_iproc_mdio_attach(device_t); 84 static int brcm_iproc_mdio_detach(device_t); 85 86 /* OFW bus interface */ 87 struct brcm_mdio_ofw_devinfo { 88 struct ofw_bus_devinfo di_dinfo; 89 struct resource_list di_rl; 90 }; 91 92 struct brcm_iproc_mdio_softc { 93 struct simplebus_softc sbus; 94 device_t dev; 95 struct resource * reg_base; 96 uint32_t clock_rate; 97 }; 98 99 MALLOC_DEFINE(M_BRCM_IPROC_MDIO, "Broadcom IPROC MDIO", 100 "Broadcom IPROC MDIO dynamic memory"); 101 102 static int brcm_iproc_config(struct brcm_iproc_mdio_softc*); 103 static const struct ofw_bus_devinfo * 104 brcm_iproc_mdio_get_devinfo(device_t, device_t); 105 static int brcm_iproc_mdio_write_mux(device_t, int, int, int, int); 106 static int brcm_iproc_mdio_read_mux(device_t, int, int, int); 107 108 static device_method_t brcm_iproc_mdio_fdt_methods[] = { 109 /* Device interface */ 110 DEVMETHOD(device_probe, brcm_iproc_mdio_probe), 111 DEVMETHOD(device_attach, brcm_iproc_mdio_attach), 112 DEVMETHOD(device_detach, brcm_iproc_mdio_detach), 113 114 /* Bus interface */ 115 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource), 116 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 117 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 118 119 /* ofw_bus interface */ 120 DEVMETHOD(ofw_bus_get_devinfo, brcm_iproc_mdio_get_devinfo), 121 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), 122 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), 123 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), 124 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), 125 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), 126 127 /* MDIO interface */ 128 DEVMETHOD(mdio_writereg_mux, brcm_iproc_mdio_write_mux), 129 DEVMETHOD(mdio_readreg_mux, brcm_iproc_mdio_read_mux), 130 131 /* End */ 132 DEVMETHOD_END 133 }; 134 135 DEFINE_CLASS_0(brcm_iproc_mdio, brcm_iproc_mdio_driver, 136 brcm_iproc_mdio_fdt_methods, sizeof(struct brcm_iproc_mdio_softc)); 137 138 EARLY_DRIVER_MODULE(brcm_iproc_mdio, ofwbus, brcm_iproc_mdio_driver, 0, 0, 139 BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); 140 EARLY_DRIVER_MODULE(brcm_iproc_mdio, simplebus, brcm_iproc_mdio_driver, 0, 0, 141 BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); 142 143 static struct ofw_compat_data mdio_compat_data[] = { 144 {"brcm,mdio-mux-iproc", true}, 145 {NULL, false} 146 }; 147 148 static int 149 brcm_iproc_switch(struct brcm_iproc_mdio_softc *sc, int child) 150 { 151 uint32_t param, bus_id; 152 uint32_t bus_dir; 153 154 /* select bus and its properties */ 155 bus_dir = (child < EXT_BUS_START_ADDR); 156 bus_id = bus_dir ? child : (child - EXT_BUS_START_ADDR); 157 158 param = (bus_dir ? 1 : 0) << MDIO_PARAM_INTERNAL_SEL; 159 param |= (bus_id << MDIO_PARAM_BUS_ID); 160 161 bus_write_4(sc->reg_base, MDIO_PARAM_OFFSET, param); 162 163 return (0); 164 } 165 166 static int 167 iproc_mdio_wait_for_idle(struct brcm_iproc_mdio_softc *sc, uint32_t result) 168 { 169 unsigned int timeout = 1000; /* loop for 1s */ 170 uint32_t val; 171 172 do { 173 val = bus_read_4(sc->reg_base, MDIO_STAT_OFFSET); 174 if ((val & MDIO_STAT_DONE) == result) 175 return (0); 176 177 pause("BRCM MDIO SLEEP", 1000 / hz); 178 } while (timeout--); 179 180 return (ETIMEDOUT); 181 } 182 183 /* start_miim_ops- Program and start MDIO transaction over mdio bus. 184 * @base: Base address 185 * @phyid: phyid of the selected bus. 186 * @reg: register offset to be read/written. 187 * @val :0 if read op else value to be written in @reg; 188 * @op: Operation that need to be carried out. 189 * MDIO_CTRL_READ_OP: Read transaction. 190 * MDIO_CTRL_WRITE_OP: Write transaction. 191 * 192 * Return value: Successful Read operation returns read reg values and write 193 * operation returns 0. Failure operation returns negative error code. 194 */ 195 static int 196 brcm_iproc_mdio_op(struct brcm_iproc_mdio_softc *sc, 197 uint16_t phyid, uint32_t reg, uint32_t val, uint32_t op) 198 { 199 uint32_t param; 200 int ret; 201 202 bus_write_4(sc->reg_base, MDIO_CTRL_OFFSET, 0); 203 bus_read_4(sc->reg_base, MDIO_STAT_OFFSET); 204 ret = iproc_mdio_wait_for_idle(sc, 0); 205 if (ret) 206 goto err; 207 208 param = bus_read_4(sc->reg_base, MDIO_PARAM_OFFSET); 209 param |= phyid << MDIO_PARAM_PHY_ID; 210 param |= val << MDIO_PARAM_PHY_DATA; 211 if (reg & MII_ADDR_C45) 212 param |= (1 << MDIO_PARAM_C45_SEL); 213 214 bus_write_4(sc->reg_base, MDIO_PARAM_OFFSET, param); 215 216 bus_write_4(sc->reg_base, MDIO_ADDR_OFFSET, reg); 217 218 bus_write_4(sc->reg_base, MDIO_CTRL_OFFSET, op); 219 220 ret = iproc_mdio_wait_for_idle(sc, 1); 221 if (ret) 222 goto err; 223 224 if (op == MDIO_CTRL_READ_OP) 225 ret = bus_read_4(sc->reg_base, MDIO_READ_OFFSET) & MDIO_READ_DATA_MASK; 226 err: 227 return ret; 228 } 229 230 static int 231 brcm_iproc_config(struct brcm_iproc_mdio_softc *sc) 232 { 233 uint32_t divisor; 234 uint32_t val; 235 236 /* Disable external mdio master access */ 237 val = bus_read_4(sc->reg_base, MDIO_SCAN_CTRL_OFFSET); 238 val |= 1 << MDIO_SCAN_CTRL_OVRIDE_EXT_MSTR; 239 bus_write_4(sc->reg_base, MDIO_SCAN_CTRL_OFFSET, val); 240 241 if (sc->clock_rate) { 242 /* use rate adjust regs to derrive the mdio's operating 243 * frequency from the specified core clock 244 */ 245 divisor = sc->clock_rate / MDIO_OPERATING_FREQUENCY; 246 divisor = divisor / (MDIO_RATE_ADJ_DIVIDENT + 1); 247 val = divisor; 248 val |= MDIO_RATE_ADJ_DIVIDENT << MDIO_RATE_ADJ_DIVIDENT_SHIFT; 249 bus_write_4(sc->reg_base, MDIO_RATE_ADJ_EXT_OFFSET, val); 250 bus_write_4(sc->reg_base, MDIO_RATE_ADJ_INT_OFFSET, val); 251 } 252 253 return (0); 254 } 255 256 static int 257 brcm_iproc_mdio_write_mux(device_t dev, int bus, int phy, int reg, int val) 258 { 259 struct brcm_iproc_mdio_softc *sc; 260 261 sc = device_get_softc(dev); 262 263 if (brcm_iproc_switch(sc, bus) != 0) { 264 device_printf(dev, "Failed to set BUS MUX\n"); 265 return (EINVAL); 266 } 267 268 return (brcm_iproc_mdio_op(sc, phy, reg, val, MDIO_CTRL_WRITE_OP)); 269 } 270 271 static int 272 brcm_iproc_mdio_read_mux(device_t dev, int bus, int phy, int reg) 273 { 274 struct brcm_iproc_mdio_softc *sc; 275 276 sc = device_get_softc(dev); 277 278 if (brcm_iproc_switch(sc, bus) != 0) { 279 device_printf(dev, "Failed to set BUS MUX\n"); 280 return (EINVAL); 281 } 282 283 return (brcm_iproc_mdio_op(sc, phy, reg, 0, MDIO_CTRL_READ_OP)); 284 } 285 286 static int 287 brcm_iproc_mdio_probe(device_t dev) 288 { 289 290 if (!ofw_bus_status_okay(dev)) 291 return (ENXIO); 292 if (!ofw_bus_search_compatible(dev, mdio_compat_data)->ocd_data) 293 return (ENXIO); 294 295 device_set_desc(dev, "Broadcom MDIO MUX driver"); 296 return (BUS_PROBE_DEFAULT); 297 } 298 299 static int 300 brcm_iproc_mdio_attach(device_t dev) 301 { 302 struct brcm_iproc_mdio_softc *sc; 303 phandle_t node, parent; 304 struct brcm_mdio_ofw_devinfo *di; 305 int rid; 306 device_t child; 307 308 sc = device_get_softc(dev); 309 sc->dev = dev; 310 311 /* Allocate memory resources */ 312 rid = REG_BASE_RID; 313 sc->reg_base = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 314 RF_ACTIVE); 315 if (sc->reg_base == NULL) { 316 device_printf(dev, "Could not allocate memory\n"); 317 return (ENXIO); 318 } 319 320 /* Configure MDIO controlled */ 321 if (brcm_iproc_config(sc) < 0) { 322 device_printf(dev, "Unable to initialize IPROC MDIO\n"); 323 goto error; 324 } 325 326 parent = ofw_bus_get_node(dev); 327 simplebus_init(dev, parent); 328 329 /* Iterate through all bus subordinates */ 330 for (node = OF_child(parent); node > 0; node = OF_peer(node)) { 331 /* Allocate and populate devinfo. */ 332 di = malloc(sizeof(*di), M_BRCM_IPROC_MDIO, M_WAITOK | M_ZERO); 333 if (ofw_bus_gen_setup_devinfo(&di->di_dinfo, node) != 0) { 334 free(di, M_BRCM_IPROC_MDIO); 335 continue; 336 } 337 338 /* Initialize and populate resource list. */ 339 resource_list_init(&di->di_rl); 340 ofw_bus_reg_to_rl(dev, node, sc->sbus.acells, sc->sbus.scells, 341 &di->di_rl); 342 ofw_bus_intr_to_rl(dev, node, &di->di_rl, NULL); 343 344 /* Add newbus device for this FDT node */ 345 child = device_add_child(dev, NULL, -1); 346 if (child == NULL) { 347 printf("Failed to add child\n"); 348 resource_list_free(&di->di_rl); 349 ofw_bus_gen_destroy_devinfo(&di->di_dinfo); 350 free(di, M_BRCM_IPROC_MDIO); 351 continue; 352 } 353 354 device_set_ivars(child, di); 355 } 356 357 /* 358 * Register device to this node/xref. 359 * Thanks to that we will be able to retrieve device_t structure 360 * while holding only node reference acquired from FDT. 361 */ 362 node = ofw_bus_get_node(dev); 363 OF_device_register_xref(OF_xref_from_node(node), dev); 364 365 return (bus_generic_attach(dev)); 366 367 error: 368 brcm_iproc_mdio_detach(dev); 369 return (ENXIO); 370 } 371 372 static const struct ofw_bus_devinfo * 373 brcm_iproc_mdio_get_devinfo(device_t bus __unused, device_t child) 374 { 375 struct brcm_mdio_ofw_devinfo *di; 376 377 di = device_get_ivars(child); 378 return (&di->di_dinfo); 379 } 380 381 static int 382 brcm_iproc_mdio_detach(device_t dev) 383 { 384 struct brcm_iproc_mdio_softc *sc; 385 386 sc = device_get_softc(dev); 387 388 if (sc->reg_base != NULL) { 389 bus_release_resource(dev, SYS_RES_MEMORY, REG_BASE_RID, 390 sc->reg_base); 391 } 392 393 return (0); 394 } 395