1 /*- 2 * Copyright (c) 2019 Juniper Networks, Inc. 3 * Copyright (c) 2019 Semihalf. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 #include <sys/param.h> 30 #include <sys/bus.h> 31 #include <sys/kernel.h> 32 #include <sys/module.h> 33 #include <sys/rman.h> 34 #include <sys/systm.h> 35 36 #include <dev/fdt/simplebus.h> 37 #include <dev/ofw/ofw_bus_subr.h> 38 #include <dev/ofw/ofw_bus.h> 39 40 #include <machine/bus.h> 41 #include <machine/resource.h> 42 43 #include "mdio_if.h" 44 45 #define REG_BASE_RID 0 46 47 #define MDIO_RATE_ADJ_EXT_OFFSET 0x000 48 #define MDIO_RATE_ADJ_INT_OFFSET 0x004 49 #define MDIO_RATE_ADJ_DIVIDENT_SHIFT 16 50 51 #define MDIO_SCAN_CTRL_OFFSET 0x008 52 #define MDIO_SCAN_CTRL_OVRIDE_EXT_MSTR 28 53 54 #define MDIO_PARAM_OFFSET 0x23c 55 #define MDIO_PARAM_MIIM_CYCLE 29 56 #define MDIO_PARAM_INTERNAL_SEL 25 57 #define MDIO_PARAM_BUS_ID 22 58 #define MDIO_PARAM_C45_SEL 21 59 #define MDIO_PARAM_PHY_ID 16 60 #define MDIO_PARAM_PHY_DATA 0 61 62 #define MDIO_READ_OFFSET 0x240 63 #define MDIO_READ_DATA_MASK 0xffff 64 #define MDIO_ADDR_OFFSET 0x244 65 66 #define MDIO_CTRL_OFFSET 0x248 67 #define MDIO_CTRL_WRITE_OP 0x1 68 #define MDIO_CTRL_READ_OP 0x2 69 70 #define MDIO_STAT_OFFSET 0x24c 71 #define MDIO_STAT_DONE 1 72 73 #define BUS_MAX_ADDR 32 74 #define EXT_BUS_START_ADDR 16 75 76 #define MDIO_REG_ADDR_SPACE_SIZE 0x250 77 78 #define MDIO_OPERATING_FREQUENCY 11000000 79 #define MDIO_RATE_ADJ_DIVIDENT 1 80 81 #define MII_ADDR_C45 (1<<30) 82 83 static int brcm_iproc_mdio_probe(device_t); 84 static int brcm_iproc_mdio_attach(device_t); 85 static int brcm_iproc_mdio_detach(device_t); 86 87 /* OFW bus interface */ 88 struct brcm_mdio_ofw_devinfo { 89 struct ofw_bus_devinfo di_dinfo; 90 struct resource_list di_rl; 91 }; 92 93 struct brcm_iproc_mdio_softc { 94 struct simplebus_softc sbus; 95 device_t dev; 96 struct resource * reg_base; 97 uint32_t clock_rate; 98 }; 99 100 MALLOC_DEFINE(M_BRCM_IPROC_MDIO, "Broadcom IPROC MDIO", 101 "Broadcom IPROC MDIO dynamic memory"); 102 103 static int brcm_iproc_config(struct brcm_iproc_mdio_softc*); 104 static const struct ofw_bus_devinfo * 105 brcm_iproc_mdio_get_devinfo(device_t, device_t); 106 static int brcm_iproc_mdio_write_mux(device_t, int, int, int, int); 107 static int brcm_iproc_mdio_read_mux(device_t, int, int, int); 108 109 static device_method_t brcm_iproc_mdio_fdt_methods[] = { 110 /* Device interface */ 111 DEVMETHOD(device_probe, brcm_iproc_mdio_probe), 112 DEVMETHOD(device_attach, brcm_iproc_mdio_attach), 113 DEVMETHOD(device_detach, brcm_iproc_mdio_detach), 114 115 /* Bus interface */ 116 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource), 117 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 118 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 119 120 /* ofw_bus interface */ 121 DEVMETHOD(ofw_bus_get_devinfo, brcm_iproc_mdio_get_devinfo), 122 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), 123 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), 124 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), 125 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), 126 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), 127 128 /* MDIO interface */ 129 DEVMETHOD(mdio_writereg_mux, brcm_iproc_mdio_write_mux), 130 DEVMETHOD(mdio_readreg_mux, brcm_iproc_mdio_read_mux), 131 132 /* End */ 133 DEVMETHOD_END 134 }; 135 136 DEFINE_CLASS_0(brcm_iproc_mdio, brcm_iproc_mdio_driver, 137 brcm_iproc_mdio_fdt_methods, sizeof(struct brcm_iproc_mdio_softc)); 138 139 EARLY_DRIVER_MODULE(brcm_iproc_mdio, ofwbus, brcm_iproc_mdio_driver, 0, 0, 140 BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); 141 EARLY_DRIVER_MODULE(brcm_iproc_mdio, simplebus, brcm_iproc_mdio_driver, 0, 0, 142 BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); 143 144 static struct ofw_compat_data mdio_compat_data[] = { 145 {"brcm,mdio-mux-iproc", true}, 146 {NULL, false} 147 }; 148 149 static int 150 brcm_iproc_switch(struct brcm_iproc_mdio_softc *sc, int child) 151 { 152 uint32_t param, bus_id; 153 uint32_t bus_dir; 154 155 /* select bus and its properties */ 156 bus_dir = (child < EXT_BUS_START_ADDR); 157 bus_id = bus_dir ? child : (child - EXT_BUS_START_ADDR); 158 159 param = (bus_dir ? 1 : 0) << MDIO_PARAM_INTERNAL_SEL; 160 param |= (bus_id << MDIO_PARAM_BUS_ID); 161 162 bus_write_4(sc->reg_base, MDIO_PARAM_OFFSET, param); 163 164 return (0); 165 } 166 167 static int 168 iproc_mdio_wait_for_idle(struct brcm_iproc_mdio_softc *sc, uint32_t result) 169 { 170 unsigned int timeout = 1000; /* loop for 1s */ 171 uint32_t val; 172 173 do { 174 val = bus_read_4(sc->reg_base, MDIO_STAT_OFFSET); 175 if ((val & MDIO_STAT_DONE) == result) 176 return (0); 177 178 pause("BRCM MDIO SLEEP", 1000 / hz); 179 } while (timeout--); 180 181 return (ETIMEDOUT); 182 } 183 184 /* start_miim_ops- Program and start MDIO transaction over mdio bus. 185 * @base: Base address 186 * @phyid: phyid of the selected bus. 187 * @reg: register offset to be read/written. 188 * @val :0 if read op else value to be written in @reg; 189 * @op: Operation that need to be carried out. 190 * MDIO_CTRL_READ_OP: Read transaction. 191 * MDIO_CTRL_WRITE_OP: Write transaction. 192 * 193 * Return value: Successful Read operation returns read reg values and write 194 * operation returns 0. Failure operation returns negative error code. 195 */ 196 static int 197 brcm_iproc_mdio_op(struct brcm_iproc_mdio_softc *sc, 198 uint16_t phyid, uint32_t reg, uint32_t val, uint32_t op) 199 { 200 uint32_t param; 201 int ret; 202 203 bus_write_4(sc->reg_base, MDIO_CTRL_OFFSET, 0); 204 bus_read_4(sc->reg_base, MDIO_STAT_OFFSET); 205 ret = iproc_mdio_wait_for_idle(sc, 0); 206 if (ret) 207 goto err; 208 209 param = bus_read_4(sc->reg_base, MDIO_PARAM_OFFSET); 210 param |= phyid << MDIO_PARAM_PHY_ID; 211 param |= val << MDIO_PARAM_PHY_DATA; 212 if (reg & MII_ADDR_C45) 213 param |= (1 << MDIO_PARAM_C45_SEL); 214 215 bus_write_4(sc->reg_base, MDIO_PARAM_OFFSET, param); 216 217 bus_write_4(sc->reg_base, MDIO_ADDR_OFFSET, reg); 218 219 bus_write_4(sc->reg_base, MDIO_CTRL_OFFSET, op); 220 221 ret = iproc_mdio_wait_for_idle(sc, 1); 222 if (ret) 223 goto err; 224 225 if (op == MDIO_CTRL_READ_OP) 226 ret = bus_read_4(sc->reg_base, MDIO_READ_OFFSET) & MDIO_READ_DATA_MASK; 227 err: 228 return ret; 229 } 230 231 static int 232 brcm_iproc_config(struct brcm_iproc_mdio_softc *sc) 233 { 234 uint32_t divisor; 235 uint32_t val; 236 237 /* Disable external mdio master access */ 238 val = bus_read_4(sc->reg_base, MDIO_SCAN_CTRL_OFFSET); 239 val |= 1 << MDIO_SCAN_CTRL_OVRIDE_EXT_MSTR; 240 bus_write_4(sc->reg_base, MDIO_SCAN_CTRL_OFFSET, val); 241 242 if (sc->clock_rate) { 243 /* use rate adjust regs to derrive the mdio's operating 244 * frequency from the specified core clock 245 */ 246 divisor = sc->clock_rate / MDIO_OPERATING_FREQUENCY; 247 divisor = divisor / (MDIO_RATE_ADJ_DIVIDENT + 1); 248 val = divisor; 249 val |= MDIO_RATE_ADJ_DIVIDENT << MDIO_RATE_ADJ_DIVIDENT_SHIFT; 250 bus_write_4(sc->reg_base, MDIO_RATE_ADJ_EXT_OFFSET, val); 251 bus_write_4(sc->reg_base, MDIO_RATE_ADJ_INT_OFFSET, val); 252 } 253 254 return (0); 255 } 256 257 static int 258 brcm_iproc_mdio_write_mux(device_t dev, int bus, int phy, int reg, int val) 259 { 260 struct brcm_iproc_mdio_softc *sc; 261 262 sc = device_get_softc(dev); 263 264 if (brcm_iproc_switch(sc, bus) != 0) { 265 device_printf(dev, "Failed to set BUS MUX\n"); 266 return (EINVAL); 267 } 268 269 return (brcm_iproc_mdio_op(sc, phy, reg, val, MDIO_CTRL_WRITE_OP)); 270 } 271 272 static int 273 brcm_iproc_mdio_read_mux(device_t dev, int bus, int phy, int reg) 274 { 275 struct brcm_iproc_mdio_softc *sc; 276 277 sc = device_get_softc(dev); 278 279 if (brcm_iproc_switch(sc, bus) != 0) { 280 device_printf(dev, "Failed to set BUS MUX\n"); 281 return (EINVAL); 282 } 283 284 return (brcm_iproc_mdio_op(sc, phy, reg, 0, MDIO_CTRL_READ_OP)); 285 } 286 287 static int 288 brcm_iproc_mdio_probe(device_t dev) 289 { 290 291 if (!ofw_bus_status_okay(dev)) 292 return (ENXIO); 293 if (!ofw_bus_search_compatible(dev, mdio_compat_data)->ocd_data) 294 return (ENXIO); 295 296 device_set_desc(dev, "Broadcom MDIO MUX driver"); 297 return (BUS_PROBE_DEFAULT); 298 } 299 300 static int 301 brcm_iproc_mdio_attach(device_t dev) 302 { 303 struct brcm_iproc_mdio_softc *sc; 304 phandle_t node, parent; 305 struct brcm_mdio_ofw_devinfo *di; 306 int rid; 307 device_t child; 308 309 sc = device_get_softc(dev); 310 sc->dev = dev; 311 312 /* Allocate memory resources */ 313 rid = REG_BASE_RID; 314 sc->reg_base = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 315 RF_ACTIVE); 316 if (sc->reg_base == NULL) { 317 device_printf(dev, "Could not allocate memory\n"); 318 return (ENXIO); 319 } 320 321 /* Configure MDIO controlled */ 322 if (brcm_iproc_config(sc) < 0) { 323 device_printf(dev, "Unable to initialize IPROC MDIO\n"); 324 goto error; 325 } 326 327 parent = ofw_bus_get_node(dev); 328 simplebus_init(dev, parent); 329 330 /* Iterate through all bus subordinates */ 331 for (node = OF_child(parent); node > 0; node = OF_peer(node)) { 332 /* Allocate and populate devinfo. */ 333 di = malloc(sizeof(*di), M_BRCM_IPROC_MDIO, M_WAITOK | M_ZERO); 334 if (ofw_bus_gen_setup_devinfo(&di->di_dinfo, node) != 0) { 335 free(di, M_BRCM_IPROC_MDIO); 336 continue; 337 } 338 339 /* Initialize and populate resource list. */ 340 resource_list_init(&di->di_rl); 341 ofw_bus_reg_to_rl(dev, node, sc->sbus.acells, sc->sbus.scells, 342 &di->di_rl); 343 ofw_bus_intr_to_rl(dev, node, &di->di_rl, NULL); 344 345 /* Add newbus device for this FDT node */ 346 child = device_add_child(dev, NULL, -1); 347 if (child == NULL) { 348 printf("Failed to add child\n"); 349 resource_list_free(&di->di_rl); 350 ofw_bus_gen_destroy_devinfo(&di->di_dinfo); 351 free(di, M_BRCM_IPROC_MDIO); 352 continue; 353 } 354 355 device_set_ivars(child, di); 356 } 357 358 /* 359 * Register device to this node/xref. 360 * Thanks to that we will be able to retrieve device_t structure 361 * while holding only node reference acquired from FDT. 362 */ 363 node = ofw_bus_get_node(dev); 364 OF_device_register_xref(OF_xref_from_node(node), dev); 365 366 return (bus_generic_attach(dev)); 367 368 error: 369 brcm_iproc_mdio_detach(dev); 370 return (ENXIO); 371 } 372 373 static const struct ofw_bus_devinfo * 374 brcm_iproc_mdio_get_devinfo(device_t bus __unused, device_t child) 375 { 376 struct brcm_mdio_ofw_devinfo *di; 377 378 di = device_get_ivars(child); 379 return (&di->di_dinfo); 380 } 381 382 static int 383 brcm_iproc_mdio_detach(device_t dev) 384 { 385 struct brcm_iproc_mdio_softc *sc; 386 387 sc = device_get_softc(dev); 388 389 if (sc->reg_base != NULL) { 390 bus_release_resource(dev, SYS_RES_MEMORY, REG_BASE_RID, 391 sc->reg_base); 392 } 393 394 return (0); 395 } 396