1/*- 2 * Copyright (c) 2012-2014 Andrew Turner 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29#include "assym.s" 30#include "opt_kstack_pages.h" 31#include <sys/syscall.h> 32#include <machine/asm.h> 33#include <machine/armreg.h> 34#include <machine/hypervisor.h> 35#include <machine/param.h> 36#include <machine/pte.h> 37 38#define VIRT_BITS 39 39 40 .globl kernbase 41 .set kernbase, KERNBASE 42 43#define DEVICE_MEM 0 44#define NORMAL_UNCACHED 1 45#define NORMAL_MEM 2 46 47/* 48 * We assume: 49 * MMU on with an identity map, or off 50 * D-Cache: off 51 * I-Cache: on or off 52 * We are loaded at a 2MiB aligned address 53 */ 54 55 .text 56 .globl _start 57_start: 58 /* Drop to EL1 */ 59 bl drop_to_el1 60 61 /* 62 * Disable the MMU. We may have entered the kernel with it on and 63 * will need to update the tables later. If this has been set up 64 * with anything other than a VA == PA map then this will fail, 65 * but in this case the code to find where we are running from 66 * would have also failed. 67 */ 68 dsb sy 69 mrs x2, sctlr_el1 70 bic x2, x2, SCTLR_M 71 msr sctlr_el1, x2 72 isb 73 74 /* Set the context id */ 75 msr contextidr_el1, xzr 76 77 /* Get the virt -> phys offset */ 78 bl get_virt_delta 79 80 /* 81 * At this point: 82 * x29 = PA - VA 83 * x28 = Our physical load address 84 */ 85 86 /* Create the page tables */ 87 bl create_pagetables 88 89 /* 90 * At this point: 91 * x27 = TTBR0 table 92 * x26 = TTBR1 table 93 */ 94 95 /* Enable the mmu */ 96 bl start_mmu 97 98 /* Jump to the virtual address space */ 99 ldr x15, .Lvirtdone 100 br x15 101 102virtdone: 103 /* Set up the stack */ 104 adr x25, initstack_end 105 mov sp, x25 106 sub sp, sp, #PCB_SIZE 107 108 /* Zero the BSS */ 109 ldr x15, .Lbss 110 ldr x14, .Lend 1111: 112 str xzr, [x15], #8 113 cmp x15, x14 114 b.lo 1b 115 116 /* Backup the module pointer */ 117 mov x1, x0 118 119 /* Make the page table base a virtual address */ 120 sub x26, x26, x29 121 122 sub sp, sp, #(64 * 4) 123 mov x0, sp 124 125 /* Degate the delda so it is VA -> PA */ 126 neg x29, x29 127 128 str x1, [x0] /* modulep */ 129 str x26, [x0, 8] /* kern_l1pt */ 130 str x29, [x0, 16] /* kern_delta */ 131 str x25, [x0, 24] /* kern_stack */ 132 133 /* trace back starts here */ 134 mov fp, #0 135 /* Branch to C code */ 136 bl initarm 137 bl mi_startup 138 139 /* We should not get here */ 140 brk 0 141 142 .align 3 143.Lvirtdone: 144 .quad virtdone 145.Lbss: 146 .quad __bss_start 147.Lend: 148 .quad _end 149 150#ifdef SMP 151/* 152 * mpentry(unsigned long) 153 * 154 * Called by a core when it is being brought online. 155 * The data in x0 is passed straight to init_secondary. 156 */ 157ENTRY(mpentry) 158 /* Disable interrupts */ 159 msr daifset, #2 160 161 /* Drop to EL1 */ 162 bl drop_to_el1 163 164 /* Set the context id */ 165 msr contextidr_el1, x1 166 167 /* Load the kernel page table */ 168 adr x26, pagetable_l1_ttbr1 169 /* Load the identity page table */ 170 adr x27, pagetable_l1_ttbr0 171 172 /* Enable the mmu */ 173 bl start_mmu 174 175 /* Jump to the virtual address space */ 176 ldr x15, =mp_virtdone 177 br x15 178 179mp_virtdone: 180 ldr x4, =secondary_stacks 181 mov x5, #(PAGE_SIZE * KSTACK_PAGES) 182 mul x5, x0, x5 183 add sp, x4, x5 184 185 b init_secondary 186END(mpentry) 187#endif 188 189/* 190 * If we are started in EL2, configure the required hypervisor 191 * registers and drop to EL1. 192 */ 193drop_to_el1: 194 mrs x1, CurrentEL 195 lsr x1, x1, #2 196 cmp x1, #0x2 197 b.eq 1f 198 ret 1991: 200 /* Configure the Hypervisor */ 201 mov x2, #(HCR_RW) 202 msr hcr_el2, x2 203 204 /* Load the Virtualization Process ID Register */ 205 mrs x2, midr_el1 206 msr vpidr_el2, x2 207 208 /* Load the Virtualization Multiprocess ID Register */ 209 mrs x2, mpidr_el1 210 msr vmpidr_el2, x2 211 212 /* Set the bits that need to be 1 in sctlr_el1 */ 213 ldr x2, .Lsctlr_res1 214 msr sctlr_el1, x2 215 216 /* Don't trap to EL2 for exceptions */ 217 mov x2, #CPTR_RES1 218 msr cptr_el2, x2 219 220 /* Don't trap to EL2 for CP15 traps */ 221 msr hstr_el2, xzr 222 223 /* Hypervisor trap functions */ 224 adr x2, hyp_vectors 225 msr vbar_el2, x2 226 227 mov x2, #(PSR_F | PSR_I | PSR_A | PSR_D | PSR_M_EL1h) 228 msr spsr_el2, x2 229 230 /* Configure GICv3 CPU interface */ 231 mrs x2, id_aa64pfr0_el1 232 /* Extract GIC bits from the register */ 233 ubfx x2, x2, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_BITS 234 /* GIC[3:0] == 0001 - GIC CPU interface via special regs. supported */ 235 cmp x2, #(ID_AA64PFR0_GIC_CPUIF_EN >> ID_AA64PFR0_GIC_SHIFT) 236 b.ne 2f 237 238 mrs x2, icc_sre_el2 239 orr x2, x2, #ICC_SRE_EL2_EN /* Enable access from insecure EL1 */ 240 msr icc_sre_el2, x2 241 isb 2422: 243 244 /* Set the address to return to our return address */ 245 msr elr_el2, x30 246 247 eret 248 249 .align 3 250.Lsctlr_res1: 251 .quad SCTLR_RES1 252 253#define VECT_EMPTY \ 254 .align 7; \ 255 1: b 1b 256 257 .align 11 258hyp_vectors: 259 VECT_EMPTY /* Synchronous EL2t */ 260 VECT_EMPTY /* IRQ EL2t */ 261 VECT_EMPTY /* FIQ EL2t */ 262 VECT_EMPTY /* Error EL2t */ 263 264 VECT_EMPTY /* Synchronous EL2h */ 265 VECT_EMPTY /* IRQ EL2h */ 266 VECT_EMPTY /* FIQ EL2h */ 267 VECT_EMPTY /* Error EL2h */ 268 269 VECT_EMPTY /* Synchronous 64-bit EL1 */ 270 VECT_EMPTY /* IRQ 64-bit EL1 */ 271 VECT_EMPTY /* FIQ 64-bit EL1 */ 272 VECT_EMPTY /* Error 64-bit EL1 */ 273 274 VECT_EMPTY /* Synchronous 32-bit EL1 */ 275 VECT_EMPTY /* IRQ 32-bit EL1 */ 276 VECT_EMPTY /* FIQ 32-bit EL1 */ 277 VECT_EMPTY /* Error 32-bit EL1 */ 278 279/* 280 * Get the delta between the physical address we were loaded to and the 281 * virtual address we expect to run from. This is used when building the 282 * initial page table. 283 */ 284get_virt_delta: 285 /* Load the physical address of virt_map */ 286 adr x29, virt_map 287 /* Load the virtual address of virt_map stored in virt_map */ 288 ldr x28, [x29] 289 /* Find PA - VA as PA' = VA' - VA + PA = VA' + (PA - VA) = VA' + x29 */ 290 sub x29, x29, x28 291 /* Find the load address for the kernel */ 292 mov x28, #(KERNBASE) 293 add x28, x28, x29 294 ret 295 296 .align 3 297virt_map: 298 .quad virt_map 299 300/* 301 * This builds the page tables containing the identity map, and the kernel 302 * virtual map. 303 * 304 * It relys on: 305 * We were loaded to an address that is on a 2MiB boundary 306 * All the memory must not cross a 1GiB boundaty 307 * x28 contains the physical address we were loaded from 308 * 309 * TODO: This is out of date. 310 * There are at least 5 pages before that address for the page tables 311 * The pages used are: 312 * - The identity (PA = VA) table (TTBR0) 313 * - The Kernel L1 table (TTBR1)(not yet) 314 * - The PA != VA L2 table to jump into (not yet) 315 * - The FDT L2 table (not yet) 316 */ 317create_pagetables: 318 /* Save the Link register */ 319 mov x5, x30 320 321 /* Clean the page table */ 322 adr x6, pagetable 323 mov x26, x6 324 adr x27, pagetable_end 3251: 326 stp xzr, xzr, [x6], #16 327 stp xzr, xzr, [x6], #16 328 stp xzr, xzr, [x6], #16 329 stp xzr, xzr, [x6], #16 330 cmp x6, x27 331 b.lo 1b 332 333 /* 334 * Build the TTBR1 maps. 335 */ 336 337 /* Find the size of the kernel */ 338 mov x6, #(KERNBASE) 339 ldr x7, .Lend 340 /* Find the end - begin */ 341 sub x8, x7, x6 342 /* Get the number of l2 pages to allocate, rounded down */ 343 lsr x10, x8, #(L2_SHIFT) 344 /* Add 4 MiB for any rounding above and the module data */ 345 add x10, x10, #2 346 347 /* Create the kernel space L2 table */ 348 mov x6, x26 349 mov x7, #NORMAL_MEM 350 mov x8, #(KERNBASE & L2_BLOCK_MASK) 351 mov x9, x28 352 bl build_block_pagetable 353 354 /* Move to the l1 table */ 355 add x26, x26, #PAGE_SIZE 356 357 /* Link the l1 -> l2 table */ 358 mov x9, x6 359 mov x6, x26 360 bl link_l1_pagetable 361 362 363 /* 364 * Build the TTBR0 maps. 365 */ 366 add x27, x26, #PAGE_SIZE 367 368#if defined(SOCDEV_PA) && defined(SOCDEV_VA) 369 /* Create a table for the UART */ 370 mov x6, x27 /* The initial page table */ 371 mov x7, #DEVICE_MEM 372 mov x8, #(SOCDEV_VA) /* VA start */ 373 mov x9, #(SOCDEV_PA) /* PA start */ 374 bl build_section_pagetable 375#endif 376 377 /* Create the VA = PA map */ 378 mov x6, x27 /* The initial page table */ 379 mov x7, #NORMAL_UNCACHED /* Uncached as it's only needed early on */ 380 mov x9, x27 381 mov x8, x9 /* VA start (== PA start) */ 382 bl build_section_pagetable 383 384 /* Restore the Link register */ 385 mov x30, x5 386 ret 387 388/* 389 * Builds a 1 GiB page table entry 390 * x6 = L1 table 391 * x7 = Type (0 = Device, 1 = Normal) 392 * x8 = VA start 393 * x9 = PA start (trashed) 394 * x11, x12 and x13 are trashed 395 */ 396build_section_pagetable: 397 /* 398 * Build the L1 table entry. 399 */ 400 /* Find the table index */ 401 lsr x11, x8, #L1_SHIFT 402 and x11, x11, #Ln_ADDR_MASK 403 404 /* Build the L1 block entry */ 405 lsl x12, x7, #2 406 orr x12, x12, #L1_BLOCK 407 orr x12, x12, #(ATTR_AF) 408 409 /* Only use the output address bits */ 410 lsr x9, x9, #L1_SHIFT 411 orr x12, x12, x9, lsl #L1_SHIFT 412 413 /* Store the entry */ 414 str x12, [x6, x11, lsl #3] 415 416 ret 417 418/* 419 * Builds an L1 -> L2 table descriptor 420 * 421 * This is a link for a 1GiB block of memory with up to 2MiB regions mapped 422 * within it by build_block_pagetable. 423 * 424 * x6 = L1 table 425 * x8 = Virtual Address 426 * x9 = L2 PA (trashed) 427 * x11, x12 and x13 are trashed 428 */ 429link_l1_pagetable: 430 /* 431 * Link an L1 -> L2 table entry. 432 */ 433 /* Find the table index */ 434 lsr x11, x8, #L1_SHIFT 435 and x11, x11, #Ln_ADDR_MASK 436 437 /* Build the L1 block entry */ 438 mov x12, #L1_TABLE 439 440 /* Only use the output address bits */ 441 lsr x9, x9, #12 442 orr x12, x12, x9, lsl #12 443 444 /* Store the entry */ 445 str x12, [x6, x11, lsl #3] 446 447 ret 448 449/* 450 * Builds count 2 MiB page table entry 451 * x6 = L2 table 452 * x7 = Type (0 = Device, 1 = Normal) 453 * x8 = VA start 454 * x9 = PA start (trashed) 455 * x10 = Entry count (TODO) 456 * x11, x12 and x13 are trashed 457 */ 458build_block_pagetable: 459 /* 460 * Build the L2 table entry. 461 */ 462 /* Find the table index */ 463 lsr x11, x8, #L2_SHIFT 464 and x11, x11, #Ln_ADDR_MASK 465 466 /* Build the L2 block entry */ 467 lsl x12, x7, #2 468 orr x12, x12, #L2_BLOCK 469 orr x12, x12, #(ATTR_AF) 470#ifdef SMP 471 orr x12, x12, ATTR_SH(ATTR_SH_IS) 472#endif 473 474 /* Only use the output address bits */ 475 lsr x9, x9, #L2_SHIFT 476 477 /* Set the physical address for this virtual address */ 4781: orr x12, x12, x9, lsl #L2_SHIFT 479 480 /* Store the entry */ 481 str x12, [x6, x11, lsl #3] 482 483 /* Clear the address bits */ 484 and x12, x12, #ATTR_MASK_L 485 486 sub x10, x10, #1 487 add x11, x11, #1 488 add x9, x9, #1 489 cbnz x10, 1b 490 4912: ret 492 493start_mmu: 494 dsb sy 495 496 /* Load the exception vectors */ 497 ldr x2, =exception_vectors 498 msr vbar_el1, x2 499 500 /* Load ttbr0 and ttbr1 */ 501 msr ttbr0_el1, x27 502 msr ttbr1_el1, x26 503 isb 504 505 /* Clear the Monitor Debug System control register */ 506 msr mdscr_el1, xzr 507 508 /* Invalidate the TLB */ 509 tlbi vmalle1is 510 511 ldr x2, mair 512 msr mair_el1, x2 513 514 /* Setup TCR according to PARange bits from ID_AA64MMFR0_EL1 */ 515 ldr x2, tcr 516 mrs x3, id_aa64mmfr0_el1 517 bfi x2, x3, #32, #3 518 msr tcr_el1, x2 519 520 /* Setup SCTLR */ 521 ldr x2, sctlr_set 522 ldr x3, sctlr_clear 523 mrs x1, sctlr_el1 524 bic x1, x1, x3 /* Clear the required bits */ 525 orr x1, x1, x2 /* Set the required bits */ 526 msr sctlr_el1, x1 527 isb 528 529 ret 530 531 .align 3 532mair: 533 /* Device Normal, no cache Normal, write-back */ 534 .quad MAIR_ATTR(0x00, 0) | MAIR_ATTR(0x44, 1) | MAIR_ATTR(0xff, 2) 535tcr: 536 .quad (TCR_TxSZ(64 - VIRT_BITS) | TCR_ASID_16 | TCR_TG1_4K | \ 537 TCR_CACHE_ATTRS | TCR_SMP_ATTRS) 538sctlr_set: 539 /* Bits to set */ 540 .quad (SCTLR_UCI | SCTLR_nTWE | SCTLR_nTWI | SCTLR_UCT | SCTLR_DZE | \ 541 SCTLR_I | SCTLR_SED | SCTLR_C | SCTLR_M) 542sctlr_clear: 543 /* Bits to clear */ 544 .quad (SCTLR_EE | SCTLR_EOE | SCTLR_WXN | SCTLR_UMA | SCTLR_ITD | \ 545 SCTLR_THEE | SCTLR_CP15BEN | SCTLR_SA0 | SCTLR_SA | SCTLR_A) 546 547 .globl abort 548abort: 549 b abort 550 551 //.section .init_pagetable 552 .align 12 /* 4KiB aligned */ 553 /* 554 * 3 initial tables (in the following order): 555 * L2 for kernel (High addresses) 556 * L1 for kernel 557 * L1 for user (Low addresses) 558 */ 559pagetable: 560 .space PAGE_SIZE 561pagetable_l1_ttbr1: 562 .space PAGE_SIZE 563pagetable_l1_ttbr0: 564 .space PAGE_SIZE 565pagetable_end: 566 567el2_pagetable: 568 .space PAGE_SIZE 569 570 .globl init_pt_va 571init_pt_va: 572 .quad pagetable /* XXX: Keep page tables VA */ 573 574 .align 4 575initstack: 576 .space (PAGE_SIZE * KSTACK_PAGES) 577initstack_end: 578 579 580ENTRY(sigcode) 581 mov x0, sp 582 add x0, x0, #SF_UC 583 5841: 585 mov x8, #SYS_sigreturn 586 svc 0 587 588 /* sigreturn failed, exit */ 589 mov x8, #SYS_exit 590 svc 0 591 592 b 1b 593END(sigcode) 594 /* This may be copied to the stack, keep it 16-byte aligned */ 595 .align 3 596esigcode: 597 598 .data 599 .align 3 600 .global szsigcode 601szsigcode: 602 .quad esigcode - sigcode 603