1/*- 2 * Copyright (c) 2012-2014 Andrew Turner 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29#include "assym.inc" 30#include "opt_kstack_pages.h" 31#include <sys/syscall.h> 32#include <machine/asm.h> 33#include <machine/armreg.h> 34#include <machine/hypervisor.h> 35#include <machine/param.h> 36#include <machine/pte.h> 37#include <machine/vm.h> 38#include <machine/vmparam.h> 39 40#define VIRT_BITS 48 41#define DMAP_TABLES ((DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS) >> L0_SHIFT) 42 43 .globl kernbase 44 .set kernbase, KERNBASE 45 46/* 47 * We assume: 48 * MMU on with an identity map, or off 49 * D-Cache: off 50 * I-Cache: on or off 51 * We are loaded at a 2MiB aligned address 52 */ 53 54ENTRY(_start) 55 /* Drop to EL1 */ 56 bl drop_to_el1 57 58 /* 59 * Disable the MMU. We may have entered the kernel with it on and 60 * will need to update the tables later. If this has been set up 61 * with anything other than a VA == PA map then this will fail, 62 * but in this case the code to find where we are running from 63 * would have also failed. 64 */ 65 dsb sy 66 mrs x2, sctlr_el1 67 bic x2, x2, SCTLR_M 68 msr sctlr_el1, x2 69 isb 70 71 /* Set the context id */ 72 msr contextidr_el1, xzr 73 74 /* Get the virt -> phys offset */ 75 bl get_virt_delta 76 77 /* 78 * At this point: 79 * x29 = PA - VA 80 * x28 = Our physical load address 81 */ 82 83 /* Create the page tables */ 84 bl create_pagetables 85 86 /* 87 * At this point: 88 * x27 = TTBR0 table 89 * x26 = Kernel L1 table 90 * x24 = TTBR1 table 91 */ 92 93 /* Enable the mmu */ 94 bl start_mmu 95 96 /* Load the new ttbr0 pagetable */ 97 adrp x27, pagetable_l0_ttbr0 98 add x27, x27, :lo12:pagetable_l0_ttbr0 99 100 /* Jump to the virtual address space */ 101 ldr x15, .Lvirtdone 102 br x15 103 104virtdone: 105 /* Set up the stack */ 106 adrp x25, initstack_end 107 add x25, x25, :lo12:initstack_end 108 mov sp, x25 109 sub sp, sp, #PCB_SIZE 110 111 /* Zero the BSS */ 112 ldr x15, .Lbss 113 ldr x14, .Lend 1141: 115 str xzr, [x15], #8 116 cmp x15, x14 117 b.lo 1b 118 119#if defined(PERTHREAD_SSP) 120 /* Set sp_el0 to the boot canary for early per-thread SSP to work */ 121 adrp x15, boot_canary 122 add x15, x15, :lo12:boot_canary 123 msr sp_el0, x15 124#endif 125 126 /* Backup the module pointer */ 127 mov x1, x0 128 129 /* Make the page table base a virtual address */ 130 sub x26, x26, x29 131 sub x24, x24, x29 132 133 sub sp, sp, #BOOTPARAMS_SIZE 134 mov x0, sp 135 136 /* Degate the delda so it is VA -> PA */ 137 neg x29, x29 138 139 str x1, [x0, #BP_MODULEP] 140 str x26, [x0, #BP_KERN_L1PT] 141 str x29, [x0, #BP_KERN_DELTA] 142 adrp x25, initstack 143 add x25, x25, :lo12:initstack 144 str x25, [x0, #BP_KERN_STACK] 145 str x24, [x0, #BP_KERN_L0PT] 146 str x27, [x0, #BP_KERN_TTBR0] 147 str x23, [x0, #BP_BOOT_EL] 148 149 /* trace back starts here */ 150 mov fp, #0 151 /* Branch to C code */ 152 bl initarm 153 /* We are done with the boot params */ 154 add sp, sp, #BOOTPARAMS_SIZE 155 156 /* 157 * Enable pointer authentication in the kernel. We set the keys for 158 * thread0 in initarm so have to wait until it returns to enable it. 159 * If we were to enable it in initarm then any authentication when 160 * returning would fail as it was called with pointer authentication 161 * disabled. 162 */ 163 bl ptrauth_start 164 165 bl mi_startup 166 167 /* We should not get here */ 168 brk 0 169 170 .align 3 171.Lvirtdone: 172 .quad virtdone 173.Lbss: 174 .quad __bss_start 175.Lend: 176 .quad __bss_end 177END(_start) 178 179#ifdef SMP 180/* 181 * mpentry(unsigned long) 182 * 183 * Called by a core when it is being brought online. 184 * The data in x0 is passed straight to init_secondary. 185 */ 186ENTRY(mpentry) 187 /* Disable interrupts */ 188 msr daifset, #DAIF_INTR 189 190 /* Drop to EL1 */ 191 bl drop_to_el1 192 193 /* Set the context id */ 194 msr contextidr_el1, xzr 195 196 /* Load the kernel page table */ 197 adrp x24, pagetable_l0_ttbr1 198 add x24, x24, :lo12:pagetable_l0_ttbr1 199 /* Load the identity page table */ 200 adrp x27, pagetable_l0_ttbr0_boostrap 201 add x27, x27, :lo12:pagetable_l0_ttbr0_boostrap 202 203 /* Enable the mmu */ 204 bl start_mmu 205 206 /* Load the new ttbr0 pagetable */ 207 adrp x27, pagetable_l0_ttbr0 208 add x27, x27, :lo12:pagetable_l0_ttbr0 209 210 /* Jump to the virtual address space */ 211 ldr x15, =mp_virtdone 212 br x15 213 214mp_virtdone: 215 /* Start using the AP boot stack */ 216 ldr x4, =bootstack 217 ldr x4, [x4] 218 mov sp, x4 219 220#if defined(PERTHREAD_SSP) 221 /* Set sp_el0 to the boot canary for early per-thread SSP to work */ 222 adrp x15, boot_canary 223 add x15, x15, :lo12:boot_canary 224 msr sp_el0, x15 225#endif 226 227 /* Load the kernel ttbr0 pagetable */ 228 msr ttbr0_el1, x27 229 isb 230 231 /* Invalidate the TLB */ 232 tlbi vmalle1 233 dsb sy 234 isb 235 236 b init_secondary 237END(mpentry) 238#endif 239 240/* 241 * If we are started in EL2, configure the required hypervisor 242 * registers and drop to EL1. 243 */ 244LENTRY(drop_to_el1) 245 mrs x23, CurrentEL 246 lsr x23, x23, #2 247 cmp x23, #0x2 248 b.eq 1f 249 ret 2501: 251 /* Configure the Hypervisor */ 252 ldr x2, =(HCR_RW | HCR_APK | HCR_API) 253 msr hcr_el2, x2 254 255 /* Load the Virtualization Process ID Register */ 256 mrs x2, midr_el1 257 msr vpidr_el2, x2 258 259 /* Load the Virtualization Multiprocess ID Register */ 260 mrs x2, mpidr_el1 261 msr vmpidr_el2, x2 262 263 /* Set the bits that need to be 1 in sctlr_el1 */ 264 ldr x2, .Lsctlr_res1 265 msr sctlr_el1, x2 266 267 /* Don't trap to EL2 for exceptions */ 268 mov x2, #CPTR_RES1 269 msr cptr_el2, x2 270 271 /* Don't trap to EL2 for CP15 traps */ 272 msr hstr_el2, xzr 273 274 /* Enable access to the physical timers at EL1 */ 275 mrs x2, cnthctl_el2 276 orr x2, x2, #(CNTHCTL_EL1PCTEN | CNTHCTL_EL1PCEN) 277 msr cnthctl_el2, x2 278 279 /* Set the counter offset to a known value */ 280 msr cntvoff_el2, xzr 281 282 /* Hypervisor trap functions */ 283 adrp x2, hyp_vectors 284 add x2, x2, :lo12:hyp_vectors 285 msr vbar_el2, x2 286 287 mov x2, #(PSR_F | PSR_I | PSR_A | PSR_D | PSR_M_EL1h) 288 msr spsr_el2, x2 289 290 /* Configure GICv3 CPU interface */ 291 mrs x2, id_aa64pfr0_el1 292 /* Extract GIC bits from the register */ 293 ubfx x2, x2, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_BITS 294 /* GIC[3:0] == 0001 - GIC CPU interface via special regs. supported */ 295 cmp x2, #(ID_AA64PFR0_GIC_CPUIF_EN >> ID_AA64PFR0_GIC_SHIFT) 296 b.ne 2f 297 298 mrs x2, icc_sre_el2 299 orr x2, x2, #ICC_SRE_EL2_EN /* Enable access from insecure EL1 */ 300 orr x2, x2, #ICC_SRE_EL2_SRE /* Enable system registers */ 301 msr icc_sre_el2, x2 3022: 303 304 /* Set the address to return to our return address */ 305 msr elr_el2, x30 306 isb 307 308 eret 309 310 .align 3 311.Lsctlr_res1: 312 .quad SCTLR_RES1 313LEND(drop_to_el1) 314 315#define VECT_EMPTY \ 316 .align 7; \ 317 1: b 1b 318 319 .align 11 320hyp_vectors: 321 VECT_EMPTY /* Synchronous EL2t */ 322 VECT_EMPTY /* IRQ EL2t */ 323 VECT_EMPTY /* FIQ EL2t */ 324 VECT_EMPTY /* Error EL2t */ 325 326 VECT_EMPTY /* Synchronous EL2h */ 327 VECT_EMPTY /* IRQ EL2h */ 328 VECT_EMPTY /* FIQ EL2h */ 329 VECT_EMPTY /* Error EL2h */ 330 331 VECT_EMPTY /* Synchronous 64-bit EL1 */ 332 VECT_EMPTY /* IRQ 64-bit EL1 */ 333 VECT_EMPTY /* FIQ 64-bit EL1 */ 334 VECT_EMPTY /* Error 64-bit EL1 */ 335 336 VECT_EMPTY /* Synchronous 32-bit EL1 */ 337 VECT_EMPTY /* IRQ 32-bit EL1 */ 338 VECT_EMPTY /* FIQ 32-bit EL1 */ 339 VECT_EMPTY /* Error 32-bit EL1 */ 340 341/* 342 * Get the delta between the physical address we were loaded to and the 343 * virtual address we expect to run from. This is used when building the 344 * initial page table. 345 */ 346LENTRY(get_virt_delta) 347 /* Load the physical address of virt_map */ 348 adrp x29, virt_map 349 add x29, x29, :lo12:virt_map 350 /* Load the virtual address of virt_map stored in virt_map */ 351 ldr x28, [x29] 352 /* Find PA - VA as PA' = VA' - VA + PA = VA' + (PA - VA) = VA' + x29 */ 353 sub x29, x29, x28 354 /* Find the load address for the kernel */ 355 mov x28, #(KERNBASE) 356 add x28, x28, x29 357 ret 358 359 .align 3 360virt_map: 361 .quad virt_map 362LEND(get_virt_delta) 363 364/* 365 * This builds the page tables containing the identity map, and the kernel 366 * virtual map. 367 * 368 * It relys on: 369 * We were loaded to an address that is on a 2MiB boundary 370 * All the memory must not cross a 1GiB boundaty 371 * x28 contains the physical address we were loaded from 372 * 373 * TODO: This is out of date. 374 * There are at least 5 pages before that address for the page tables 375 * The pages used are: 376 * - The Kernel L2 table 377 * - The Kernel L1 table 378 * - The Kernel L0 table (TTBR1) 379 * - The identity (PA = VA) L1 table 380 * - The identity (PA = VA) L0 table (TTBR0) 381 * - The DMAP L1 tables 382 */ 383LENTRY(create_pagetables) 384 /* Save the Link register */ 385 mov x5, x30 386 387 /* Clean the page table */ 388 adrp x6, pagetable 389 add x6, x6, :lo12:pagetable 390 mov x26, x6 391 adrp x27, pagetable_end 392 add x27, x27, :lo12:pagetable_end 3931: 394 stp xzr, xzr, [x6], #16 395 stp xzr, xzr, [x6], #16 396 stp xzr, xzr, [x6], #16 397 stp xzr, xzr, [x6], #16 398 cmp x6, x27 399 b.lo 1b 400 401 /* 402 * Build the TTBR1 maps. 403 */ 404 405 /* Find the size of the kernel */ 406 mov x6, #(KERNBASE) 407 408#if defined(LINUX_BOOT_ABI) 409 /* X19 is used as 'map FDT data' flag */ 410 mov x19, xzr 411 412 /* No modules or FDT pointer ? */ 413 cbz x0, booti_no_fdt 414 415 /* 416 * Test if x0 points to modules descriptor(virtual address) or 417 * to FDT (physical address) 418 */ 419 cmp x0, x6 /* x6 is #(KERNBASE) */ 420 b.lo booti_fdt 421#endif 422 423 /* Booted with modules pointer */ 424 /* Find modulep - begin */ 425 sub x8, x0, x6 426 /* Add two 2MiB pages for the module data and round up */ 427 ldr x7, =(3 * L2_SIZE - 1) 428 add x8, x8, x7 429 b common 430 431#if defined(LINUX_BOOT_ABI) 432booti_fdt: 433 /* Booted by U-Boot booti with FDT data */ 434 /* Set 'map FDT data' flag */ 435 mov x19, #1 436 437booti_no_fdt: 438 /* Booted by U-Boot booti without FTD data */ 439 /* Find the end - begin */ 440 ldr x7, .Lend 441 sub x8, x7, x6 442 443 /* 444 * Add one 2MiB page for copy of FDT data (maximum FDT size), 445 * one for metadata and round up 446 */ 447 ldr x7, =(3 * L2_SIZE - 1) 448 add x8, x8, x7 449#endif 450 451common: 452 /* Get the number of l2 pages to allocate, rounded down */ 453 lsr x10, x8, #(L2_SHIFT) 454 455 /* Create the kernel space L2 table */ 456 mov x6, x26 457 mov x7, #(ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK)) 458 mov x8, #(KERNBASE & L2_BLOCK_MASK) 459 mov x9, x28 460 bl build_l2_block_pagetable 461 462 /* Move to the l1 table */ 463 add x26, x26, #PAGE_SIZE 464 465 /* Link the l1 -> l2 table */ 466 mov x9, x6 467 mov x6, x26 468 bl link_l1_pagetable 469 470 /* Move to the l0 table */ 471 add x24, x26, #PAGE_SIZE 472 473 /* Link the l0 -> l1 table */ 474 mov x9, x6 475 mov x6, x24 476 mov x10, #1 477 bl link_l0_pagetable 478 479 /* Link the DMAP tables */ 480 ldr x8, =DMAP_MIN_ADDRESS 481 adrp x9, pagetable_dmap 482 add x9, x9, :lo12:pagetable_dmap 483 mov x10, #DMAP_TABLES 484 bl link_l0_pagetable 485 486 /* 487 * Build the TTBR0 maps. As TTBR0 maps, they must specify ATTR_S1_nG. 488 * They are only needed early on, so the VA = PA map is uncached. 489 */ 490 add x27, x24, #PAGE_SIZE 491 492 mov x6, x27 /* The initial page table */ 493 494 /* Create the VA = PA map */ 495 mov x7, #(ATTR_S1_nG | ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK)) 496 adrp x16, _start 497 and x16, x16, #(~L2_OFFSET) 498 mov x9, x16 /* PA start */ 499 mov x8, x16 /* VA start (== PA start) */ 500 mov x10, #1 501 bl build_l2_block_pagetable 502 503#if defined(SOCDEV_PA) 504 /* Create a table for the UART */ 505 mov x7, #(ATTR_S1_nG | ATTR_S1_IDX(VM_MEMATTR_DEVICE)) 506 add x16, x16, #(L2_SIZE) /* VA start */ 507 mov x8, x16 508 509 /* Store the socdev virtual address */ 510 add x17, x8, #(SOCDEV_PA & L2_OFFSET) 511 adrp x9, socdev_va 512 str x17, [x9, :lo12:socdev_va] 513 514 mov x9, #(SOCDEV_PA & ~L2_OFFSET) /* PA start */ 515 mov x10, #1 516 bl build_l2_block_pagetable 517#endif 518 519#if defined(LINUX_BOOT_ABI) 520 /* Map FDT data ? */ 521 cbz x19, 1f 522 523 /* Create the mapping for FDT data (2 MiB max) */ 524 mov x7, #(ATTR_S1_nG | ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK)) 525 add x16, x16, #(L2_SIZE) /* VA start */ 526 mov x8, x16 527 mov x9, x0 /* PA start */ 528 /* Update the module pointer to point at the allocated memory */ 529 and x0, x0, #(L2_OFFSET) /* Keep the lower bits */ 530 add x0, x0, x8 /* Add the aligned virtual address */ 531 532 mov x10, #1 533 bl build_l2_block_pagetable 534 5351: 536#endif 537 538 /* Move to the l1 table */ 539 add x27, x27, #PAGE_SIZE 540 541 /* Link the l1 -> l2 table */ 542 mov x9, x6 543 mov x6, x27 544 bl link_l1_pagetable 545 546 /* Move to the l0 table */ 547 add x27, x27, #PAGE_SIZE 548 549 /* Link the l0 -> l1 table */ 550 mov x9, x6 551 mov x6, x27 552 mov x10, #1 553 bl link_l0_pagetable 554 555 /* Restore the Link register */ 556 mov x30, x5 557 ret 558LEND(create_pagetables) 559 560/* 561 * Builds an L0 -> L1 table descriptor 562 * 563 * x6 = L0 table 564 * x8 = Virtual Address 565 * x9 = L1 PA (trashed) 566 * x10 = Entry count (trashed) 567 * x11, x12 and x13 are trashed 568 */ 569LENTRY(link_l0_pagetable) 570 /* 571 * Link an L0 -> L1 table entry. 572 */ 573 /* Find the table index */ 574 lsr x11, x8, #L0_SHIFT 575 and x11, x11, #L0_ADDR_MASK 576 577 /* Build the L0 block entry */ 578 mov x12, #L0_TABLE 579 orr x12, x12, #(TATTR_UXN_TABLE | TATTR_AP_TABLE_NO_EL0) 580 581 /* Only use the output address bits */ 582 lsr x9, x9, #PAGE_SHIFT 5831: orr x13, x12, x9, lsl #PAGE_SHIFT 584 585 /* Store the entry */ 586 str x13, [x6, x11, lsl #3] 587 588 sub x10, x10, #1 589 add x11, x11, #1 590 add x9, x9, #1 591 cbnz x10, 1b 592 593 ret 594LEND(link_l0_pagetable) 595 596/* 597 * Builds an L1 -> L2 table descriptor 598 * 599 * x6 = L1 table 600 * x8 = Virtual Address 601 * x9 = L2 PA (trashed) 602 * x11, x12 and x13 are trashed 603 */ 604LENTRY(link_l1_pagetable) 605 /* 606 * Link an L1 -> L2 table entry. 607 */ 608 /* Find the table index */ 609 lsr x11, x8, #L1_SHIFT 610 and x11, x11, #Ln_ADDR_MASK 611 612 /* Build the L1 block entry */ 613 mov x12, #L1_TABLE 614 615 /* Only use the output address bits */ 616 lsr x9, x9, #PAGE_SHIFT 617 orr x13, x12, x9, lsl #PAGE_SHIFT 618 619 /* Store the entry */ 620 str x13, [x6, x11, lsl #3] 621 622 ret 623LEND(link_l1_pagetable) 624 625/* 626 * Builds count 2 MiB page table entry 627 * x6 = L2 table 628 * x7 = Block attributes 629 * x8 = VA start 630 * x9 = PA start (trashed) 631 * x10 = Entry count (trashed) 632 * x11, x12 and x13 are trashed 633 */ 634LENTRY(build_l2_block_pagetable) 635 /* 636 * Build the L2 table entry. 637 */ 638 /* Find the table index */ 639 lsr x11, x8, #L2_SHIFT 640 and x11, x11, #Ln_ADDR_MASK 641 642 /* Build the L2 block entry */ 643 orr x12, x7, #L2_BLOCK 644 orr x12, x12, #(ATTR_DEFAULT) 645 orr x12, x12, #(ATTR_S1_UXN) 646 647 /* Only use the output address bits */ 648 lsr x9, x9, #L2_SHIFT 649 650 /* Set the physical address for this virtual address */ 6511: orr x13, x12, x9, lsl #L2_SHIFT 652 653 /* Store the entry */ 654 str x13, [x6, x11, lsl #3] 655 656 sub x10, x10, #1 657 add x11, x11, #1 658 add x9, x9, #1 659 cbnz x10, 1b 660 661 ret 662LEND(build_l2_block_pagetable) 663 664LENTRY(start_mmu) 665 dsb sy 666 667 /* Load the exception vectors */ 668 ldr x2, =exception_vectors 669 msr vbar_el1, x2 670 671 /* Load ttbr0 and ttbr1 */ 672 msr ttbr0_el1, x27 673 msr ttbr1_el1, x24 674 isb 675 676 /* Clear the Monitor Debug System control register */ 677 msr mdscr_el1, xzr 678 679 /* Invalidate the TLB */ 680 tlbi vmalle1is 681 dsb ish 682 isb 683 684 ldr x2, mair 685 msr mair_el1, x2 686 687 /* 688 * Setup TCR according to the PARange and ASIDBits fields 689 * from ID_AA64MMFR0_EL1 and the HAFDBS field from the 690 * ID_AA64MMFR1_EL1. More precisely, set TCR_EL1.AS 691 * to 1 only if the ASIDBits field equals 0b0010. 692 */ 693 ldr x2, tcr 694 mrs x3, id_aa64mmfr0_el1 695 696 /* Copy the bottom 3 bits from id_aa64mmfr0_el1 into TCR.IPS */ 697 bfi x2, x3, #(TCR_IPS_SHIFT), #(TCR_IPS_WIDTH) 698 and x3, x3, #(ID_AA64MMFR0_ASIDBits_MASK) 699 700 /* Check if the HW supports 16 bit ASIDS */ 701 cmp x3, #(ID_AA64MMFR0_ASIDBits_16) 702 /* If so x3 == 1, else x3 == 0 */ 703 cset x3, eq 704 /* Set TCR.AS with x3 */ 705 bfi x2, x3, #(TCR_ASID_SHIFT), #(TCR_ASID_WIDTH) 706 707 /* 708 * Check if the HW supports access flag and dirty state updates, 709 * and set TCR_EL1.HA and TCR_EL1.HD accordingly. 710 */ 711 mrs x3, id_aa64mmfr1_el1 712 and x3, x3, #(ID_AA64MMFR1_HAFDBS_MASK) 713 cmp x3, #1 714 b.ne 1f 715 orr x2, x2, #(TCR_HA) 716 b 2f 7171: 718 cmp x3, #2 719 b.ne 2f 720 orr x2, x2, #(TCR_HA | TCR_HD) 7212: 722 msr tcr_el1, x2 723 724 /* 725 * Setup SCTLR. 726 */ 727 ldr x2, sctlr_set 728 ldr x3, sctlr_clear 729 mrs x1, sctlr_el1 730 bic x1, x1, x3 /* Clear the required bits */ 731 orr x1, x1, x2 /* Set the required bits */ 732 msr sctlr_el1, x1 733 isb 734 735 ret 736 737 .align 3 738mair: 739 .quad MAIR_ATTR(MAIR_DEVICE_nGnRnE, VM_MEMATTR_DEVICE_nGnRnE) | \ 740 MAIR_ATTR(MAIR_NORMAL_NC, VM_MEMATTR_UNCACHEABLE) | \ 741 MAIR_ATTR(MAIR_NORMAL_WB, VM_MEMATTR_WRITE_BACK) | \ 742 MAIR_ATTR(MAIR_NORMAL_WT, VM_MEMATTR_WRITE_THROUGH) | \ 743 MAIR_ATTR(MAIR_DEVICE_nGnRE, VM_MEMATTR_DEVICE_nGnRE) 744tcr: 745 .quad (TCR_TxSZ(64 - VIRT_BITS) | TCR_TG1_4K | \ 746 TCR_CACHE_ATTRS | TCR_SMP_ATTRS) 747sctlr_set: 748 /* Bits to set */ 749 .quad (SCTLR_LSMAOE | SCTLR_nTLSMD | SCTLR_UCI | SCTLR_SPAN | \ 750 SCTLR_nTWE | SCTLR_nTWI | SCTLR_UCT | SCTLR_DZE | \ 751 SCTLR_I | SCTLR_SED | SCTLR_SA0 | SCTLR_SA | SCTLR_C | \ 752 SCTLR_M | SCTLR_CP15BEN) 753sctlr_clear: 754 /* Bits to clear */ 755 .quad (SCTLR_EE | SCTLR_E0E | SCTLR_IESB | SCTLR_WXN | SCTLR_UMA | \ 756 SCTLR_ITD | SCTLR_A) 757LEND(start_mmu) 758 759ENTRY(abort) 760 b abort 761END(abort) 762 763 .section .init_pagetable, "aw", %nobits 764 .align PAGE_SHIFT 765 /* 766 * 6 initial tables (in the following order): 767 * L2 for kernel (High addresses) 768 * L1 for kernel 769 * L0 for kernel 770 * L1 bootstrap for user (Low addresses) 771 * L0 bootstrap for user 772 * L0 for user 773 */ 774pagetable: 775 .space PAGE_SIZE 776pagetable_l1_ttbr1: 777 .space PAGE_SIZE 778pagetable_l0_ttbr1: 779 .space PAGE_SIZE 780pagetable_l2_ttbr0_bootstrap: 781 .space PAGE_SIZE 782pagetable_l1_ttbr0_bootstrap: 783 .space PAGE_SIZE 784pagetable_l0_ttbr0_boostrap: 785 .space PAGE_SIZE 786pagetable_l0_ttbr0: 787 .space PAGE_SIZE 788 789 .globl pagetable_dmap 790pagetable_dmap: 791 .space PAGE_SIZE * DMAP_TABLES 792pagetable_end: 793 794el2_pagetable: 795 .space PAGE_SIZE 796 797 .align 4 798initstack: 799 .space (PAGE_SIZE * KSTACK_PAGES) 800initstack_end: 801 802 803.text 804EENTRY(aarch32_sigcode) 805 .word 0xe1a0000d // mov r0, sp 806 .word 0xe2800040 // add r0, r0, #SIGF_UC 807 .word 0xe59f700c // ldr r7, [pc, #12] 808 .word 0xef000000 // swi #0 809 .word 0xe59f7008 // ldr r7, [pc, #8] 810 .word 0xef000000 // swi #0 811 .word 0xeafffffa // b . - 16 812EEND(aarch32_sigcode) 813 .word SYS_sigreturn 814 .word SYS_exit 815 .align 3 816aarch32_esigcode: 817 .data 818 .global sz_aarch32_sigcode 819sz_aarch32_sigcode: 820 .quad aarch32_esigcode - aarch32_sigcode 821