1/*- 2 * Copyright (c) 2012-2014 Andrew Turner 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29#include "assym.s" 30#include <sys/syscall.h> 31#include <machine/asm.h> 32#include <machine/armreg.h> 33#include <machine/hypervisor.h> 34#include <machine/param.h> 35#include <machine/pte.h> 36 37#define VIRT_BITS 39 38 39 .globl kernbase 40 .set kernbase, KERNBASE 41 42#define DEVICE_MEM 0 43#define NORMAL_UNCACHED 1 44#define NORMAL_MEM 2 45 46/* 47 * We assume: 48 * MMU on with an identity map, or off 49 * D-Cache: off 50 * I-Cache: on or off 51 * We are loaded at a 2MiB aligned address 52 */ 53 54#define INIT_STACK_SIZE (PAGE_SIZE * 4) 55 56 .text 57 .globl _start 58_start: 59 /* Drop to EL1 */ 60 bl drop_to_el1 61 62 /* 63 * Disable the MMU. We may have entered the kernel with it on and 64 * will need to update the tables later. If this has been set up 65 * with anything other than a VA == PA map then this will fail, 66 * but in this case the code to find where we are running from 67 * would have also failed. 68 */ 69 dsb sy 70 mrs x2, sctlr_el1 71 bic x2, x2, SCTLR_M 72 msr sctlr_el1, x2 73 isb 74 75 76 /* Get the virt -> phys offset */ 77 bl get_virt_delta 78 79 /* 80 * At this point: 81 * x29 = PA - VA 82 * x28 = Our physical load address 83 */ 84 85 /* Create the page tables */ 86 bl create_pagetables 87 88 /* 89 * At this point: 90 * x27 = TTBR0 table 91 * x26 = TTBR1 table 92 */ 93 94 /* Enable the mmu */ 95 bl start_mmu 96 97 /* Jump to the virtual address space */ 98 ldr x15, .Lvirtdone 99 br x15 100 101virtdone: 102 /* Set up the stack */ 103 adr x25, initstack_end 104 mov sp, x25 105 sub sp, sp, #PCB_SIZE 106 107 /* Zero the BSS */ 108 ldr x15, .Lbss 109 ldr x14, .Lend 1101: 111 str xzr, [x15], #8 112 cmp x15, x14 113 b.lo 1b 114 115 /* Backup the module pointer */ 116 mov x1, x0 117 118 /* Make the page table base a virtual address */ 119 sub x26, x26, x29 120 121 sub sp, sp, #(64 * 4) 122 mov x0, sp 123 124 /* Degate the delda so it is VA -> PA */ 125 neg x29, x29 126 127 str x1, [x0] /* modulep */ 128 str x26, [x0, 8] /* kern_l1pt */ 129 str x29, [x0, 16] /* kern_delta */ 130 str x25, [x0, 24] /* kern_stack */ 131 132 /* trace back starts here */ 133 mov fp, #0 134 /* Branch to C code */ 135 bl initarm 136 bl mi_startup 137 138 /* We should not get here */ 139 brk 0 140 141 .align 3 142.Lvirtdone: 143 .quad virtdone 144.Lbss: 145 .quad __bss_start 146.Lend: 147 .quad _end 148 149/* 150 * If we are started in EL2, configure the required hypervisor 151 * registers and drop to EL1. 152 */ 153drop_to_el1: 154 mrs x1, CurrentEL 155 lsr x1, x1, #2 156 cmp x1, #0x2 157 b.eq 1f 158 ret 1591: 160 /* Configure the Hypervisor */ 161 mov x2, #(HCR_RW) 162 msr hcr_el2, x2 163 164 /* Load the Virtualization Process ID Register */ 165 mrs x2, midr_el1 166 msr vpidr_el2, x2 167 168 /* Load the Virtualization Multiprocess ID Register */ 169 mrs x2, mpidr_el1 170 msr vmpidr_el2, x2 171 172 /* Set the bits that need to be 1 in sctlr_el1 */ 173 ldr x2, .Lsctlr_res1 174 msr sctlr_el1, x2 175 176 /* Don't trap to EL2 for exceptions */ 177 mov x2, #CPTR_RES1 178 msr cptr_el2, x2 179 180 /* Don't trap to EL2 for CP15 traps */ 181 msr hstr_el2, xzr 182 183 /* Hypervisor trap functions */ 184 adr x2, hyp_vectors 185 msr vbar_el2, x2 186 187 mov x2, #(PSR_F | PSR_I | PSR_A | PSR_D | PSR_M_EL1h) 188 msr spsr_el2, x2 189 190 /* Set the address to return to our return address */ 191 msr elr_el2, x30 192 193 eret 194 195 .align 3 196.Lsctlr_res1: 197 .quad SCTLR_RES1 198 199#define VECT_EMPTY \ 200 .align 7; \ 201 1: b 1b 202 203 .align 11 204hyp_vectors: 205 VECT_EMPTY /* Synchronous EL2t */ 206 VECT_EMPTY /* IRQ EL2t */ 207 VECT_EMPTY /* FIQ EL2t */ 208 VECT_EMPTY /* Error EL2t */ 209 210 VECT_EMPTY /* Synchronous EL2h */ 211 VECT_EMPTY /* IRQ EL2h */ 212 VECT_EMPTY /* FIQ EL2h */ 213 VECT_EMPTY /* Error EL2h */ 214 215 VECT_EMPTY /* Synchronous 64-bit EL1 */ 216 VECT_EMPTY /* IRQ 64-bit EL1 */ 217 VECT_EMPTY /* FIQ 64-bit EL1 */ 218 VECT_EMPTY /* Error 64-bit EL1 */ 219 220 VECT_EMPTY /* Synchronous 32-bit EL1 */ 221 VECT_EMPTY /* IRQ 32-bit EL1 */ 222 VECT_EMPTY /* FIQ 32-bit EL1 */ 223 VECT_EMPTY /* Error 32-bit EL1 */ 224 225/* 226 * Get the delta between the physical address we were loaded to and the 227 * virtual address we expect to run from. This is used when building the 228 * initial page table. 229 */ 230get_virt_delta: 231 /* Load the physical address of virt_map */ 232 adr x29, virt_map 233 /* Load the virtual address of virt_map stored in virt_map */ 234 ldr x28, [x29] 235 /* Find PA - VA as PA' = VA' - VA + PA = VA' + (PA - VA) = VA' + x29 */ 236 sub x29, x29, x28 237 /* Find the load address for the kernel */ 238 mov x28, #(KERNBASE) 239 add x28, x28, x29 240 ret 241 242 .align 3 243virt_map: 244 .quad virt_map 245 246/* 247 * This builds the page tables containing the identity map, and the kernel 248 * virtual map. 249 * 250 * It relys on: 251 * We were loaded to an address that is on a 2MiB boundary 252 * All the memory must not cross a 1GiB boundaty 253 * x28 contains the physical address we were loaded from 254 * 255 * TODO: This is out of date. 256 * There are at least 5 pages before that address for the page tables 257 * The pages used are: 258 * - The identity (PA = VA) table (TTBR0) 259 * - The Kernel L1 table (TTBR1)(not yet) 260 * - The PA != VA L2 table to jump into (not yet) 261 * - The FDT L2 table (not yet) 262 */ 263create_pagetables: 264 /* Save the Link register */ 265 mov x5, x30 266 267 /* Clean the page table */ 268 adr x6, pagetable 269 mov x26, x6 270 adr x27, pagetable_end 2711: 272 stp xzr, xzr, [x6], #16 273 stp xzr, xzr, [x6], #16 274 stp xzr, xzr, [x6], #16 275 stp xzr, xzr, [x6], #16 276 cmp x6, x27 277 b.lo 1b 278 279 /* 280 * Build the TTBR1 maps. 281 */ 282 283 /* Find the size of the kernel */ 284 mov x6, #(KERNBASE) 285 ldr x7, .Lend 286 /* Find the end - begin */ 287 sub x8, x7, x6 288 /* Get the number of l2 pages to allocate, rounded down */ 289 lsr x10, x8, #(L2_SHIFT) 290 /* Add 4 MiB for any rounding above and the module data */ 291 add x10, x10, #2 292 293 /* Create the kernel space L2 table */ 294 mov x6, x26 295 mov x7, #NORMAL_MEM 296 mov x8, #(KERNBASE & L2_BLOCK_MASK) 297 mov x9, x28 298 bl build_block_pagetable 299 300 /* Move to the l1 table */ 301 add x26, x26, #PAGE_SIZE 302 303 /* Link the l1 -> l2 table */ 304 mov x9, x6 305 mov x6, x26 306 bl link_l1_pagetable 307 308 309 /* 310 * Build the TTBR0 maps. 311 */ 312 add x27, x26, #PAGE_SIZE 313 314#if defined(SOCDEV_PA) && defined(SOCDEV_VA) 315 /* Create a table for the UART */ 316 mov x6, x27 /* The initial page table */ 317 mov x7, #DEVICE_MEM 318 mov x8, #(SOCDEV_VA) /* VA start */ 319 mov x9, #(SOCDEV_PA) /* PA start */ 320 bl build_section_pagetable 321#endif 322 323 /* Create the VA = PA map */ 324 mov x6, x27 /* The initial page table */ 325 mov x7, #NORMAL_UNCACHED /* Uncached as it's only needed early on */ 326 mov x9, x27 327 mov x8, x9 /* VA start (== PA start) */ 328 bl build_section_pagetable 329 330 /* Restore the Link register */ 331 mov x30, x5 332 ret 333 334/* 335 * Builds a 1 GiB page table entry 336 * x6 = L1 table 337 * x7 = Type (0 = Device, 1 = Normal) 338 * x8 = VA start 339 * x9 = PA start (trashed) 340 * x11, x12 and x13 are trashed 341 */ 342build_section_pagetable: 343 /* 344 * Build the L1 table entry. 345 */ 346 /* Find the table index */ 347 lsr x11, x8, #L1_SHIFT 348 and x11, x11, #Ln_ADDR_MASK 349 350 /* Build the L1 block entry */ 351 lsl x12, x7, #2 352 orr x12, x12, #L1_BLOCK 353 orr x12, x12, #(ATTR_AF) 354 355 /* Only use the output address bits */ 356 lsr x9, x9, #L1_SHIFT 357 orr x12, x12, x9, lsl #L1_SHIFT 358 359 /* Store the entry */ 360 str x12, [x6, x11, lsl #3] 361 362 ret 363 364/* 365 * Builds an L1 -> L2 table descriptor 366 * 367 * This is a link for a 1GiB block of memory with up to 2MiB regions mapped 368 * within it by build_block_pagetable. 369 * 370 * x6 = L1 table 371 * x8 = Virtual Address 372 * x9 = L2 PA (trashed) 373 * x11, x12 and x13 are trashed 374 */ 375link_l1_pagetable: 376 /* 377 * Link an L1 -> L2 table entry. 378 */ 379 /* Find the table index */ 380 lsr x11, x8, #L1_SHIFT 381 and x11, x11, #Ln_ADDR_MASK 382 383 /* Build the L1 block entry */ 384 mov x12, #L1_TABLE 385 386 /* Only use the output address bits */ 387 lsr x9, x9, #12 388 orr x12, x12, x9, lsl #12 389 390 /* Store the entry */ 391 str x12, [x6, x11, lsl #3] 392 393 ret 394 395/* 396 * Builds count 2 MiB page table entry 397 * x6 = L2 table 398 * x7 = Type (0 = Device, 1 = Normal) 399 * x8 = VA start 400 * x9 = PA start (trashed) 401 * x10 = Entry count (TODO) 402 * x11, x12 and x13 are trashed 403 */ 404build_block_pagetable: 405 /* 406 * Build the L2 table entry. 407 */ 408 /* Find the table index */ 409 lsr x11, x8, #L2_SHIFT 410 and x11, x11, #Ln_ADDR_MASK 411 412 /* Build the L2 block entry */ 413 lsl x12, x7, #2 414 orr x12, x12, #L2_BLOCK 415 orr x12, x12, #(ATTR_AF) 416 417 /* Only use the output address bits */ 418 lsr x9, x9, #L2_SHIFT 419 420 /* Set the physical address for this virtual address */ 4211: orr x12, x12, x9, lsl #L2_SHIFT 422 423 /* Store the entry */ 424 str x12, [x6, x11, lsl #3] 425 426 /* Clear the address bits */ 427 and x12, x12, #ATTR_MASK_L 428 429 sub x10, x10, #1 430 add x11, x11, #1 431 add x9, x9, #1 432 cbnz x10, 1b 433 4342: ret 435 436start_mmu: 437 dsb sy 438 439 /* Load the exception vectors */ 440 ldr x2, =exception_vectors 441 msr vbar_el1, x2 442 443 /* Load ttbr0 and ttbr1 */ 444 msr ttbr0_el1, x27 445 msr ttbr1_el1, x26 446 isb 447 448 /* Clear the Monitor Debug System control register */ 449 msr mdscr_el1, xzr 450 451 /* Invalidate the TLB */ 452 tlbi vmalle1is 453 454 ldr x2, mair 455 msr mair_el1, x2 456 457 /* Setup TCR according to PARange bits from ID_AA64MMFR0_EL1 */ 458 ldr x2, tcr 459 mrs x3, id_aa64mmfr0_el1 460 bfi x2, x3, #32, #3 461 msr tcr_el1, x2 462 463 /* Setup SCTLR */ 464 ldr x2, sctlr_set 465 ldr x3, sctlr_clear 466 mrs x1, sctlr_el1 467 bic x1, x1, x3 /* Clear the required bits */ 468 orr x1, x1, x2 /* Set the required bits */ 469 msr sctlr_el1, x1 470 isb 471 472 ret 473 474 .align 3 475mair: 476 /* Device Normal, no cache Normal, write-back */ 477 .quad MAIR_ATTR(0x00, 0) | MAIR_ATTR(0x44, 1) | MAIR_ATTR(0xff, 2) 478tcr: 479 .quad (TCR_TxSZ(64 - VIRT_BITS) | TCR_ASID_16 | TCR_TG1_4K) 480sctlr_set: 481 /* Bits to set */ 482 .quad (SCTLR_UCI | SCTLR_nTWE | SCTLR_nTWI | SCTLR_UCT | SCTLR_DZE | \ 483 SCTLR_I | SCTLR_SED | SCTLR_C | SCTLR_M) 484sctlr_clear: 485 /* Bits to clear */ 486 .quad (SCTLR_EE | SCTLR_EOE | SCTLR_WXN | SCTLR_UMA | SCTLR_ITD | \ 487 SCTLR_THEE | SCTLR_CP15BEN | SCTLR_SA0 | SCTLR_SA | SCTLR_A) 488 489 .globl abort 490abort: 491 b abort 492 493 //.section .init_pagetable 494 .align 12 /* 4KiB aligned */ 495 /* 496 * 3 initial tables (in the following order): 497 * L2 for kernel (High addresses) 498 * L1 for kernel 499 * L1 for user (Low addresses) 500 */ 501pagetable: 502 .space PAGE_SIZE 503pagetable_l1_ttbr1: 504 .space PAGE_SIZE 505pagetable_l1_ttbr0: 506 .space PAGE_SIZE 507pagetable_end: 508 509el2_pagetable: 510 .space PAGE_SIZE 511 512 .globl init_pt_va 513init_pt_va: 514 .quad pagetable /* XXX: Keep page tables VA */ 515 516 .align 4 517initstack: 518 .space (PAGE_SIZE * KSTACK_PAGES) 519initstack_end: 520 521 522ENTRY(sigcode) 523 mov x0, sp 524 add x0, x0, #SF_UC 525 5261: 527 mov x8, #SYS_sigreturn 528 svc 0 529 530 /* sigreturn failed, exit */ 531 mov x8, #SYS_exit 532 svc 0 533 534 b 1b 535END(sigcode) 536 /* This may be copied to the stack, keep it 16-byte aligned */ 537 .align 3 538esigcode: 539 540 .data 541 .align 3 542 .global szsigcode 543szsigcode: 544 .quad esigcode - sigcode 545