1/*- 2 * Copyright (c) 2012-2014 Andrew Turner 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29#include "assym.inc" 30#include "opt_kstack_pages.h" 31#include <sys/syscall.h> 32#include <machine/asm.h> 33#include <machine/armreg.h> 34#include <machine/hypervisor.h> 35#include <machine/param.h> 36#include <machine/pte.h> 37#include <machine/vm.h> 38#include <machine/vmparam.h> 39 40#define VIRT_BITS 48 41#define DMAP_TABLES ((DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS) >> L0_SHIFT) 42 43 .globl kernbase 44 .set kernbase, KERNBASE 45 46/* 47 * We assume: 48 * MMU on with an identity map, or off 49 * D-Cache: off 50 * I-Cache: on or off 51 * We are loaded at a 2MiB aligned address 52 */ 53 54ENTRY(_start) 55 /* Drop to EL1 */ 56 bl drop_to_el1 57 58 /* 59 * Disable the MMU. We may have entered the kernel with it on and 60 * will need to update the tables later. If this has been set up 61 * with anything other than a VA == PA map then this will fail, 62 * but in this case the code to find where we are running from 63 * would have also failed. 64 */ 65 dsb sy 66 mrs x2, sctlr_el1 67 bic x2, x2, SCTLR_M 68 msr sctlr_el1, x2 69 isb 70 71 /* Set the context id */ 72 msr contextidr_el1, xzr 73 74 /* Get the virt -> phys offset */ 75 bl get_virt_delta 76 77 /* 78 * At this point: 79 * x29 = PA - VA 80 * x28 = Our physical load address 81 */ 82 83 /* Create the page tables */ 84 bl create_pagetables 85 86 /* 87 * At this point: 88 * x27 = TTBR0 table 89 * x26 = Kernel L1 table 90 * x24 = TTBR1 table 91 */ 92 93 /* Enable the mmu */ 94 bl start_mmu 95 96 /* Load the new ttbr0 pagetable */ 97 adrp x27, pagetable_l0_ttbr0 98 add x27, x27, :lo12:pagetable_l0_ttbr0 99 100 /* Jump to the virtual address space */ 101 ldr x15, .Lvirtdone 102 br x15 103 104virtdone: 105 /* Set up the stack */ 106 adrp x25, initstack_end 107 add x25, x25, :lo12:initstack_end 108 mov sp, x25 109 sub sp, sp, #PCB_SIZE 110 111 /* Zero the BSS */ 112 ldr x15, .Lbss 113 ldr x14, .Lend 1141: 115 str xzr, [x15], #8 116 cmp x15, x14 117 b.lo 1b 118 119#if defined(PERTHREAD_SSP) 120 /* Set sp_el0 to the boot canary for early per-thread SSP to work */ 121 adrp x15, boot_canary 122 add x15, x15, :lo12:boot_canary 123 msr sp_el0, x15 124#endif 125 126 /* Backup the module pointer */ 127 mov x1, x0 128 129 /* Make the page table base a virtual address */ 130 sub x26, x26, x29 131 sub x24, x24, x29 132 133 sub sp, sp, #BOOTPARAMS_SIZE 134 mov x0, sp 135 136 /* Degate the delda so it is VA -> PA */ 137 neg x29, x29 138 139 str x1, [x0, #BP_MODULEP] 140 str x26, [x0, #BP_KERN_L1PT] 141 str x29, [x0, #BP_KERN_DELTA] 142 adrp x25, initstack 143 add x25, x25, :lo12:initstack 144 str x25, [x0, #BP_KERN_STACK] 145 str x24, [x0, #BP_KERN_L0PT] 146 str x27, [x0, #BP_KERN_TTBR0] 147 str x23, [x0, #BP_BOOT_EL] 148 149 /* trace back starts here */ 150 mov fp, #0 151 /* Branch to C code */ 152 bl initarm 153 /* We are done with the boot params */ 154 add sp, sp, #BOOTPARAMS_SIZE 155 bl mi_startup 156 157 /* We should not get here */ 158 brk 0 159 160 .align 3 161.Lvirtdone: 162 .quad virtdone 163.Lbss: 164 .quad __bss_start 165.Lend: 166 .quad __bss_end 167END(_start) 168 169#ifdef SMP 170/* 171 * mpentry(unsigned long) 172 * 173 * Called by a core when it is being brought online. 174 * The data in x0 is passed straight to init_secondary. 175 */ 176ENTRY(mpentry) 177 /* Disable interrupts */ 178 msr daifset, #DAIF_INTR 179 180 /* Drop to EL1 */ 181 bl drop_to_el1 182 183 /* Set the context id */ 184 msr contextidr_el1, xzr 185 186 /* Load the kernel page table */ 187 adrp x24, pagetable_l0_ttbr1 188 add x24, x24, :lo12:pagetable_l0_ttbr1 189 /* Load the identity page table */ 190 adrp x27, pagetable_l0_ttbr0_boostrap 191 add x27, x27, :lo12:pagetable_l0_ttbr0_boostrap 192 193 /* Enable the mmu */ 194 bl start_mmu 195 196 /* Load the new ttbr0 pagetable */ 197 adrp x27, pagetable_l0_ttbr0 198 add x27, x27, :lo12:pagetable_l0_ttbr0 199 200 /* Jump to the virtual address space */ 201 ldr x15, =mp_virtdone 202 br x15 203 204mp_virtdone: 205 /* Start using the AP boot stack */ 206 ldr x4, =bootstack 207 ldr x4, [x4] 208 mov sp, x4 209 210#if defined(PERTHREAD_SSP) 211 /* Set sp_el0 to the boot canary for early per-thread SSP to work */ 212 adrp x15, boot_canary 213 add x15, x15, :lo12:boot_canary 214 msr sp_el0, x15 215#endif 216 217 /* Load the kernel ttbr0 pagetable */ 218 msr ttbr0_el1, x27 219 isb 220 221 /* Invalidate the TLB */ 222 tlbi vmalle1 223 dsb sy 224 isb 225 226 b init_secondary 227END(mpentry) 228#endif 229 230/* 231 * If we are started in EL2, configure the required hypervisor 232 * registers and drop to EL1. 233 */ 234LENTRY(drop_to_el1) 235 mrs x23, CurrentEL 236 lsr x23, x23, #2 237 cmp x23, #0x2 238 b.eq 1f 239 ret 2401: 241 /* Configure the Hypervisor */ 242 mov x2, #(HCR_RW) 243 msr hcr_el2, x2 244 245 /* Load the Virtualization Process ID Register */ 246 mrs x2, midr_el1 247 msr vpidr_el2, x2 248 249 /* Load the Virtualization Multiprocess ID Register */ 250 mrs x2, mpidr_el1 251 msr vmpidr_el2, x2 252 253 /* Set the bits that need to be 1 in sctlr_el1 */ 254 ldr x2, .Lsctlr_res1 255 msr sctlr_el1, x2 256 257 /* Don't trap to EL2 for exceptions */ 258 mov x2, #CPTR_RES1 259 msr cptr_el2, x2 260 261 /* Don't trap to EL2 for CP15 traps */ 262 msr hstr_el2, xzr 263 264 /* Enable access to the physical timers at EL1 */ 265 mrs x2, cnthctl_el2 266 orr x2, x2, #(CNTHCTL_EL1PCTEN | CNTHCTL_EL1PCEN) 267 msr cnthctl_el2, x2 268 269 /* Set the counter offset to a known value */ 270 msr cntvoff_el2, xzr 271 272 /* Hypervisor trap functions */ 273 adrp x2, hyp_vectors 274 add x2, x2, :lo12:hyp_vectors 275 msr vbar_el2, x2 276 277 mov x2, #(PSR_F | PSR_I | PSR_A | PSR_D | PSR_M_EL1h) 278 msr spsr_el2, x2 279 280 /* Configure GICv3 CPU interface */ 281 mrs x2, id_aa64pfr0_el1 282 /* Extract GIC bits from the register */ 283 ubfx x2, x2, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_BITS 284 /* GIC[3:0] == 0001 - GIC CPU interface via special regs. supported */ 285 cmp x2, #(ID_AA64PFR0_GIC_CPUIF_EN >> ID_AA64PFR0_GIC_SHIFT) 286 b.ne 2f 287 288 mrs x2, icc_sre_el2 289 orr x2, x2, #ICC_SRE_EL2_EN /* Enable access from insecure EL1 */ 290 orr x2, x2, #ICC_SRE_EL2_SRE /* Enable system registers */ 291 msr icc_sre_el2, x2 2922: 293 294 /* Set the address to return to our return address */ 295 msr elr_el2, x30 296 isb 297 298 eret 299 300 .align 3 301.Lsctlr_res1: 302 .quad SCTLR_RES1 303LEND(drop_to_el1) 304 305#define VECT_EMPTY \ 306 .align 7; \ 307 1: b 1b 308 309 .align 11 310hyp_vectors: 311 VECT_EMPTY /* Synchronous EL2t */ 312 VECT_EMPTY /* IRQ EL2t */ 313 VECT_EMPTY /* FIQ EL2t */ 314 VECT_EMPTY /* Error EL2t */ 315 316 VECT_EMPTY /* Synchronous EL2h */ 317 VECT_EMPTY /* IRQ EL2h */ 318 VECT_EMPTY /* FIQ EL2h */ 319 VECT_EMPTY /* Error EL2h */ 320 321 VECT_EMPTY /* Synchronous 64-bit EL1 */ 322 VECT_EMPTY /* IRQ 64-bit EL1 */ 323 VECT_EMPTY /* FIQ 64-bit EL1 */ 324 VECT_EMPTY /* Error 64-bit EL1 */ 325 326 VECT_EMPTY /* Synchronous 32-bit EL1 */ 327 VECT_EMPTY /* IRQ 32-bit EL1 */ 328 VECT_EMPTY /* FIQ 32-bit EL1 */ 329 VECT_EMPTY /* Error 32-bit EL1 */ 330 331/* 332 * Get the delta between the physical address we were loaded to and the 333 * virtual address we expect to run from. This is used when building the 334 * initial page table. 335 */ 336LENTRY(get_virt_delta) 337 /* Load the physical address of virt_map */ 338 adrp x29, virt_map 339 add x29, x29, :lo12:virt_map 340 /* Load the virtual address of virt_map stored in virt_map */ 341 ldr x28, [x29] 342 /* Find PA - VA as PA' = VA' - VA + PA = VA' + (PA - VA) = VA' + x29 */ 343 sub x29, x29, x28 344 /* Find the load address for the kernel */ 345 mov x28, #(KERNBASE) 346 add x28, x28, x29 347 ret 348 349 .align 3 350virt_map: 351 .quad virt_map 352LEND(get_virt_delta) 353 354/* 355 * This builds the page tables containing the identity map, and the kernel 356 * virtual map. 357 * 358 * It relys on: 359 * We were loaded to an address that is on a 2MiB boundary 360 * All the memory must not cross a 1GiB boundaty 361 * x28 contains the physical address we were loaded from 362 * 363 * TODO: This is out of date. 364 * There are at least 5 pages before that address for the page tables 365 * The pages used are: 366 * - The Kernel L2 table 367 * - The Kernel L1 table 368 * - The Kernel L0 table (TTBR1) 369 * - The identity (PA = VA) L1 table 370 * - The identity (PA = VA) L0 table (TTBR0) 371 * - The DMAP L1 tables 372 */ 373LENTRY(create_pagetables) 374 /* Save the Link register */ 375 mov x5, x30 376 377 /* Clean the page table */ 378 adrp x6, pagetable 379 add x6, x6, :lo12:pagetable 380 mov x26, x6 381 adrp x27, pagetable_end 382 add x27, x27, :lo12:pagetable_end 3831: 384 stp xzr, xzr, [x6], #16 385 stp xzr, xzr, [x6], #16 386 stp xzr, xzr, [x6], #16 387 stp xzr, xzr, [x6], #16 388 cmp x6, x27 389 b.lo 1b 390 391 /* 392 * Build the TTBR1 maps. 393 */ 394 395 /* Find the size of the kernel */ 396 mov x6, #(KERNBASE) 397 398#if defined(LINUX_BOOT_ABI) 399 /* X19 is used as 'map FDT data' flag */ 400 mov x19, xzr 401 402 /* No modules or FDT pointer ? */ 403 cbz x0, booti_no_fdt 404 405 /* 406 * Test if x0 points to modules descriptor(virtual address) or 407 * to FDT (physical address) 408 */ 409 cmp x0, x6 /* x6 is #(KERNBASE) */ 410 b.lo booti_fdt 411#endif 412 413 /* Booted with modules pointer */ 414 /* Find modulep - begin */ 415 sub x8, x0, x6 416 /* Add two 2MiB pages for the module data and round up */ 417 ldr x7, =(3 * L2_SIZE - 1) 418 add x8, x8, x7 419 b common 420 421#if defined(LINUX_BOOT_ABI) 422booti_fdt: 423 /* Booted by U-Boot booti with FDT data */ 424 /* Set 'map FDT data' flag */ 425 mov x19, #1 426 427booti_no_fdt: 428 /* Booted by U-Boot booti without FTD data */ 429 /* Find the end - begin */ 430 ldr x7, .Lend 431 sub x8, x7, x6 432 433 /* 434 * Add one 2MiB page for copy of FDT data (maximum FDT size), 435 * one for metadata and round up 436 */ 437 ldr x7, =(3 * L2_SIZE - 1) 438 add x8, x8, x7 439#endif 440 441common: 442 /* Get the number of l2 pages to allocate, rounded down */ 443 lsr x10, x8, #(L2_SHIFT) 444 445 /* Create the kernel space L2 table */ 446 mov x6, x26 447 mov x7, #(ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK)) 448 mov x8, #(KERNBASE & L2_BLOCK_MASK) 449 mov x9, x28 450 bl build_l2_block_pagetable 451 452 /* Move to the l1 table */ 453 add x26, x26, #PAGE_SIZE 454 455 /* Link the l1 -> l2 table */ 456 mov x9, x6 457 mov x6, x26 458 bl link_l1_pagetable 459 460 /* Move to the l0 table */ 461 add x24, x26, #PAGE_SIZE 462 463 /* Link the l0 -> l1 table */ 464 mov x9, x6 465 mov x6, x24 466 mov x10, #1 467 bl link_l0_pagetable 468 469 /* Link the DMAP tables */ 470 ldr x8, =DMAP_MIN_ADDRESS 471 adrp x9, pagetable_dmap 472 add x9, x9, :lo12:pagetable_dmap 473 mov x10, #DMAP_TABLES 474 bl link_l0_pagetable 475 476 /* 477 * Build the TTBR0 maps. As TTBR0 maps, they must specify ATTR_S1_nG. 478 * They are only needed early on, so the VA = PA map is uncached. 479 */ 480 add x27, x24, #PAGE_SIZE 481 482 mov x6, x27 /* The initial page table */ 483 484 /* Create the VA = PA map */ 485 mov x7, #(ATTR_S1_nG | ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK)) 486 adrp x16, _start 487 and x16, x16, #(~L2_OFFSET) 488 mov x9, x16 /* PA start */ 489 mov x8, x16 /* VA start (== PA start) */ 490 mov x10, #1 491 bl build_l2_block_pagetable 492 493#if defined(SOCDEV_PA) 494 /* Create a table for the UART */ 495 mov x7, #(ATTR_S1_nG | ATTR_S1_IDX(VM_MEMATTR_DEVICE)) 496 add x16, x16, #(L2_SIZE) /* VA start */ 497 mov x8, x16 498 499 /* Store the socdev virtual address */ 500 add x17, x8, #(SOCDEV_PA & L2_OFFSET) 501 adrp x9, socdev_va 502 str x17, [x9, :lo12:socdev_va] 503 504 mov x9, #(SOCDEV_PA & ~L2_OFFSET) /* PA start */ 505 mov x10, #1 506 bl build_l2_block_pagetable 507#endif 508 509#if defined(LINUX_BOOT_ABI) 510 /* Map FDT data ? */ 511 cbz x19, 1f 512 513 /* Create the mapping for FDT data (2 MiB max) */ 514 mov x7, #(ATTR_S1_nG | ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK)) 515 add x16, x16, #(L2_SIZE) /* VA start */ 516 mov x8, x16 517 mov x9, x0 /* PA start */ 518 /* Update the module pointer to point at the allocated memory */ 519 and x0, x0, #(L2_OFFSET) /* Keep the lower bits */ 520 add x0, x0, x8 /* Add the aligned virtual address */ 521 522 mov x10, #1 523 bl build_l2_block_pagetable 524 5251: 526#endif 527 528 /* Move to the l1 table */ 529 add x27, x27, #PAGE_SIZE 530 531 /* Link the l1 -> l2 table */ 532 mov x9, x6 533 mov x6, x27 534 bl link_l1_pagetable 535 536 /* Move to the l0 table */ 537 add x27, x27, #PAGE_SIZE 538 539 /* Link the l0 -> l1 table */ 540 mov x9, x6 541 mov x6, x27 542 mov x10, #1 543 bl link_l0_pagetable 544 545 /* Restore the Link register */ 546 mov x30, x5 547 ret 548LEND(create_pagetables) 549 550/* 551 * Builds an L0 -> L1 table descriptor 552 * 553 * x6 = L0 table 554 * x8 = Virtual Address 555 * x9 = L1 PA (trashed) 556 * x10 = Entry count (trashed) 557 * x11, x12 and x13 are trashed 558 */ 559LENTRY(link_l0_pagetable) 560 /* 561 * Link an L0 -> L1 table entry. 562 */ 563 /* Find the table index */ 564 lsr x11, x8, #L0_SHIFT 565 and x11, x11, #L0_ADDR_MASK 566 567 /* Build the L0 block entry */ 568 mov x12, #L0_TABLE 569 orr x12, x12, #(TATTR_UXN_TABLE | TATTR_AP_TABLE_NO_EL0) 570 571 /* Only use the output address bits */ 572 lsr x9, x9, #PAGE_SHIFT 5731: orr x13, x12, x9, lsl #PAGE_SHIFT 574 575 /* Store the entry */ 576 str x13, [x6, x11, lsl #3] 577 578 sub x10, x10, #1 579 add x11, x11, #1 580 add x9, x9, #1 581 cbnz x10, 1b 582 583 ret 584LEND(link_l0_pagetable) 585 586/* 587 * Builds an L1 -> L2 table descriptor 588 * 589 * x6 = L1 table 590 * x8 = Virtual Address 591 * x9 = L2 PA (trashed) 592 * x11, x12 and x13 are trashed 593 */ 594LENTRY(link_l1_pagetable) 595 /* 596 * Link an L1 -> L2 table entry. 597 */ 598 /* Find the table index */ 599 lsr x11, x8, #L1_SHIFT 600 and x11, x11, #Ln_ADDR_MASK 601 602 /* Build the L1 block entry */ 603 mov x12, #L1_TABLE 604 605 /* Only use the output address bits */ 606 lsr x9, x9, #PAGE_SHIFT 607 orr x13, x12, x9, lsl #PAGE_SHIFT 608 609 /* Store the entry */ 610 str x13, [x6, x11, lsl #3] 611 612 ret 613LEND(link_l1_pagetable) 614 615/* 616 * Builds count 2 MiB page table entry 617 * x6 = L2 table 618 * x7 = Block attributes 619 * x8 = VA start 620 * x9 = PA start (trashed) 621 * x10 = Entry count (trashed) 622 * x11, x12 and x13 are trashed 623 */ 624LENTRY(build_l2_block_pagetable) 625 /* 626 * Build the L2 table entry. 627 */ 628 /* Find the table index */ 629 lsr x11, x8, #L2_SHIFT 630 and x11, x11, #Ln_ADDR_MASK 631 632 /* Build the L2 block entry */ 633 orr x12, x7, #L2_BLOCK 634 orr x12, x12, #(ATTR_DEFAULT) 635 orr x12, x12, #(ATTR_S1_UXN) 636 637 /* Only use the output address bits */ 638 lsr x9, x9, #L2_SHIFT 639 640 /* Set the physical address for this virtual address */ 6411: orr x13, x12, x9, lsl #L2_SHIFT 642 643 /* Store the entry */ 644 str x13, [x6, x11, lsl #3] 645 646 sub x10, x10, #1 647 add x11, x11, #1 648 add x9, x9, #1 649 cbnz x10, 1b 650 651 ret 652LEND(build_l2_block_pagetable) 653 654LENTRY(start_mmu) 655 dsb sy 656 657 /* Load the exception vectors */ 658 ldr x2, =exception_vectors 659 msr vbar_el1, x2 660 661 /* Load ttbr0 and ttbr1 */ 662 msr ttbr0_el1, x27 663 msr ttbr1_el1, x24 664 isb 665 666 /* Clear the Monitor Debug System control register */ 667 msr mdscr_el1, xzr 668 669 /* Invalidate the TLB */ 670 tlbi vmalle1is 671 dsb ish 672 isb 673 674 ldr x2, mair 675 msr mair_el1, x2 676 677 /* 678 * Setup TCR according to the PARange and ASIDBits fields 679 * from ID_AA64MMFR0_EL1 and the HAFDBS field from the 680 * ID_AA64MMFR1_EL1. More precisely, set TCR_EL1.AS 681 * to 1 only if the ASIDBits field equals 0b0010. 682 */ 683 ldr x2, tcr 684 mrs x3, id_aa64mmfr0_el1 685 686 /* Copy the bottom 3 bits from id_aa64mmfr0_el1 into TCR.IPS */ 687 bfi x2, x3, #(TCR_IPS_SHIFT), #(TCR_IPS_WIDTH) 688 and x3, x3, #(ID_AA64MMFR0_ASIDBits_MASK) 689 690 /* Check if the HW supports 16 bit ASIDS */ 691 cmp x3, #(ID_AA64MMFR0_ASIDBits_16) 692 /* If so x3 == 1, else x3 == 0 */ 693 cset x3, eq 694 /* Set TCR.AS with x3 */ 695 bfi x2, x3, #(TCR_ASID_SHIFT), #(TCR_ASID_WIDTH) 696 697 /* 698 * Check if the HW supports access flag and dirty state updates, 699 * and set TCR_EL1.HA and TCR_EL1.HD accordingly. 700 */ 701 mrs x3, id_aa64mmfr1_el1 702 and x3, x3, #(ID_AA64MMFR1_HAFDBS_MASK) 703 cmp x3, #1 704 b.ne 1f 705 orr x2, x2, #(TCR_HA) 706 b 2f 7071: 708 cmp x3, #2 709 b.ne 2f 710 orr x2, x2, #(TCR_HA | TCR_HD) 7112: 712 msr tcr_el1, x2 713 714 /* 715 * Setup SCTLR. 716 */ 717 ldr x2, sctlr_set 718 ldr x3, sctlr_clear 719 mrs x1, sctlr_el1 720 bic x1, x1, x3 /* Clear the required bits */ 721 orr x1, x1, x2 /* Set the required bits */ 722 msr sctlr_el1, x1 723 isb 724 725 ret 726 727 .align 3 728mair: 729 .quad MAIR_ATTR(MAIR_DEVICE_nGnRnE, VM_MEMATTR_DEVICE_nGnRnE) | \ 730 MAIR_ATTR(MAIR_NORMAL_NC, VM_MEMATTR_UNCACHEABLE) | \ 731 MAIR_ATTR(MAIR_NORMAL_WB, VM_MEMATTR_WRITE_BACK) | \ 732 MAIR_ATTR(MAIR_NORMAL_WT, VM_MEMATTR_WRITE_THROUGH) | \ 733 MAIR_ATTR(MAIR_DEVICE_nGnRE, VM_MEMATTR_DEVICE_nGnRE) 734tcr: 735 .quad (TCR_TxSZ(64 - VIRT_BITS) | TCR_TG1_4K | \ 736 TCR_CACHE_ATTRS | TCR_SMP_ATTRS) 737sctlr_set: 738 /* Bits to set */ 739 .quad (SCTLR_LSMAOE | SCTLR_nTLSMD | SCTLR_UCI | SCTLR_SPAN | \ 740 SCTLR_nTWE | SCTLR_nTWI | SCTLR_UCT | SCTLR_DZE | \ 741 SCTLR_I | SCTLR_SED | SCTLR_SA0 | SCTLR_SA | SCTLR_C | \ 742 SCTLR_M | SCTLR_CP15BEN) 743sctlr_clear: 744 /* Bits to clear */ 745 .quad (SCTLR_EE | SCTLR_E0E | SCTLR_IESB | SCTLR_WXN | SCTLR_UMA | \ 746 SCTLR_ITD | SCTLR_A) 747LEND(start_mmu) 748 749ENTRY(abort) 750 b abort 751END(abort) 752 753 .section .init_pagetable, "aw", %nobits 754 .align PAGE_SHIFT 755 /* 756 * 6 initial tables (in the following order): 757 * L2 for kernel (High addresses) 758 * L1 for kernel 759 * L0 for kernel 760 * L1 bootstrap for user (Low addresses) 761 * L0 bootstrap for user 762 * L0 for user 763 */ 764pagetable: 765 .space PAGE_SIZE 766pagetable_l1_ttbr1: 767 .space PAGE_SIZE 768pagetable_l0_ttbr1: 769 .space PAGE_SIZE 770pagetable_l2_ttbr0_bootstrap: 771 .space PAGE_SIZE 772pagetable_l1_ttbr0_bootstrap: 773 .space PAGE_SIZE 774pagetable_l0_ttbr0_boostrap: 775 .space PAGE_SIZE 776pagetable_l0_ttbr0: 777 .space PAGE_SIZE 778 779 .globl pagetable_dmap 780pagetable_dmap: 781 .space PAGE_SIZE * DMAP_TABLES 782pagetable_end: 783 784el2_pagetable: 785 .space PAGE_SIZE 786 787 .align 4 788initstack: 789 .space (PAGE_SIZE * KSTACK_PAGES) 790initstack_end: 791 792 793.text 794EENTRY(aarch32_sigcode) 795 .word 0xe1a0000d // mov r0, sp 796 .word 0xe2800040 // add r0, r0, #SIGF_UC 797 .word 0xe59f700c // ldr r7, [pc, #12] 798 .word 0xef000000 // swi #0 799 .word 0xe59f7008 // ldr r7, [pc, #8] 800 .word 0xef000000 // swi #0 801 .word 0xeafffffa // b . - 16 802EEND(aarch32_sigcode) 803 .word SYS_sigreturn 804 .word SYS_exit 805 .align 3 806aarch32_esigcode: 807 .data 808 .global sz_aarch32_sigcode 809sz_aarch32_sigcode: 810 .quad aarch32_esigcode - aarch32_sigcode 811