1/*- 2 * Copyright (c) 2012-2014 Andrew Turner 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29#include "assym.inc" 30#include "opt_kstack_pages.h" 31#include <sys/syscall.h> 32#include <machine/asm.h> 33#include <machine/armreg.h> 34#include <machine/hypervisor.h> 35#include <machine/param.h> 36#include <machine/pte.h> 37#include <machine/vm.h> 38#include <machine/vmparam.h> 39 40#define VIRT_BITS 48 41 42 .globl kernbase 43 .set kernbase, KERNBASE 44 45/* 46 * We assume: 47 * MMU on with an identity map, or off 48 * D-Cache: off 49 * I-Cache: on or off 50 * We are loaded at a 2MiB aligned address 51 */ 52 53ENTRY(_start) 54 /* Drop to EL1 */ 55 bl drop_to_el1 56 57 /* 58 * Disable the MMU. We may have entered the kernel with it on and 59 * will need to update the tables later. If this has been set up 60 * with anything other than a VA == PA map then this will fail, 61 * but in this case the code to find where we are running from 62 * would have also failed. 63 */ 64 dsb sy 65 mrs x2, sctlr_el1 66 bic x2, x2, SCTLR_M 67 msr sctlr_el1, x2 68 isb 69 70 /* Set the context id */ 71 msr contextidr_el1, xzr 72 73 /* Get the virt -> phys offset */ 74 bl get_virt_delta 75 76 /* 77 * At this point: 78 * x29 = PA - VA 79 * x28 = Our physical load address 80 */ 81 82 /* Create the page tables */ 83 bl create_pagetables 84 85 /* 86 * At this point: 87 * x27 = TTBR0 table 88 * x26 = Kernel L1 table 89 * x24 = TTBR1 table 90 */ 91 92 /* Enable the mmu */ 93 bl start_mmu 94 95 /* Load the new ttbr0 pagetable */ 96 adrp x27, pagetable_l0_ttbr0 97 add x27, x27, :lo12:pagetable_l0_ttbr0 98 99 /* Jump to the virtual address space */ 100 ldr x15, .Lvirtdone 101 br x15 102 103virtdone: 104 /* Set up the stack */ 105 adrp x25, initstack_end 106 add x25, x25, :lo12:initstack_end 107 mov sp, x25 108 sub sp, sp, #PCB_SIZE 109 110 /* Zero the BSS */ 111 ldr x15, .Lbss 112 ldr x14, .Lend 1131: 114 str xzr, [x15], #8 115 cmp x15, x14 116 b.lo 1b 117 118#if defined(PERTHREAD_SSP) 119 /* Set sp_el0 to the boot canary for early per-thread SSP to work */ 120 adrp x15, boot_canary 121 add x15, x15, :lo12:boot_canary 122 msr sp_el0, x15 123#endif 124 125 /* Backup the module pointer */ 126 mov x1, x0 127 128 /* Make the page table base a virtual address */ 129 sub x26, x26, x29 130 sub x24, x24, x29 131 132 sub sp, sp, #BOOTPARAMS_SIZE 133 mov x0, sp 134 135 /* Degate the delda so it is VA -> PA */ 136 neg x29, x29 137 138 str x1, [x0, #BP_MODULEP] 139 str x26, [x0, #BP_KERN_L1PT] 140 str x29, [x0, #BP_KERN_DELTA] 141 adrp x25, initstack 142 add x25, x25, :lo12:initstack 143 str x25, [x0, #BP_KERN_STACK] 144 str x24, [x0, #BP_KERN_L0PT] 145 str x27, [x0, #BP_KERN_TTBR0] 146 str x23, [x0, #BP_BOOT_EL] 147 148 /* trace back starts here */ 149 mov fp, #0 150 /* Branch to C code */ 151 bl initarm 152 /* We are done with the boot params */ 153 add sp, sp, #BOOTPARAMS_SIZE 154 155 /* 156 * Enable pointer authentication in the kernel. We set the keys for 157 * thread0 in initarm so have to wait until it returns to enable it. 158 * If we were to enable it in initarm then any authentication when 159 * returning would fail as it was called with pointer authentication 160 * disabled. 161 */ 162 bl ptrauth_start 163 164 bl mi_startup 165 166 /* We should not get here */ 167 brk 0 168 169 .align 3 170.Lvirtdone: 171 .quad virtdone 172.Lbss: 173 .quad __bss_start 174.Lend: 175 .quad __bss_end 176END(_start) 177 178#ifdef SMP 179/* 180 * mpentry(unsigned long) 181 * 182 * Called by a core when it is being brought online. 183 * The data in x0 is passed straight to init_secondary. 184 */ 185ENTRY(mpentry) 186 /* Disable interrupts */ 187 msr daifset, #DAIF_INTR 188 189 /* Drop to EL1 */ 190 bl drop_to_el1 191 192 /* Set the context id */ 193 msr contextidr_el1, xzr 194 195 /* Load the kernel page table */ 196 adrp x24, pagetable_l0_ttbr1 197 add x24, x24, :lo12:pagetable_l0_ttbr1 198 /* Load the identity page table */ 199 adrp x27, pagetable_l0_ttbr0_boostrap 200 add x27, x27, :lo12:pagetable_l0_ttbr0_boostrap 201 202 /* Enable the mmu */ 203 bl start_mmu 204 205 /* Load the new ttbr0 pagetable */ 206 adrp x27, pagetable_l0_ttbr0 207 add x27, x27, :lo12:pagetable_l0_ttbr0 208 209 /* Jump to the virtual address space */ 210 ldr x15, =mp_virtdone 211 br x15 212 213mp_virtdone: 214 /* Start using the AP boot stack */ 215 ldr x4, =bootstack 216 ldr x4, [x4] 217 mov sp, x4 218 219#if defined(PERTHREAD_SSP) 220 /* Set sp_el0 to the boot canary for early per-thread SSP to work */ 221 adrp x15, boot_canary 222 add x15, x15, :lo12:boot_canary 223 msr sp_el0, x15 224#endif 225 226 /* Load the kernel ttbr0 pagetable */ 227 msr ttbr0_el1, x27 228 isb 229 230 /* Invalidate the TLB */ 231 tlbi vmalle1 232 dsb sy 233 isb 234 235 b init_secondary 236END(mpentry) 237#endif 238 239/* 240 * If we are started in EL2, configure the required hypervisor 241 * registers and drop to EL1. 242 */ 243LENTRY(drop_to_el1) 244 mrs x23, CurrentEL 245 lsr x23, x23, #2 246 cmp x23, #0x2 247 b.eq 1f 248 ret 2491: 250 /* 251 * Disable the MMU. If the HCR_EL2.E2H field is set we will clear it 252 * which may break address translation. 253 */ 254 dsb sy 255 mrs x2, sctlr_el2 256 bic x2, x2, SCTLR_M 257 msr sctlr_el2, x2 258 isb 259 260 /* Configure the Hypervisor */ 261 ldr x2, =(HCR_RW | HCR_APK | HCR_API) 262 msr hcr_el2, x2 263 264 /* Load the Virtualization Process ID Register */ 265 mrs x2, midr_el1 266 msr vpidr_el2, x2 267 268 /* Load the Virtualization Multiprocess ID Register */ 269 mrs x2, mpidr_el1 270 msr vmpidr_el2, x2 271 272 /* Set the bits that need to be 1 in sctlr_el1 */ 273 ldr x2, .Lsctlr_res1 274 msr sctlr_el1, x2 275 276 /* Don't trap to EL2 for exceptions */ 277 mov x2, #CPTR_RES1 278 msr cptr_el2, x2 279 280 /* Don't trap to EL2 for CP15 traps */ 281 msr hstr_el2, xzr 282 283 /* Enable access to the physical timers at EL1 */ 284 mrs x2, cnthctl_el2 285 orr x2, x2, #(CNTHCTL_EL1PCTEN | CNTHCTL_EL1PCEN) 286 msr cnthctl_el2, x2 287 288 /* Set the counter offset to a known value */ 289 msr cntvoff_el2, xzr 290 291 /* Hypervisor trap functions */ 292 adrp x2, hyp_vectors 293 add x2, x2, :lo12:hyp_vectors 294 msr vbar_el2, x2 295 296 mov x2, #(PSR_F | PSR_I | PSR_A | PSR_D | PSR_M_EL1h) 297 msr spsr_el2, x2 298 299 /* Configure GICv3 CPU interface */ 300 mrs x2, id_aa64pfr0_el1 301 /* Extract GIC bits from the register */ 302 ubfx x2, x2, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_BITS 303 /* GIC[3:0] == 0001 - GIC CPU interface via special regs. supported */ 304 cmp x2, #(ID_AA64PFR0_GIC_CPUIF_EN >> ID_AA64PFR0_GIC_SHIFT) 305 b.ne 2f 306 307 mrs x2, icc_sre_el2 308 orr x2, x2, #ICC_SRE_EL2_EN /* Enable access from insecure EL1 */ 309 orr x2, x2, #ICC_SRE_EL2_SRE /* Enable system registers */ 310 msr icc_sre_el2, x2 3112: 312 313 /* Set the address to return to our return address */ 314 msr elr_el2, x30 315 isb 316 317 eret 318 319 .align 3 320.Lsctlr_res1: 321 .quad SCTLR_RES1 322LEND(drop_to_el1) 323 324#define VECT_EMPTY \ 325 .align 7; \ 326 1: b 1b 327 328 .align 11 329hyp_vectors: 330 VECT_EMPTY /* Synchronous EL2t */ 331 VECT_EMPTY /* IRQ EL2t */ 332 VECT_EMPTY /* FIQ EL2t */ 333 VECT_EMPTY /* Error EL2t */ 334 335 VECT_EMPTY /* Synchronous EL2h */ 336 VECT_EMPTY /* IRQ EL2h */ 337 VECT_EMPTY /* FIQ EL2h */ 338 VECT_EMPTY /* Error EL2h */ 339 340 VECT_EMPTY /* Synchronous 64-bit EL1 */ 341 VECT_EMPTY /* IRQ 64-bit EL1 */ 342 VECT_EMPTY /* FIQ 64-bit EL1 */ 343 VECT_EMPTY /* Error 64-bit EL1 */ 344 345 VECT_EMPTY /* Synchronous 32-bit EL1 */ 346 VECT_EMPTY /* IRQ 32-bit EL1 */ 347 VECT_EMPTY /* FIQ 32-bit EL1 */ 348 VECT_EMPTY /* Error 32-bit EL1 */ 349 350/* 351 * Get the delta between the physical address we were loaded to and the 352 * virtual address we expect to run from. This is used when building the 353 * initial page table. 354 */ 355LENTRY(get_virt_delta) 356 /* Load the physical address of virt_map */ 357 adrp x29, virt_map 358 add x29, x29, :lo12:virt_map 359 /* Load the virtual address of virt_map stored in virt_map */ 360 ldr x28, [x29] 361 /* Find PA - VA as PA' = VA' - VA + PA = VA' + (PA - VA) = VA' + x29 */ 362 sub x29, x29, x28 363 /* Find the load address for the kernel */ 364 mov x28, #(KERNBASE) 365 add x28, x28, x29 366 ret 367 368 .align 3 369virt_map: 370 .quad virt_map 371LEND(get_virt_delta) 372 373/* 374 * This builds the page tables containing the identity map, and the kernel 375 * virtual map. 376 * 377 * It relys on: 378 * We were loaded to an address that is on a 2MiB boundary 379 * All the memory must not cross a 1GiB boundaty 380 * x28 contains the physical address we were loaded from 381 * 382 * TODO: This is out of date. 383 * There are at least 5 pages before that address for the page tables 384 * The pages used are: 385 * - The Kernel L2 table 386 * - The Kernel L1 table 387 * - The Kernel L0 table (TTBR1) 388 * - The identity (PA = VA) L1 table 389 * - The identity (PA = VA) L0 table (TTBR0) 390 */ 391LENTRY(create_pagetables) 392 /* Save the Link register */ 393 mov x5, x30 394 395 /* Clean the page table */ 396 adrp x6, pagetable 397 add x6, x6, :lo12:pagetable 398 mov x26, x6 399 adrp x27, pagetable_end 400 add x27, x27, :lo12:pagetable_end 4011: 402 stp xzr, xzr, [x6], #16 403 stp xzr, xzr, [x6], #16 404 stp xzr, xzr, [x6], #16 405 stp xzr, xzr, [x6], #16 406 cmp x6, x27 407 b.lo 1b 408 409 /* 410 * Build the TTBR1 maps. 411 */ 412 413 /* Find the size of the kernel */ 414 mov x6, #(KERNBASE) 415 416#if defined(LINUX_BOOT_ABI) 417 /* X19 is used as 'map FDT data' flag */ 418 mov x19, xzr 419 420 /* No modules or FDT pointer ? */ 421 cbz x0, booti_no_fdt 422 423 /* 424 * Test if x0 points to modules descriptor(virtual address) or 425 * to FDT (physical address) 426 */ 427 cmp x0, x6 /* x6 is #(KERNBASE) */ 428 b.lo booti_fdt 429#endif 430 431 /* Booted with modules pointer */ 432 /* Find modulep - begin */ 433 sub x8, x0, x6 434 /* Add two 2MiB pages for the module data and round up */ 435 ldr x7, =(3 * L2_SIZE - 1) 436 add x8, x8, x7 437 b common 438 439#if defined(LINUX_BOOT_ABI) 440booti_fdt: 441 /* Booted by U-Boot booti with FDT data */ 442 /* Set 'map FDT data' flag */ 443 mov x19, #1 444 445booti_no_fdt: 446 /* Booted by U-Boot booti without FTD data */ 447 /* Find the end - begin */ 448 ldr x7, .Lend 449 sub x8, x7, x6 450 451 /* 452 * Add one 2MiB page for copy of FDT data (maximum FDT size), 453 * one for metadata and round up 454 */ 455 ldr x7, =(3 * L2_SIZE - 1) 456 add x8, x8, x7 457#endif 458 459common: 460 /* Get the number of l2 pages to allocate, rounded down */ 461 lsr x10, x8, #(L2_SHIFT) 462 463 /* Create the kernel space L2 table */ 464 mov x6, x26 465 mov x7, #(ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK)) 466 mov x8, #(KERNBASE) 467 mov x9, x28 468 bl build_l2_block_pagetable 469 470 /* Move to the l1 table */ 471 add x26, x26, #PAGE_SIZE 472 473 /* Link the l1 -> l2 table */ 474 mov x9, x6 475 mov x6, x26 476 bl link_l1_pagetable 477 478 /* Move to the l0 table */ 479 add x24, x26, #PAGE_SIZE 480 481 /* Link the l0 -> l1 table */ 482 mov x9, x6 483 mov x6, x24 484 mov x10, #1 485 bl link_l0_pagetable 486 487 /* 488 * Build the TTBR0 maps. As TTBR0 maps, they must specify ATTR_S1_nG. 489 * They are only needed early on, so the VA = PA map is uncached. 490 */ 491 add x27, x24, #PAGE_SIZE 492 493 mov x6, x27 /* The initial page table */ 494 495 /* Create the VA = PA map */ 496 mov x7, #(ATTR_S1_nG | ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK)) 497 adrp x16, _start 498 and x16, x16, #(~L2_OFFSET) 499 mov x9, x16 /* PA start */ 500 mov x8, x16 /* VA start (== PA start) */ 501 mov x10, #1 502 bl build_l2_block_pagetable 503 504#if defined(SOCDEV_PA) 505 /* Create a table for the UART */ 506 mov x7, #(ATTR_S1_nG | ATTR_S1_IDX(VM_MEMATTR_DEVICE)) 507 add x16, x16, #(L2_SIZE) /* VA start */ 508 mov x8, x16 509 510 /* Store the socdev virtual address */ 511 add x17, x8, #(SOCDEV_PA & L2_OFFSET) 512 adrp x9, socdev_va 513 str x17, [x9, :lo12:socdev_va] 514 515 mov x9, #(SOCDEV_PA & ~L2_OFFSET) /* PA start */ 516 mov x10, #1 517 bl build_l2_block_pagetable 518#endif 519 520#if defined(LINUX_BOOT_ABI) 521 /* Map FDT data ? */ 522 cbz x19, 1f 523 524 /* Create the mapping for FDT data (2 MiB max) */ 525 mov x7, #(ATTR_S1_nG | ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK)) 526 add x16, x16, #(L2_SIZE) /* VA start */ 527 mov x8, x16 528 mov x9, x0 /* PA start */ 529 /* Update the module pointer to point at the allocated memory */ 530 and x0, x0, #(L2_OFFSET) /* Keep the lower bits */ 531 add x0, x0, x8 /* Add the aligned virtual address */ 532 533 mov x10, #1 534 bl build_l2_block_pagetable 535 5361: 537#endif 538 539 /* Move to the l1 table */ 540 add x27, x27, #PAGE_SIZE 541 542 /* Link the l1 -> l2 table */ 543 mov x9, x6 544 mov x6, x27 545 bl link_l1_pagetable 546 547 /* Move to the l0 table */ 548 add x27, x27, #PAGE_SIZE 549 550 /* Link the l0 -> l1 table */ 551 mov x9, x6 552 mov x6, x27 553 mov x10, #1 554 bl link_l0_pagetable 555 556 /* Restore the Link register */ 557 mov x30, x5 558 ret 559LEND(create_pagetables) 560 561/* 562 * Builds an L0 -> L1 table descriptor 563 * 564 * x6 = L0 table 565 * x8 = Virtual Address 566 * x9 = L1 PA (trashed) 567 * x10 = Entry count (trashed) 568 * x11, x12 and x13 are trashed 569 */ 570LENTRY(link_l0_pagetable) 571 /* 572 * Link an L0 -> L1 table entry. 573 */ 574 /* Find the table index */ 575 lsr x11, x8, #L0_SHIFT 576 and x11, x11, #L0_ADDR_MASK 577 578 /* Build the L0 block entry */ 579 mov x12, #L0_TABLE 580 orr x12, x12, #(TATTR_UXN_TABLE | TATTR_AP_TABLE_NO_EL0) 581 582 /* Only use the output address bits */ 583 lsr x9, x9, #PAGE_SHIFT 5841: orr x13, x12, x9, lsl #PAGE_SHIFT 585 586 /* Store the entry */ 587 str x13, [x6, x11, lsl #3] 588 589 sub x10, x10, #1 590 add x11, x11, #1 591 add x9, x9, #1 592 cbnz x10, 1b 593 594 ret 595LEND(link_l0_pagetable) 596 597/* 598 * Builds an L1 -> L2 table descriptor 599 * 600 * x6 = L1 table 601 * x8 = Virtual Address 602 * x9 = L2 PA (trashed) 603 * x11, x12 and x13 are trashed 604 */ 605LENTRY(link_l1_pagetable) 606 /* 607 * Link an L1 -> L2 table entry. 608 */ 609 /* Find the table index */ 610 lsr x11, x8, #L1_SHIFT 611 and x11, x11, #Ln_ADDR_MASK 612 613 /* Build the L1 block entry */ 614 mov x12, #L1_TABLE 615 616 /* Only use the output address bits */ 617 lsr x9, x9, #PAGE_SHIFT 618 orr x13, x12, x9, lsl #PAGE_SHIFT 619 620 /* Store the entry */ 621 str x13, [x6, x11, lsl #3] 622 623 ret 624LEND(link_l1_pagetable) 625 626/* 627 * Builds count 2 MiB page table entry 628 * x6 = L2 table 629 * x7 = Block attributes 630 * x8 = VA start 631 * x9 = PA start (trashed) 632 * x10 = Entry count (trashed) 633 * x11, x12 and x13 are trashed 634 */ 635LENTRY(build_l2_block_pagetable) 636 /* 637 * Build the L2 table entry. 638 */ 639 /* Find the table index */ 640 lsr x11, x8, #L2_SHIFT 641 and x11, x11, #Ln_ADDR_MASK 642 643 /* Build the L2 block entry */ 644 orr x12, x7, #L2_BLOCK 645 orr x12, x12, #(ATTR_DEFAULT) 646 orr x12, x12, #(ATTR_S1_UXN) 647 648 /* Only use the output address bits */ 649 lsr x9, x9, #L2_SHIFT 650 651 /* Set the physical address for this virtual address */ 6521: orr x13, x12, x9, lsl #L2_SHIFT 653 654 /* Store the entry */ 655 str x13, [x6, x11, lsl #3] 656 657 sub x10, x10, #1 658 add x11, x11, #1 659 add x9, x9, #1 660 cbnz x10, 1b 661 662 ret 663LEND(build_l2_block_pagetable) 664 665LENTRY(start_mmu) 666 dsb sy 667 668 /* Load the exception vectors */ 669 ldr x2, =exception_vectors 670 msr vbar_el1, x2 671 672 /* Load ttbr0 and ttbr1 */ 673 msr ttbr0_el1, x27 674 msr ttbr1_el1, x24 675 isb 676 677 /* Clear the Monitor Debug System control register */ 678 msr mdscr_el1, xzr 679 680 /* Invalidate the TLB */ 681 tlbi vmalle1is 682 dsb ish 683 isb 684 685 ldr x2, mair 686 msr mair_el1, x2 687 688 /* 689 * Setup TCR according to the PARange and ASIDBits fields 690 * from ID_AA64MMFR0_EL1 and the HAFDBS field from the 691 * ID_AA64MMFR1_EL1. More precisely, set TCR_EL1.AS 692 * to 1 only if the ASIDBits field equals 0b0010. 693 */ 694 ldr x2, tcr 695 mrs x3, id_aa64mmfr0_el1 696 697 /* Copy the bottom 3 bits from id_aa64mmfr0_el1 into TCR.IPS */ 698 bfi x2, x3, #(TCR_IPS_SHIFT), #(TCR_IPS_WIDTH) 699 and x3, x3, #(ID_AA64MMFR0_ASIDBits_MASK) 700 701 /* Check if the HW supports 16 bit ASIDS */ 702 cmp x3, #(ID_AA64MMFR0_ASIDBits_16) 703 /* If so x3 == 1, else x3 == 0 */ 704 cset x3, eq 705 /* Set TCR.AS with x3 */ 706 bfi x2, x3, #(TCR_ASID_SHIFT), #(TCR_ASID_WIDTH) 707 708 /* 709 * Check if the HW supports access flag and dirty state updates, 710 * and set TCR_EL1.HA and TCR_EL1.HD accordingly. 711 */ 712 mrs x3, id_aa64mmfr1_el1 713 and x3, x3, #(ID_AA64MMFR1_HAFDBS_MASK) 714 cmp x3, #1 715 b.ne 1f 716 orr x2, x2, #(TCR_HA) 717 b 2f 7181: 719 cmp x3, #2 720 b.ne 2f 721 orr x2, x2, #(TCR_HA | TCR_HD) 7222: 723 msr tcr_el1, x2 724 725 /* 726 * Setup SCTLR. 727 */ 728 ldr x2, sctlr_set 729 ldr x3, sctlr_clear 730 mrs x1, sctlr_el1 731 bic x1, x1, x3 /* Clear the required bits */ 732 orr x1, x1, x2 /* Set the required bits */ 733 msr sctlr_el1, x1 734 isb 735 736 ret 737 738 .align 3 739mair: 740 .quad MAIR_ATTR(MAIR_DEVICE_nGnRnE, VM_MEMATTR_DEVICE_nGnRnE) | \ 741 MAIR_ATTR(MAIR_NORMAL_NC, VM_MEMATTR_UNCACHEABLE) | \ 742 MAIR_ATTR(MAIR_NORMAL_WB, VM_MEMATTR_WRITE_BACK) | \ 743 MAIR_ATTR(MAIR_NORMAL_WT, VM_MEMATTR_WRITE_THROUGH) | \ 744 MAIR_ATTR(MAIR_DEVICE_nGnRE, VM_MEMATTR_DEVICE_nGnRE) 745tcr: 746 .quad (TCR_TxSZ(64 - VIRT_BITS) | TCR_TG1_4K | TCR_TG0_4K | \ 747 TCR_CACHE_ATTRS | TCR_SMP_ATTRS) 748sctlr_set: 749 /* Bits to set */ 750 .quad (SCTLR_LSMAOE | SCTLR_nTLSMD | SCTLR_UCI | SCTLR_SPAN | \ 751 SCTLR_nTWE | SCTLR_nTWI | SCTLR_UCT | SCTLR_DZE | \ 752 SCTLR_I | SCTLR_SED | SCTLR_SA0 | SCTLR_SA | SCTLR_C | \ 753 SCTLR_M | SCTLR_CP15BEN) 754sctlr_clear: 755 /* Bits to clear */ 756 .quad (SCTLR_EE | SCTLR_E0E | SCTLR_IESB | SCTLR_WXN | SCTLR_UMA | \ 757 SCTLR_ITD | SCTLR_A) 758LEND(start_mmu) 759 760ENTRY(abort) 761 b abort 762END(abort) 763 764 .section .init_pagetable, "aw", %nobits 765 .align PAGE_SHIFT 766 /* 767 * 6 initial tables (in the following order): 768 * L2 for kernel (High addresses) 769 * L1 for kernel 770 * L0 for kernel 771 * L1 bootstrap for user (Low addresses) 772 * L0 bootstrap for user 773 * L0 for user 774 */ 775 .globl pagetable_l0_ttbr1 776pagetable: 777 .space PAGE_SIZE 778pagetable_l1_ttbr1: 779 .space PAGE_SIZE 780pagetable_l0_ttbr1: 781 .space PAGE_SIZE 782pagetable_l2_ttbr0_bootstrap: 783 .space PAGE_SIZE 784pagetable_l1_ttbr0_bootstrap: 785 .space PAGE_SIZE 786pagetable_l0_ttbr0_boostrap: 787 .space PAGE_SIZE 788pagetable_l0_ttbr0: 789 .space PAGE_SIZE 790 791pagetable_end: 792 793el2_pagetable: 794 .space PAGE_SIZE 795 796 .align 4 797initstack: 798 .space (PAGE_SIZE * KSTACK_PAGES) 799initstack_end: 800 801 802.text 803EENTRY(aarch32_sigcode) 804 .word 0xe1a0000d // mov r0, sp 805 .word 0xe2800040 // add r0, r0, #SIGF_UC 806 .word 0xe59f700c // ldr r7, [pc, #12] 807 .word 0xef000000 // swi #0 808 .word 0xe59f7008 // ldr r7, [pc, #8] 809 .word 0xef000000 // swi #0 810 .word 0xeafffffa // b . - 16 811EEND(aarch32_sigcode) 812 .word SYS_sigreturn 813 .word SYS_exit 814 .align 3 815aarch32_esigcode: 816 .data 817 .global sz_aarch32_sigcode 818sz_aarch32_sigcode: 819 .quad aarch32_esigcode - aarch32_sigcode 820