1/*- 2 * Copyright (c) 2012-2014 Andrew Turner 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29#include "assym.inc" 30#include "opt_kstack_pages.h" 31#include <sys/syscall.h> 32#include <machine/asm.h> 33#include <machine/armreg.h> 34#include <machine/hypervisor.h> 35#include <machine/param.h> 36#include <machine/pte.h> 37#include <machine/vm.h> 38#include <machine/vmparam.h> 39 40#define VIRT_BITS 48 41#define DMAP_TABLES ((DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS) >> L0_SHIFT) 42 43 .globl kernbase 44 .set kernbase, KERNBASE 45 46 47/* U-Boot booti related constants. */ 48#if defined(LINUX_BOOT_ABI) 49#ifndef UBOOT_IMAGE_OFFSET 50#define UBOOT_IMAGE_OFFSET 0 /* Image offset from start of */ 51#endif /* 2 MiB page */ 52 53#ifndef UBOOT_IMAGE_SIZE /* Total size of image */ 54#define UBOOT_IMAGE_SIZE _end - _start 55#endif 56 57#ifndef UBOOT_IMAGE_FLAGS 58#define UBOOT_IMAGE_FLAGS 0 /* LE kernel, unspecified */ 59#endif /* page size */ 60#endif /* defined(LINUX_BOOT_ABI) */ 61 62/* 63 * We assume: 64 * MMU on with an identity map, or off 65 * D-Cache: off 66 * I-Cache: on or off 67 * We are loaded at a 2MiB aligned address 68 */ 69 70 .text 71 .globl _start 72_start: 73#if defined(LINUX_BOOT_ABI) 74 /* U-boot image header */ 75 b 1f /* code 0 */ 76 .long 0 /* code 1 */ 77 .quad UBOOT_IMAGE_OFFSET /* Image offset in 2 MiB page, LE */ 78 .quad UBOOT_IMAGE_SIZE /* Image size, LE */ 79 .quad UBOOT_IMAGE_FLAGS /* Flags for kernel. LE */ 80 .quad 0 /* Reserved */ 81 .quad 0 /* Reserved */ 82 .quad 0 /* Reserved */ 83 .long 0x644d5241 /* Magic "ARM\x64", LE */ 84 .long 0 /* Reserved for PE COFF offset*/ 851: 86#endif /* defined(LINUX_BOOT_ABI) */ 87 88 /* Drop to EL1 */ 89 bl drop_to_el1 90 91 /* 92 * Disable the MMU. We may have entered the kernel with it on and 93 * will need to update the tables later. If this has been set up 94 * with anything other than a VA == PA map then this will fail, 95 * but in this case the code to find where we are running from 96 * would have also failed. 97 */ 98 dsb sy 99 mrs x2, sctlr_el1 100 bic x2, x2, SCTLR_M 101 msr sctlr_el1, x2 102 isb 103 104 /* Set the context id */ 105 msr contextidr_el1, xzr 106 107 /* Get the virt -> phys offset */ 108 bl get_virt_delta 109 110 /* 111 * At this point: 112 * x29 = PA - VA 113 * x28 = Our physical load address 114 */ 115 116 /* Create the page tables */ 117 bl create_pagetables 118 119 /* 120 * At this point: 121 * x27 = TTBR0 table 122 * x26 = Kernel L1 table 123 * x24 = TTBR1 table 124 */ 125 126 /* Enable the mmu */ 127 bl start_mmu 128 129 /* Load the new ttbr0 pagetable */ 130 adr x27, pagetable_l0_ttbr0 131 132 /* Jump to the virtual address space */ 133 ldr x15, .Lvirtdone 134 br x15 135 136virtdone: 137 /* Set up the stack */ 138 adr x25, initstack_end 139 mov sp, x25 140 sub sp, sp, #PCB_SIZE 141 142 /* Zero the BSS */ 143 ldr x15, .Lbss 144 ldr x14, .Lend 1451: 146 str xzr, [x15], #8 147 cmp x15, x14 148 b.lo 1b 149 150 /* Backup the module pointer */ 151 mov x1, x0 152 153 /* Make the page table base a virtual address */ 154 sub x26, x26, x29 155 sub x24, x24, x29 156 157 sub sp, sp, #BOOTPARAMS_SIZE 158 mov x0, sp 159 160 /* Degate the delda so it is VA -> PA */ 161 neg x29, x29 162 163 str x1, [x0, #BP_MODULEP] 164 str x26, [x0, #BP_KERN_L1PT] 165 str x29, [x0, #BP_KERN_DELTA] 166 adr x25, initstack 167 str x25, [x0, #BP_KERN_STACK] 168 str x24, [x0, #BP_KERN_L0PT] 169 str x23, [x0, #BP_BOOT_EL] 170 str x27, [x0, 40] /* kern_ttbr0 */ 171 172 /* trace back starts here */ 173 mov fp, #0 174 /* Branch to C code */ 175 bl initarm 176 bl mi_startup 177 178 /* We should not get here */ 179 brk 0 180 181 .align 3 182.Lvirtdone: 183 .quad virtdone 184.Lbss: 185 .quad __bss_start 186.Lend: 187 .quad _end 188 189#ifdef SMP 190/* 191 * mpentry(unsigned long) 192 * 193 * Called by a core when it is being brought online. 194 * The data in x0 is passed straight to init_secondary. 195 */ 196ENTRY(mpentry) 197 /* Disable interrupts */ 198 msr daifset, #2 199 200 /* Drop to EL1 */ 201 bl drop_to_el1 202 203 /* Set the context id */ 204 msr contextidr_el1, xzr 205 206 /* Load the kernel page table */ 207 adr x24, pagetable_l0_ttbr1 208 /* Load the identity page table */ 209 adr x27, pagetable_l0_ttbr0_boostrap 210 211 /* Enable the mmu */ 212 bl start_mmu 213 214 /* Load the new ttbr0 pagetable */ 215 adr x27, pagetable_l0_ttbr0 216 217 /* Jump to the virtual address space */ 218 ldr x15, =mp_virtdone 219 br x15 220 221mp_virtdone: 222 /* Start using the AP boot stack */ 223 ldr x4, =bootstack 224 ldr x4, [x4] 225 mov sp, x4 226 227 /* Load the kernel ttbr0 pagetable */ 228 msr ttbr0_el1, x27 229 isb 230 231 /* Invalidate the TLB */ 232 tlbi vmalle1 233 dsb sy 234 isb 235 236 b init_secondary 237END(mpentry) 238#endif 239 240/* 241 * If we are started in EL2, configure the required hypervisor 242 * registers and drop to EL1. 243 */ 244drop_to_el1: 245 mrs x23, CurrentEL 246 lsr x23, x23, #2 247 cmp x23, #0x2 248 b.eq 1f 249 ret 2501: 251 /* Configure the Hypervisor */ 252 mov x2, #(HCR_RW) 253 msr hcr_el2, x2 254 255 /* Load the Virtualization Process ID Register */ 256 mrs x2, midr_el1 257 msr vpidr_el2, x2 258 259 /* Load the Virtualization Multiprocess ID Register */ 260 mrs x2, mpidr_el1 261 msr vmpidr_el2, x2 262 263 /* Set the bits that need to be 1 in sctlr_el1 */ 264 ldr x2, .Lsctlr_res1 265 msr sctlr_el1, x2 266 267 /* Don't trap to EL2 for exceptions */ 268 mov x2, #CPTR_RES1 269 msr cptr_el2, x2 270 271 /* Don't trap to EL2 for CP15 traps */ 272 msr hstr_el2, xzr 273 274 /* Enable access to the physical timers at EL1 */ 275 mrs x2, cnthctl_el2 276 orr x2, x2, #(CNTHCTL_EL1PCTEN | CNTHCTL_EL1PCEN) 277 msr cnthctl_el2, x2 278 279 /* Set the counter offset to a known value */ 280 msr cntvoff_el2, xzr 281 282 /* Hypervisor trap functions */ 283 adr x2, hyp_vectors 284 msr vbar_el2, x2 285 286 mov x2, #(PSR_F | PSR_I | PSR_A | PSR_D | PSR_M_EL1h) 287 msr spsr_el2, x2 288 289 /* Configure GICv3 CPU interface */ 290 mrs x2, id_aa64pfr0_el1 291 /* Extract GIC bits from the register */ 292 ubfx x2, x2, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_BITS 293 /* GIC[3:0] == 0001 - GIC CPU interface via special regs. supported */ 294 cmp x2, #(ID_AA64PFR0_GIC_CPUIF_EN >> ID_AA64PFR0_GIC_SHIFT) 295 b.ne 2f 296 297 mrs x2, icc_sre_el2 298 orr x2, x2, #ICC_SRE_EL2_EN /* Enable access from insecure EL1 */ 299 orr x2, x2, #ICC_SRE_EL2_SRE /* Enable system registers */ 300 msr icc_sre_el2, x2 3012: 302 303 /* Set the address to return to our return address */ 304 msr elr_el2, x30 305 isb 306 307 eret 308 309 .align 3 310.Lsctlr_res1: 311 .quad SCTLR_RES1 312 313#define VECT_EMPTY \ 314 .align 7; \ 315 1: b 1b 316 317 .align 11 318hyp_vectors: 319 VECT_EMPTY /* Synchronous EL2t */ 320 VECT_EMPTY /* IRQ EL2t */ 321 VECT_EMPTY /* FIQ EL2t */ 322 VECT_EMPTY /* Error EL2t */ 323 324 VECT_EMPTY /* Synchronous EL2h */ 325 VECT_EMPTY /* IRQ EL2h */ 326 VECT_EMPTY /* FIQ EL2h */ 327 VECT_EMPTY /* Error EL2h */ 328 329 VECT_EMPTY /* Synchronous 64-bit EL1 */ 330 VECT_EMPTY /* IRQ 64-bit EL1 */ 331 VECT_EMPTY /* FIQ 64-bit EL1 */ 332 VECT_EMPTY /* Error 64-bit EL1 */ 333 334 VECT_EMPTY /* Synchronous 32-bit EL1 */ 335 VECT_EMPTY /* IRQ 32-bit EL1 */ 336 VECT_EMPTY /* FIQ 32-bit EL1 */ 337 VECT_EMPTY /* Error 32-bit EL1 */ 338 339/* 340 * Get the delta between the physical address we were loaded to and the 341 * virtual address we expect to run from. This is used when building the 342 * initial page table. 343 */ 344get_virt_delta: 345 /* Load the physical address of virt_map */ 346 adr x29, virt_map 347 /* Load the virtual address of virt_map stored in virt_map */ 348 ldr x28, [x29] 349 /* Find PA - VA as PA' = VA' - VA + PA = VA' + (PA - VA) = VA' + x29 */ 350 sub x29, x29, x28 351 /* Find the load address for the kernel */ 352 mov x28, #(KERNBASE) 353 add x28, x28, x29 354 ret 355 356 .align 3 357virt_map: 358 .quad virt_map 359 360/* 361 * This builds the page tables containing the identity map, and the kernel 362 * virtual map. 363 * 364 * It relys on: 365 * We were loaded to an address that is on a 2MiB boundary 366 * All the memory must not cross a 1GiB boundaty 367 * x28 contains the physical address we were loaded from 368 * 369 * TODO: This is out of date. 370 * There are at least 5 pages before that address for the page tables 371 * The pages used are: 372 * - The Kernel L2 table 373 * - The Kernel L1 table 374 * - The Kernel L0 table (TTBR1) 375 * - The identity (PA = VA) L1 table 376 * - The identity (PA = VA) L0 table (TTBR0) 377 * - The DMAP L1 tables 378 */ 379create_pagetables: 380 /* Save the Link register */ 381 mov x5, x30 382 383 /* Clean the page table */ 384 adr x6, pagetable 385 mov x26, x6 386 adr x27, pagetable_end 3871: 388 stp xzr, xzr, [x6], #16 389 stp xzr, xzr, [x6], #16 390 stp xzr, xzr, [x6], #16 391 stp xzr, xzr, [x6], #16 392 cmp x6, x27 393 b.lo 1b 394 395 /* 396 * Build the TTBR1 maps. 397 */ 398 399 /* Find the size of the kernel */ 400 mov x6, #(KERNBASE) 401 402#if defined(LINUX_BOOT_ABI) 403 /* X19 is used as 'map FDT data' flag */ 404 mov x19, xzr 405 406 /* No modules or FDT pointer ? */ 407 cbz x0, booti_no_fdt 408 409 /* 410 * Test if x0 points to modules descriptor(virtual address) or 411 * to FDT (physical address) 412 */ 413 cmp x0, x6 /* x6 is #(KERNBASE) */ 414 b.lo booti_fdt 415#endif 416 417 /* Booted with modules pointer */ 418 /* Find modulep - begin */ 419 sub x8, x0, x6 420 /* Add two 2MiB pages for the module data and round up */ 421 ldr x7, =(3 * L2_SIZE - 1) 422 add x8, x8, x7 423 b common 424 425#if defined(LINUX_BOOT_ABI) 426booti_fdt: 427 /* Booted by U-Boot booti with FDT data */ 428 /* Set 'map FDT data' flag */ 429 mov x19, #1 430 431booti_no_fdt: 432 /* Booted by U-Boot booti without FTD data */ 433 /* Find the end - begin */ 434 ldr x7, .Lend 435 sub x8, x7, x6 436 437 /* 438 * Add one 2MiB page for copy of FDT data (maximum FDT size), 439 * one for metadata and round up 440 */ 441 ldr x7, =(3 * L2_SIZE - 1) 442 add x8, x8, x7 443#endif 444 445common: 446 /* Get the number of l2 pages to allocate, rounded down */ 447 lsr x10, x8, #(L2_SHIFT) 448 449 /* Create the kernel space L2 table */ 450 mov x6, x26 451 mov x7, #VM_MEMATTR_WRITE_BACK 452 mov x8, #(KERNBASE & L2_BLOCK_MASK) 453 mov x9, x28 454 bl build_l2_block_pagetable 455 456 /* Move to the l1 table */ 457 add x26, x26, #PAGE_SIZE 458 459 /* Link the l1 -> l2 table */ 460 mov x9, x6 461 mov x6, x26 462 bl link_l1_pagetable 463 464 /* Move to the l0 table */ 465 add x24, x26, #PAGE_SIZE 466 467 /* Link the l0 -> l1 table */ 468 mov x9, x6 469 mov x6, x24 470 mov x10, #1 471 bl link_l0_pagetable 472 473 /* Link the DMAP tables */ 474 ldr x8, =DMAP_MIN_ADDRESS 475 adr x9, pagetable_dmap; 476 mov x10, #DMAP_TABLES 477 bl link_l0_pagetable 478 479 /* 480 * Build the TTBR0 maps. As TTBR0 maps, they must specify ATTR_S1_nG. 481 * They are only needed early on, so the VA = PA map is uncached. 482 */ 483 add x27, x24, #PAGE_SIZE 484 485 mov x6, x27 /* The initial page table */ 486#if defined(SOCDEV_PA) && defined(SOCDEV_VA) 487 /* Create a table for the UART */ 488 mov x7, #(ATTR_S1_nG | ATTR_S1_IDX(VM_MEMATTR_DEVICE)) 489 mov x8, #(SOCDEV_VA) /* VA start */ 490 mov x9, #(SOCDEV_PA) /* PA start */ 491 mov x10, #1 492 bl build_l1_block_pagetable 493#endif 494 495#if defined(LINUX_BOOT_ABI) 496 /* Map FDT data ? */ 497 cbz x19, 1f 498 499 /* Create the identity mapping for FDT data (2 MiB max) */ 500 mov x7, #(ATTR_S1_nG | ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK)) 501 mov x9, x0 502 mov x8, x0 /* VA start (== PA start) */ 503 mov x10, #1 504 bl build_l1_block_pagetable 505 5061: 507#endif 508 509 /* Create the VA = PA map */ 510 mov x7, #(ATTR_S1_nG | ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK)) 511 mov x9, x27 512 mov x8, x9 /* VA start (== PA start) */ 513 mov x10, #1 514 bl build_l1_block_pagetable 515 516 /* Move to the l0 table */ 517 add x27, x27, #PAGE_SIZE 518 519 /* Link the l0 -> l1 table */ 520 mov x9, x6 521 mov x6, x27 522 mov x10, #1 523 bl link_l0_pagetable 524 525 /* Restore the Link register */ 526 mov x30, x5 527 ret 528 529/* 530 * Builds an L0 -> L1 table descriptor 531 * 532 * This is a link for a 512GiB block of memory with up to 1GiB regions mapped 533 * within it by build_l1_block_pagetable. 534 * 535 * x6 = L0 table 536 * x8 = Virtual Address 537 * x9 = L1 PA (trashed) 538 * x10 = Entry count 539 * x11, x12 and x13 are trashed 540 */ 541link_l0_pagetable: 542 /* 543 * Link an L0 -> L1 table entry. 544 */ 545 /* Find the table index */ 546 lsr x11, x8, #L0_SHIFT 547 and x11, x11, #L0_ADDR_MASK 548 549 /* Build the L0 block entry */ 550 mov x12, #L0_TABLE 551 552 /* Only use the output address bits */ 553 lsr x9, x9, #PAGE_SHIFT 5541: orr x13, x12, x9, lsl #PAGE_SHIFT 555 556 /* Store the entry */ 557 str x13, [x6, x11, lsl #3] 558 559 sub x10, x10, #1 560 add x11, x11, #1 561 add x9, x9, #1 562 cbnz x10, 1b 563 564 ret 565 566/* 567 * Builds an L1 -> L2 table descriptor 568 * 569 * This is a link for a 1GiB block of memory with up to 2MiB regions mapped 570 * within it by build_l2_block_pagetable. 571 * 572 * x6 = L1 table 573 * x8 = Virtual Address 574 * x9 = L2 PA (trashed) 575 * x11, x12 and x13 are trashed 576 */ 577link_l1_pagetable: 578 /* 579 * Link an L1 -> L2 table entry. 580 */ 581 /* Find the table index */ 582 lsr x11, x8, #L1_SHIFT 583 and x11, x11, #Ln_ADDR_MASK 584 585 /* Build the L1 block entry */ 586 mov x12, #L1_TABLE 587 588 /* Only use the output address bits */ 589 lsr x9, x9, #PAGE_SHIFT 590 orr x13, x12, x9, lsl #PAGE_SHIFT 591 592 /* Store the entry */ 593 str x13, [x6, x11, lsl #3] 594 595 ret 596 597/* 598 * Builds count 1 GiB page table entry 599 * x6 = L1 table 600 * x7 = Variable lower block attributes 601 * x8 = VA start 602 * x9 = PA start (trashed) 603 * x10 = Entry count 604 * x11, x12 and x13 are trashed 605 */ 606build_l1_block_pagetable: 607 /* 608 * Build the L1 table entry. 609 */ 610 /* Find the table index */ 611 lsr x11, x8, #L1_SHIFT 612 and x11, x11, #Ln_ADDR_MASK 613 614 /* Build the L1 block entry */ 615 orr x12, x7, #L1_BLOCK 616 orr x12, x12, #(ATTR_DEFAULT) 617 618 /* Only use the output address bits */ 619 lsr x9, x9, #L1_SHIFT 620 621 /* Set the physical address for this virtual address */ 6221: orr x13, x12, x9, lsl #L1_SHIFT 623 624 /* Store the entry */ 625 str x13, [x6, x11, lsl #3] 626 627 sub x10, x10, #1 628 add x11, x11, #1 629 add x9, x9, #1 630 cbnz x10, 1b 631 632 ret 633 634/* 635 * Builds count 2 MiB page table entry 636 * x6 = L2 table 637 * x7 = Type (0 = Device, 1 = Normal) 638 * x8 = VA start 639 * x9 = PA start (trashed) 640 * x10 = Entry count 641 * x11, x12 and x13 are trashed 642 */ 643build_l2_block_pagetable: 644 /* 645 * Build the L2 table entry. 646 */ 647 /* Find the table index */ 648 lsr x11, x8, #L2_SHIFT 649 and x11, x11, #Ln_ADDR_MASK 650 651 /* Build the L2 block entry */ 652 lsl x12, x7, #2 653 orr x12, x12, #L2_BLOCK 654 orr x12, x12, #(ATTR_DEFAULT) 655 orr x12, x12, #(ATTR_S1_UXN) 656 657 /* Only use the output address bits */ 658 lsr x9, x9, #L2_SHIFT 659 660 /* Set the physical address for this virtual address */ 6611: orr x13, x12, x9, lsl #L2_SHIFT 662 663 /* Store the entry */ 664 str x13, [x6, x11, lsl #3] 665 666 sub x10, x10, #1 667 add x11, x11, #1 668 add x9, x9, #1 669 cbnz x10, 1b 670 671 ret 672 673start_mmu: 674 dsb sy 675 676 /* Load the exception vectors */ 677 ldr x2, =exception_vectors 678 msr vbar_el1, x2 679 680 /* Load ttbr0 and ttbr1 */ 681 msr ttbr0_el1, x27 682 msr ttbr1_el1, x24 683 isb 684 685 /* Clear the Monitor Debug System control register */ 686 msr mdscr_el1, xzr 687 688 /* Invalidate the TLB */ 689 tlbi vmalle1is 690 dsb ish 691 isb 692 693 ldr x2, mair 694 msr mair_el1, x2 695 696 /* 697 * Setup TCR according to the PARange and ASIDBits fields 698 * from ID_AA64MMFR0_EL1 and the HAFDBS field from the 699 * ID_AA64MMFR1_EL1. More precisely, set TCR_EL1.AS 700 * to 1 only if the ASIDBits field equals 0b0010. 701 */ 702 ldr x2, tcr 703 mrs x3, id_aa64mmfr0_el1 704 705 /* Copy the bottom 3 bits from id_aa64mmfr0_el1 into TCR.IPS */ 706 bfi x2, x3, #(TCR_IPS_SHIFT), #(TCR_IPS_WIDTH) 707 and x3, x3, #(ID_AA64MMFR0_ASIDBits_MASK) 708 709 /* Check if the HW supports 16 bit ASIDS */ 710 cmp x3, #(ID_AA64MMFR0_ASIDBits_16) 711 /* If so x3 == 1, else x3 == 0 */ 712 cset x3, eq 713 /* Set TCR.AS with x3 */ 714 bfi x2, x3, #(TCR_ASID_SHIFT), #(TCR_ASID_WIDTH) 715 716 /* 717 * Check if the HW supports access flag and dirty state updates, 718 * and set TCR_EL1.HA and TCR_EL1.HD accordingly. 719 */ 720 mrs x3, id_aa64mmfr1_el1 721 and x3, x3, #(ID_AA64MMFR1_HAFDBS_MASK) 722 cmp x3, #1 723 b.ne 1f 724 orr x2, x2, #(TCR_HA) 725 b 2f 7261: 727 cmp x3, #2 728 b.ne 2f 729 orr x2, x2, #(TCR_HA | TCR_HD) 7302: 731 msr tcr_el1, x2 732 733 /* 734 * Setup SCTLR. 735 */ 736 ldr x2, sctlr_set 737 ldr x3, sctlr_clear 738 mrs x1, sctlr_el1 739 bic x1, x1, x3 /* Clear the required bits */ 740 orr x1, x1, x2 /* Set the required bits */ 741 msr sctlr_el1, x1 742 isb 743 744 ret 745 746 .align 3 747mair: 748 .quad MAIR_ATTR(MAIR_DEVICE_nGnRnE, VM_MEMATTR_DEVICE) | \ 749 MAIR_ATTR(MAIR_NORMAL_NC, VM_MEMATTR_UNCACHEABLE) | \ 750 MAIR_ATTR(MAIR_NORMAL_WB, VM_MEMATTR_WRITE_BACK) | \ 751 MAIR_ATTR(MAIR_NORMAL_WT, VM_MEMATTR_WRITE_THROUGH) 752tcr: 753 .quad (TCR_TxSZ(64 - VIRT_BITS) | TCR_TG1_4K | \ 754 TCR_CACHE_ATTRS | TCR_SMP_ATTRS) 755sctlr_set: 756 /* Bits to set */ 757 .quad (SCTLR_LSMAOE | SCTLR_nTLSMD | SCTLR_UCI | SCTLR_SPAN | \ 758 SCTLR_nTWE | SCTLR_nTWI | SCTLR_UCT | SCTLR_DZE | \ 759 SCTLR_I | SCTLR_SED | SCTLR_SA0 | SCTLR_SA | SCTLR_C | \ 760 SCTLR_M | SCTLR_CP15BEN) 761sctlr_clear: 762 /* Bits to clear */ 763 .quad (SCTLR_EE | SCTLR_EOE | SCTLR_IESB | SCTLR_WXN | SCTLR_UMA | \ 764 SCTLR_ITD | SCTLR_A) 765 766 .globl abort 767abort: 768 b abort 769 770 //.section .init_pagetable 771 .align 12 /* 4KiB aligned */ 772 /* 773 * 6 initial tables (in the following order): 774 * L2 for kernel (High addresses) 775 * L1 for kernel 776 * L0 for kernel 777 * L1 bootstrap for user (Low addresses) 778 * L0 bootstrap for user 779 * L0 for user 780 */ 781pagetable: 782 .space PAGE_SIZE 783pagetable_l1_ttbr1: 784 .space PAGE_SIZE 785pagetable_l0_ttbr1: 786 .space PAGE_SIZE 787pagetable_l1_ttbr0_bootstrap: 788 .space PAGE_SIZE 789pagetable_l0_ttbr0_boostrap: 790 .space PAGE_SIZE 791pagetable_l0_ttbr0: 792 .space PAGE_SIZE 793 794 .globl pagetable_dmap 795pagetable_dmap: 796 .space PAGE_SIZE * DMAP_TABLES 797pagetable_end: 798 799el2_pagetable: 800 .space PAGE_SIZE 801 802 .globl init_pt_va 803init_pt_va: 804 .quad pagetable /* XXX: Keep page tables VA */ 805 806 .align 4 807initstack: 808 .space (PAGE_SIZE * KSTACK_PAGES) 809initstack_end: 810 811 812ENTRY(sigcode) 813 mov x0, sp 814 add x0, x0, #SF_UC 815 8161: 817 mov x8, #SYS_sigreturn 818 svc 0 819 820 /* sigreturn failed, exit */ 821 mov x8, #SYS_exit 822 svc 0 823 824 b 1b 825END(sigcode) 826 /* This may be copied to the stack, keep it 16-byte aligned */ 827 .align 3 828esigcode: 829 830 .data 831 .align 3 832 .global szsigcode 833szsigcode: 834 .quad esigcode - sigcode 835 836ENTRY(aarch32_sigcode) 837 .word 0xe1a0000d // mov r0, sp 838 .word 0xe2800040 // add r0, r0, #SIGF_UC 839 .word 0xe59f700c // ldr r7, [pc, #12] 840 .word 0xef000000 // swi #0 841 .word 0xe59f7008 // ldr r7, [pc, #8] 842 .word 0xef000000 // swi #0 843 .word 0xeafffffa // b . - 16 844END(aarch32_sigcode) 845 .word SYS_sigreturn 846 .word SYS_exit 847 .align 3 848aarch32_esigcode: 849 .data 850 .global sz_aarch32_sigcode 851sz_aarch32_sigcode: 852 .quad aarch32_esigcode - aarch32_sigcode 853