1/*- 2 * Copyright (c) 2012-2014 Andrew Turner 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29#include "assym.inc" 30#include "opt_kstack_pages.h" 31#include <sys/syscall.h> 32#include <machine/asm.h> 33#include <machine/armreg.h> 34#include <machine/hypervisor.h> 35#include <machine/param.h> 36#include <machine/pte.h> 37#include <machine/vm.h> 38#include <machine/vmparam.h> 39 40#define VIRT_BITS 48 41 42 .globl kernbase 43 .set kernbase, KERNBASE 44 45/* 46 * We assume: 47 * MMU on with an identity map, or off 48 * D-Cache: off 49 * I-Cache: on or off 50 * We are loaded at a 2MiB aligned address 51 */ 52 53ENTRY(_start) 54 /* Drop to EL1 */ 55 bl drop_to_el1 56 57 /* 58 * Disable the MMU. We may have entered the kernel with it on and 59 * will need to update the tables later. If this has been set up 60 * with anything other than a VA == PA map then this will fail, 61 * but in this case the code to find where we are running from 62 * would have also failed. 63 */ 64 dsb sy 65 mrs x2, sctlr_el1 66 bic x2, x2, SCTLR_M 67 msr sctlr_el1, x2 68 isb 69 70 /* Set the context id */ 71 msr contextidr_el1, xzr 72 73 /* Get the virt -> phys offset */ 74 bl get_virt_delta 75 76 /* 77 * At this point: 78 * x29 = PA - VA 79 * x28 = Our physical load address 80 */ 81 82 /* Create the page tables */ 83 bl create_pagetables 84 85 /* 86 * At this point: 87 * x27 = TTBR0 table 88 * x26 = Kernel L1 table 89 * x24 = TTBR1 table 90 */ 91 92 /* Enable the mmu */ 93 bl start_mmu 94 95 /* Load the new ttbr0 pagetable */ 96 adrp x27, pagetable_l0_ttbr0 97 add x27, x27, :lo12:pagetable_l0_ttbr0 98 99 /* Jump to the virtual address space */ 100 ldr x15, .Lvirtdone 101 br x15 102 103virtdone: 104 /* Set up the stack */ 105 adrp x25, initstack_end 106 add x25, x25, :lo12:initstack_end 107 mov sp, x25 108 sub sp, sp, #PCB_SIZE 109 110 /* Zero the BSS */ 111 ldr x15, .Lbss 112 ldr x14, .Lend 1131: 114 str xzr, [x15], #8 115 cmp x15, x14 116 b.lo 1b 117 118#if defined(PERTHREAD_SSP) 119 /* Set sp_el0 to the boot canary for early per-thread SSP to work */ 120 adrp x15, boot_canary 121 add x15, x15, :lo12:boot_canary 122 msr sp_el0, x15 123#endif 124 125 /* Backup the module pointer */ 126 mov x1, x0 127 128 /* Make the page table base a virtual address */ 129 sub x26, x26, x29 130 sub x24, x24, x29 131 132 sub sp, sp, #BOOTPARAMS_SIZE 133 mov x0, sp 134 135 /* Degate the delda so it is VA -> PA */ 136 neg x29, x29 137 138 str x1, [x0, #BP_MODULEP] 139 str x26, [x0, #BP_KERN_L1PT] 140 str x29, [x0, #BP_KERN_DELTA] 141 adrp x25, initstack 142 add x25, x25, :lo12:initstack 143 str x25, [x0, #BP_KERN_STACK] 144 str x24, [x0, #BP_KERN_L0PT] 145 str x27, [x0, #BP_KERN_TTBR0] 146 str x23, [x0, #BP_BOOT_EL] 147 148 /* trace back starts here */ 149 mov fp, #0 150 /* Branch to C code */ 151 bl initarm 152 /* We are done with the boot params */ 153 add sp, sp, #BOOTPARAMS_SIZE 154 155 /* 156 * Enable pointer authentication in the kernel. We set the keys for 157 * thread0 in initarm so have to wait until it returns to enable it. 158 * If we were to enable it in initarm then any authentication when 159 * returning would fail as it was called with pointer authentication 160 * disabled. 161 */ 162 bl ptrauth_start 163 164 bl mi_startup 165 166 /* We should not get here */ 167 brk 0 168 169 .align 3 170.Lvirtdone: 171 .quad virtdone 172.Lbss: 173 .quad __bss_start 174.Lend: 175 .quad __bss_end 176END(_start) 177 178#ifdef SMP 179/* 180 * mpentry(unsigned long) 181 * 182 * Called by a core when it is being brought online. 183 * The data in x0 is passed straight to init_secondary. 184 */ 185ENTRY(mpentry) 186 /* Disable interrupts */ 187 msr daifset, #DAIF_INTR 188 189 /* Drop to EL1 */ 190 bl drop_to_el1 191 192 /* Set the context id */ 193 msr contextidr_el1, xzr 194 195 /* Load the kernel page table */ 196 adrp x24, pagetable_l0_ttbr1 197 add x24, x24, :lo12:pagetable_l0_ttbr1 198 /* Load the identity page table */ 199 adrp x27, pagetable_l0_ttbr0_boostrap 200 add x27, x27, :lo12:pagetable_l0_ttbr0_boostrap 201 202 /* Enable the mmu */ 203 bl start_mmu 204 205 /* Load the new ttbr0 pagetable */ 206 adrp x27, pagetable_l0_ttbr0 207 add x27, x27, :lo12:pagetable_l0_ttbr0 208 209 /* Jump to the virtual address space */ 210 ldr x15, =mp_virtdone 211 br x15 212 213mp_virtdone: 214 /* Start using the AP boot stack */ 215 ldr x4, =bootstack 216 ldr x4, [x4] 217 mov sp, x4 218 219#if defined(PERTHREAD_SSP) 220 /* Set sp_el0 to the boot canary for early per-thread SSP to work */ 221 adrp x15, boot_canary 222 add x15, x15, :lo12:boot_canary 223 msr sp_el0, x15 224#endif 225 226 /* Load the kernel ttbr0 pagetable */ 227 msr ttbr0_el1, x27 228 isb 229 230 /* Invalidate the TLB */ 231 tlbi vmalle1 232 dsb sy 233 isb 234 235 b init_secondary 236END(mpentry) 237#endif 238 239/* 240 * If we are started in EL2, configure the required hypervisor 241 * registers and drop to EL1. 242 */ 243LENTRY(drop_to_el1) 244 mrs x23, CurrentEL 245 lsr x23, x23, #2 246 cmp x23, #0x2 247 b.eq 1f 248 ret 2491: 250 /* Configure the Hypervisor */ 251 ldr x2, =(HCR_RW | HCR_APK | HCR_API) 252 msr hcr_el2, x2 253 254 /* Load the Virtualization Process ID Register */ 255 mrs x2, midr_el1 256 msr vpidr_el2, x2 257 258 /* Load the Virtualization Multiprocess ID Register */ 259 mrs x2, mpidr_el1 260 msr vmpidr_el2, x2 261 262 /* Set the bits that need to be 1 in sctlr_el1 */ 263 ldr x2, .Lsctlr_res1 264 msr sctlr_el1, x2 265 266 /* Don't trap to EL2 for exceptions */ 267 mov x2, #CPTR_RES1 268 msr cptr_el2, x2 269 270 /* Don't trap to EL2 for CP15 traps */ 271 msr hstr_el2, xzr 272 273 /* Enable access to the physical timers at EL1 */ 274 mrs x2, cnthctl_el2 275 orr x2, x2, #(CNTHCTL_EL1PCTEN | CNTHCTL_EL1PCEN) 276 msr cnthctl_el2, x2 277 278 /* Set the counter offset to a known value */ 279 msr cntvoff_el2, xzr 280 281 /* Hypervisor trap functions */ 282 adrp x2, hyp_vectors 283 add x2, x2, :lo12:hyp_vectors 284 msr vbar_el2, x2 285 286 mov x2, #(PSR_F | PSR_I | PSR_A | PSR_D | PSR_M_EL1h) 287 msr spsr_el2, x2 288 289 /* Configure GICv3 CPU interface */ 290 mrs x2, id_aa64pfr0_el1 291 /* Extract GIC bits from the register */ 292 ubfx x2, x2, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_BITS 293 /* GIC[3:0] == 0001 - GIC CPU interface via special regs. supported */ 294 cmp x2, #(ID_AA64PFR0_GIC_CPUIF_EN >> ID_AA64PFR0_GIC_SHIFT) 295 b.ne 2f 296 297 mrs x2, icc_sre_el2 298 orr x2, x2, #ICC_SRE_EL2_EN /* Enable access from insecure EL1 */ 299 orr x2, x2, #ICC_SRE_EL2_SRE /* Enable system registers */ 300 msr icc_sre_el2, x2 3012: 302 303 /* Set the address to return to our return address */ 304 msr elr_el2, x30 305 isb 306 307 eret 308 309 .align 3 310.Lsctlr_res1: 311 .quad SCTLR_RES1 312LEND(drop_to_el1) 313 314#define VECT_EMPTY \ 315 .align 7; \ 316 1: b 1b 317 318 .align 11 319hyp_vectors: 320 VECT_EMPTY /* Synchronous EL2t */ 321 VECT_EMPTY /* IRQ EL2t */ 322 VECT_EMPTY /* FIQ EL2t */ 323 VECT_EMPTY /* Error EL2t */ 324 325 VECT_EMPTY /* Synchronous EL2h */ 326 VECT_EMPTY /* IRQ EL2h */ 327 VECT_EMPTY /* FIQ EL2h */ 328 VECT_EMPTY /* Error EL2h */ 329 330 VECT_EMPTY /* Synchronous 64-bit EL1 */ 331 VECT_EMPTY /* IRQ 64-bit EL1 */ 332 VECT_EMPTY /* FIQ 64-bit EL1 */ 333 VECT_EMPTY /* Error 64-bit EL1 */ 334 335 VECT_EMPTY /* Synchronous 32-bit EL1 */ 336 VECT_EMPTY /* IRQ 32-bit EL1 */ 337 VECT_EMPTY /* FIQ 32-bit EL1 */ 338 VECT_EMPTY /* Error 32-bit EL1 */ 339 340/* 341 * Get the delta between the physical address we were loaded to and the 342 * virtual address we expect to run from. This is used when building the 343 * initial page table. 344 */ 345LENTRY(get_virt_delta) 346 /* Load the physical address of virt_map */ 347 adrp x29, virt_map 348 add x29, x29, :lo12:virt_map 349 /* Load the virtual address of virt_map stored in virt_map */ 350 ldr x28, [x29] 351 /* Find PA - VA as PA' = VA' - VA + PA = VA' + (PA - VA) = VA' + x29 */ 352 sub x29, x29, x28 353 /* Find the load address for the kernel */ 354 mov x28, #(KERNBASE) 355 add x28, x28, x29 356 ret 357 358 .align 3 359virt_map: 360 .quad virt_map 361LEND(get_virt_delta) 362 363/* 364 * This builds the page tables containing the identity map, and the kernel 365 * virtual map. 366 * 367 * It relys on: 368 * We were loaded to an address that is on a 2MiB boundary 369 * All the memory must not cross a 1GiB boundaty 370 * x28 contains the physical address we were loaded from 371 * 372 * TODO: This is out of date. 373 * There are at least 5 pages before that address for the page tables 374 * The pages used are: 375 * - The Kernel L2 table 376 * - The Kernel L1 table 377 * - The Kernel L0 table (TTBR1) 378 * - The identity (PA = VA) L1 table 379 * - The identity (PA = VA) L0 table (TTBR0) 380 */ 381LENTRY(create_pagetables) 382 /* Save the Link register */ 383 mov x5, x30 384 385 /* Clean the page table */ 386 adrp x6, pagetable 387 add x6, x6, :lo12:pagetable 388 mov x26, x6 389 adrp x27, pagetable_end 390 add x27, x27, :lo12:pagetable_end 3911: 392 stp xzr, xzr, [x6], #16 393 stp xzr, xzr, [x6], #16 394 stp xzr, xzr, [x6], #16 395 stp xzr, xzr, [x6], #16 396 cmp x6, x27 397 b.lo 1b 398 399 /* 400 * Build the TTBR1 maps. 401 */ 402 403 /* Find the size of the kernel */ 404 mov x6, #(KERNBASE) 405 406#if defined(LINUX_BOOT_ABI) 407 /* X19 is used as 'map FDT data' flag */ 408 mov x19, xzr 409 410 /* No modules or FDT pointer ? */ 411 cbz x0, booti_no_fdt 412 413 /* 414 * Test if x0 points to modules descriptor(virtual address) or 415 * to FDT (physical address) 416 */ 417 cmp x0, x6 /* x6 is #(KERNBASE) */ 418 b.lo booti_fdt 419#endif 420 421 /* Booted with modules pointer */ 422 /* Find modulep - begin */ 423 sub x8, x0, x6 424 /* Add two 2MiB pages for the module data and round up */ 425 ldr x7, =(3 * L2_SIZE - 1) 426 add x8, x8, x7 427 b common 428 429#if defined(LINUX_BOOT_ABI) 430booti_fdt: 431 /* Booted by U-Boot booti with FDT data */ 432 /* Set 'map FDT data' flag */ 433 mov x19, #1 434 435booti_no_fdt: 436 /* Booted by U-Boot booti without FTD data */ 437 /* Find the end - begin */ 438 ldr x7, .Lend 439 sub x8, x7, x6 440 441 /* 442 * Add one 2MiB page for copy of FDT data (maximum FDT size), 443 * one for metadata and round up 444 */ 445 ldr x7, =(3 * L2_SIZE - 1) 446 add x8, x8, x7 447#endif 448 449common: 450 /* Get the number of l2 pages to allocate, rounded down */ 451 lsr x10, x8, #(L2_SHIFT) 452 453 /* Create the kernel space L2 table */ 454 mov x6, x26 455 mov x7, #(ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK)) 456 mov x8, #(KERNBASE) 457 mov x9, x28 458 bl build_l2_block_pagetable 459 460 /* Move to the l1 table */ 461 add x26, x26, #PAGE_SIZE 462 463 /* Link the l1 -> l2 table */ 464 mov x9, x6 465 mov x6, x26 466 bl link_l1_pagetable 467 468 /* Move to the l0 table */ 469 add x24, x26, #PAGE_SIZE 470 471 /* Link the l0 -> l1 table */ 472 mov x9, x6 473 mov x6, x24 474 mov x10, #1 475 bl link_l0_pagetable 476 477 /* 478 * Build the TTBR0 maps. As TTBR0 maps, they must specify ATTR_S1_nG. 479 * They are only needed early on, so the VA = PA map is uncached. 480 */ 481 add x27, x24, #PAGE_SIZE 482 483 mov x6, x27 /* The initial page table */ 484 485 /* Create the VA = PA map */ 486 mov x7, #(ATTR_S1_nG | ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK)) 487 adrp x16, _start 488 and x16, x16, #(~L2_OFFSET) 489 mov x9, x16 /* PA start */ 490 mov x8, x16 /* VA start (== PA start) */ 491 mov x10, #1 492 bl build_l2_block_pagetable 493 494#if defined(SOCDEV_PA) 495 /* Create a table for the UART */ 496 mov x7, #(ATTR_S1_nG | ATTR_S1_IDX(VM_MEMATTR_DEVICE)) 497 add x16, x16, #(L2_SIZE) /* VA start */ 498 mov x8, x16 499 500 /* Store the socdev virtual address */ 501 add x17, x8, #(SOCDEV_PA & L2_OFFSET) 502 adrp x9, socdev_va 503 str x17, [x9, :lo12:socdev_va] 504 505 mov x9, #(SOCDEV_PA & ~L2_OFFSET) /* PA start */ 506 mov x10, #1 507 bl build_l2_block_pagetable 508#endif 509 510#if defined(LINUX_BOOT_ABI) 511 /* Map FDT data ? */ 512 cbz x19, 1f 513 514 /* Create the mapping for FDT data (2 MiB max) */ 515 mov x7, #(ATTR_S1_nG | ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK)) 516 add x16, x16, #(L2_SIZE) /* VA start */ 517 mov x8, x16 518 mov x9, x0 /* PA start */ 519 /* Update the module pointer to point at the allocated memory */ 520 and x0, x0, #(L2_OFFSET) /* Keep the lower bits */ 521 add x0, x0, x8 /* Add the aligned virtual address */ 522 523 mov x10, #1 524 bl build_l2_block_pagetable 525 5261: 527#endif 528 529 /* Move to the l1 table */ 530 add x27, x27, #PAGE_SIZE 531 532 /* Link the l1 -> l2 table */ 533 mov x9, x6 534 mov x6, x27 535 bl link_l1_pagetable 536 537 /* Move to the l0 table */ 538 add x27, x27, #PAGE_SIZE 539 540 /* Link the l0 -> l1 table */ 541 mov x9, x6 542 mov x6, x27 543 mov x10, #1 544 bl link_l0_pagetable 545 546 /* Restore the Link register */ 547 mov x30, x5 548 ret 549LEND(create_pagetables) 550 551/* 552 * Builds an L0 -> L1 table descriptor 553 * 554 * x6 = L0 table 555 * x8 = Virtual Address 556 * x9 = L1 PA (trashed) 557 * x10 = Entry count (trashed) 558 * x11, x12 and x13 are trashed 559 */ 560LENTRY(link_l0_pagetable) 561 /* 562 * Link an L0 -> L1 table entry. 563 */ 564 /* Find the table index */ 565 lsr x11, x8, #L0_SHIFT 566 and x11, x11, #L0_ADDR_MASK 567 568 /* Build the L0 block entry */ 569 mov x12, #L0_TABLE 570 orr x12, x12, #(TATTR_UXN_TABLE | TATTR_AP_TABLE_NO_EL0) 571 572 /* Only use the output address bits */ 573 lsr x9, x9, #PAGE_SHIFT 5741: orr x13, x12, x9, lsl #PAGE_SHIFT 575 576 /* Store the entry */ 577 str x13, [x6, x11, lsl #3] 578 579 sub x10, x10, #1 580 add x11, x11, #1 581 add x9, x9, #1 582 cbnz x10, 1b 583 584 ret 585LEND(link_l0_pagetable) 586 587/* 588 * Builds an L1 -> L2 table descriptor 589 * 590 * x6 = L1 table 591 * x8 = Virtual Address 592 * x9 = L2 PA (trashed) 593 * x11, x12 and x13 are trashed 594 */ 595LENTRY(link_l1_pagetable) 596 /* 597 * Link an L1 -> L2 table entry. 598 */ 599 /* Find the table index */ 600 lsr x11, x8, #L1_SHIFT 601 and x11, x11, #Ln_ADDR_MASK 602 603 /* Build the L1 block entry */ 604 mov x12, #L1_TABLE 605 606 /* Only use the output address bits */ 607 lsr x9, x9, #PAGE_SHIFT 608 orr x13, x12, x9, lsl #PAGE_SHIFT 609 610 /* Store the entry */ 611 str x13, [x6, x11, lsl #3] 612 613 ret 614LEND(link_l1_pagetable) 615 616/* 617 * Builds count 2 MiB page table entry 618 * x6 = L2 table 619 * x7 = Block attributes 620 * x8 = VA start 621 * x9 = PA start (trashed) 622 * x10 = Entry count (trashed) 623 * x11, x12 and x13 are trashed 624 */ 625LENTRY(build_l2_block_pagetable) 626 /* 627 * Build the L2 table entry. 628 */ 629 /* Find the table index */ 630 lsr x11, x8, #L2_SHIFT 631 and x11, x11, #Ln_ADDR_MASK 632 633 /* Build the L2 block entry */ 634 orr x12, x7, #L2_BLOCK 635 orr x12, x12, #(ATTR_DEFAULT) 636 orr x12, x12, #(ATTR_S1_UXN) 637 638 /* Only use the output address bits */ 639 lsr x9, x9, #L2_SHIFT 640 641 /* Set the physical address for this virtual address */ 6421: orr x13, x12, x9, lsl #L2_SHIFT 643 644 /* Store the entry */ 645 str x13, [x6, x11, lsl #3] 646 647 sub x10, x10, #1 648 add x11, x11, #1 649 add x9, x9, #1 650 cbnz x10, 1b 651 652 ret 653LEND(build_l2_block_pagetable) 654 655LENTRY(start_mmu) 656 dsb sy 657 658 /* Load the exception vectors */ 659 ldr x2, =exception_vectors 660 msr vbar_el1, x2 661 662 /* Load ttbr0 and ttbr1 */ 663 msr ttbr0_el1, x27 664 msr ttbr1_el1, x24 665 isb 666 667 /* Clear the Monitor Debug System control register */ 668 msr mdscr_el1, xzr 669 670 /* Invalidate the TLB */ 671 tlbi vmalle1is 672 dsb ish 673 isb 674 675 ldr x2, mair 676 msr mair_el1, x2 677 678 /* 679 * Setup TCR according to the PARange and ASIDBits fields 680 * from ID_AA64MMFR0_EL1 and the HAFDBS field from the 681 * ID_AA64MMFR1_EL1. More precisely, set TCR_EL1.AS 682 * to 1 only if the ASIDBits field equals 0b0010. 683 */ 684 ldr x2, tcr 685 mrs x3, id_aa64mmfr0_el1 686 687 /* Copy the bottom 3 bits from id_aa64mmfr0_el1 into TCR.IPS */ 688 bfi x2, x3, #(TCR_IPS_SHIFT), #(TCR_IPS_WIDTH) 689 and x3, x3, #(ID_AA64MMFR0_ASIDBits_MASK) 690 691 /* Check if the HW supports 16 bit ASIDS */ 692 cmp x3, #(ID_AA64MMFR0_ASIDBits_16) 693 /* If so x3 == 1, else x3 == 0 */ 694 cset x3, eq 695 /* Set TCR.AS with x3 */ 696 bfi x2, x3, #(TCR_ASID_SHIFT), #(TCR_ASID_WIDTH) 697 698 /* 699 * Check if the HW supports access flag and dirty state updates, 700 * and set TCR_EL1.HA and TCR_EL1.HD accordingly. 701 */ 702 mrs x3, id_aa64mmfr1_el1 703 and x3, x3, #(ID_AA64MMFR1_HAFDBS_MASK) 704 cmp x3, #1 705 b.ne 1f 706 orr x2, x2, #(TCR_HA) 707 b 2f 7081: 709 cmp x3, #2 710 b.ne 2f 711 orr x2, x2, #(TCR_HA | TCR_HD) 7122: 713 msr tcr_el1, x2 714 715 /* 716 * Setup SCTLR. 717 */ 718 ldr x2, sctlr_set 719 ldr x3, sctlr_clear 720 mrs x1, sctlr_el1 721 bic x1, x1, x3 /* Clear the required bits */ 722 orr x1, x1, x2 /* Set the required bits */ 723 msr sctlr_el1, x1 724 isb 725 726 ret 727 728 .align 3 729mair: 730 .quad MAIR_ATTR(MAIR_DEVICE_nGnRnE, VM_MEMATTR_DEVICE_nGnRnE) | \ 731 MAIR_ATTR(MAIR_NORMAL_NC, VM_MEMATTR_UNCACHEABLE) | \ 732 MAIR_ATTR(MAIR_NORMAL_WB, VM_MEMATTR_WRITE_BACK) | \ 733 MAIR_ATTR(MAIR_NORMAL_WT, VM_MEMATTR_WRITE_THROUGH) | \ 734 MAIR_ATTR(MAIR_DEVICE_nGnRE, VM_MEMATTR_DEVICE_nGnRE) 735tcr: 736 .quad (TCR_TxSZ(64 - VIRT_BITS) | TCR_TG1_4K | TCR_TG0_4K | \ 737 TCR_CACHE_ATTRS | TCR_SMP_ATTRS) 738sctlr_set: 739 /* Bits to set */ 740 .quad (SCTLR_LSMAOE | SCTLR_nTLSMD | SCTLR_UCI | SCTLR_SPAN | \ 741 SCTLR_nTWE | SCTLR_nTWI | SCTLR_UCT | SCTLR_DZE | \ 742 SCTLR_I | SCTLR_SED | SCTLR_SA0 | SCTLR_SA | SCTLR_C | \ 743 SCTLR_M | SCTLR_CP15BEN) 744sctlr_clear: 745 /* Bits to clear */ 746 .quad (SCTLR_EE | SCTLR_E0E | SCTLR_IESB | SCTLR_WXN | SCTLR_UMA | \ 747 SCTLR_ITD | SCTLR_A) 748LEND(start_mmu) 749 750ENTRY(abort) 751 b abort 752END(abort) 753 754 .section .init_pagetable, "aw", %nobits 755 .align PAGE_SHIFT 756 /* 757 * 6 initial tables (in the following order): 758 * L2 for kernel (High addresses) 759 * L1 for kernel 760 * L0 for kernel 761 * L1 bootstrap for user (Low addresses) 762 * L0 bootstrap for user 763 * L0 for user 764 */ 765 .globl pagetable_l0_ttbr1 766pagetable: 767 .space PAGE_SIZE 768pagetable_l1_ttbr1: 769 .space PAGE_SIZE 770pagetable_l0_ttbr1: 771 .space PAGE_SIZE 772pagetable_l2_ttbr0_bootstrap: 773 .space PAGE_SIZE 774pagetable_l1_ttbr0_bootstrap: 775 .space PAGE_SIZE 776pagetable_l0_ttbr0_boostrap: 777 .space PAGE_SIZE 778pagetable_l0_ttbr0: 779 .space PAGE_SIZE 780 781pagetable_end: 782 783el2_pagetable: 784 .space PAGE_SIZE 785 786 .align 4 787initstack: 788 .space (PAGE_SIZE * KSTACK_PAGES) 789initstack_end: 790 791 792.text 793EENTRY(aarch32_sigcode) 794 .word 0xe1a0000d // mov r0, sp 795 .word 0xe2800040 // add r0, r0, #SIGF_UC 796 .word 0xe59f700c // ldr r7, [pc, #12] 797 .word 0xef000000 // swi #0 798 .word 0xe59f7008 // ldr r7, [pc, #8] 799 .word 0xef000000 // swi #0 800 .word 0xeafffffa // b . - 16 801EEND(aarch32_sigcode) 802 .word SYS_sigreturn 803 .word SYS_exit 804 .align 3 805aarch32_esigcode: 806 .data 807 .global sz_aarch32_sigcode 808sz_aarch32_sigcode: 809 .quad aarch32_esigcode - aarch32_sigcode 810