1/*- 2 * Copyright (c) 2014 Robin Randhawa 3 * Copyright (c) 2015 The FreeBSD Foundation 4 * All rights reserved. 5 * 6 * Portions of this software were developed by Andrew Turner 7 * under sponsorship from the FreeBSD Foundation 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 */ 31 32#include <sys/errno.h> 33#include <machine/asm.h> 34#include <machine/param.h> 35 36#include "assym.inc" 37/* 38 * FIXME: 39 * Need big.LITTLE awareness at some point. 40 * Using arm64_p[id]cache_line_size may not be the best option. 41 * Need better SMP awareness. 42 */ 43 .text 44 .align 2 45 46.Lpage_mask: 47 .word PAGE_MASK 48 49/* 50 * Macro to handle the cache. This takes the start address in x0, length 51 * in x1. It will corrupt x0, x1, x2, x3, and x4. 52 */ 53.macro cache_handle_range dcop = 0, ic = 0, icop = 0 54.if \ic == 0 55 ldr x3, =dcache_line_size /* Load the D cache line size */ 56.else 57 ldr x3, =idcache_line_size /* Load the I & D cache line size */ 58.endif 59 ldr x3, [x3] 60 sub x4, x3, #1 /* Get the address mask */ 61 and x2, x0, x4 /* Get the low bits of the address */ 62 add x1, x1, x2 /* Add these to the size */ 63 bic x0, x0, x4 /* Clear the low bit of the address */ 64.if \ic != 0 65 mov x2, x0 /* Save the address */ 66 mov x4, x1 /* Save the size */ 67.endif 681: 69 dc \dcop, x0 70 add x0, x0, x3 /* Move to the next line */ 71 subs x1, x1, x3 /* Reduce the size */ 72 b.hi 1b /* Check if we are done */ 73 dsb ish 74.if \ic != 0 752: 76 ic \icop, x2 77 add x2, x2, x3 /* Move to the next line */ 78 subs x4, x4, x3 /* Reduce the size */ 79 b.hi 2b /* Check if we are done */ 80 dsb ish 81 isb 82.endif 83.endm 84 85ENTRY(arm64_nullop) 86 ret 87END(arm64_nullop) 88 89/* 90 * Generic functions to read/modify/write the internal coprocessor registers 91 */ 92 93ENTRY(arm64_tlb_flushID) 94 dsb ishst 95#ifdef SMP 96 tlbi vmalle1is 97#else 98 tlbi vmalle1 99#endif 100 dsb ish 101 isb 102 ret 103END(arm64_tlb_flushID) 104 105/* 106 * void arm64_dcache_wb_range(vm_offset_t, vm_size_t) 107 */ 108ENTRY(arm64_dcache_wb_range) 109 cache_handle_range dcop = cvac 110 ret 111END(arm64_dcache_wb_range) 112 113/* 114 * void arm64_dcache_wbinv_range(vm_offset_t, vm_size_t) 115 */ 116ENTRY(arm64_dcache_wbinv_range) 117 cache_handle_range dcop = civac 118 ret 119END(arm64_dcache_wbinv_range) 120 121/* 122 * void arm64_dcache_inv_range(vm_offset_t, vm_size_t) 123 * 124 * Note, we must not invalidate everything. If the range is too big we 125 * must use wb-inv of the entire cache. 126 */ 127ENTRY(arm64_dcache_inv_range) 128 cache_handle_range dcop = ivac 129 ret 130END(arm64_dcache_inv_range) 131 132/* 133 * void arm64_dic_idc_icache_sync_range(vm_offset_t, vm_size_t) 134 * When the CTR_EL0.IDC bit is set cleaning to PoU becomes a dsb. 135 * When the CTR_EL0.DIC bit is set icache invalidation becomes an isb. 136 */ 137ENTRY(arm64_dic_idc_icache_sync_range) 138 dsb ishst 139 isb 140 ret 141END(arm64_dic_idc_icache_sync_range) 142 143/* 144 * void arm64_idc_aliasing_icache_sync_range(vm_offset_t, vm_size_t) 145 * When the CTR_EL0.IDC bit is set cleaning to PoU becomes a dsb. 146 */ 147ENTRY(arm64_idc_aliasing_icache_sync_range) 148 dsb ishst 149 ic ialluis 150 dsb ish 151 isb 152 ret 153END(arm64_idc_aliasing_icache_sync_range) 154 155/* 156 * void arm64_aliasing_icache_sync_range(vm_offset_t, vm_size_t) 157 */ 158ENTRY(arm64_aliasing_icache_sync_range) 159 /* 160 * XXX Temporary solution - I-cache flush should be range based for 161 * PIPT cache or IALLUIS for VIVT or VIPT caches 162 */ 163/* cache_handle_range dcop = cvau, ic = 1, icop = ivau */ 164 cache_handle_range dcop = cvau 165 ic ialluis 166 dsb ish 167 isb 168 ret 169END(arm64_aliasing_icache_sync_range) 170 171/* 172 * int arm64_icache_sync_range_checked(vm_offset_t, vm_size_t) 173 */ 174ENTRY(arm64_icache_sync_range_checked) 175 adr x5, cache_maint_fault 176 SET_FAULT_HANDLER(x5, x6) 177 /* XXX: See comment in arm64_icache_sync_range */ 178 cache_handle_range dcop = cvau 179 ic ialluis 180 dsb ish 181 isb 182 SET_FAULT_HANDLER(xzr, x6) 183 mov x0, #0 184 ret 185END(arm64_icache_sync_range_checked) 186 187ENTRY(cache_maint_fault) 188 SET_FAULT_HANDLER(xzr, x1) 189 mov x0, #EFAULT 190 ret 191END(cache_maint_fault) 192