1 /*- 2 * Copyright (c) 2013 Thomas Skibo 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 /* 30 * Zynq-700 SLCR driver. Provides hooks for cpu_reset and PL control stuff. 31 * In the future, maybe MIO control, clock control, etc. could go here. 32 * 33 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual. 34 * (v1.4) November 16, 2012. Xilinx doc UG585. 35 */ 36 37 #include <sys/cdefs.h> 38 __FBSDID("$FreeBSD$"); 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/conf.h> 43 #include <sys/kernel.h> 44 #include <sys/module.h> 45 #include <sys/lock.h> 46 #include <sys/mutex.h> 47 #include <sys/resource.h> 48 #include <sys/sysctl.h> 49 #include <sys/rman.h> 50 51 #include <machine/bus.h> 52 #include <machine/resource.h> 53 #include <machine/stdarg.h> 54 55 #include <dev/fdt/fdt_common.h> 56 #include <dev/ofw/ofw_bus.h> 57 #include <dev/ofw/ofw_bus_subr.h> 58 59 #include <arm/xilinx/zy7_slcr.h> 60 61 struct zy7_slcr_softc { 62 device_t dev; 63 struct mtx sc_mtx; 64 struct resource *mem_res; 65 }; 66 67 static struct zy7_slcr_softc *zy7_slcr_softc_p; 68 extern void (*zynq7_cpu_reset); 69 70 #define ZSLCR_LOCK(sc) mtx_lock(&(sc)->sc_mtx) 71 #define ZSLCR_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx) 72 #define ZSLCR_LOCK_INIT(sc) \ 73 mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev), \ 74 "zy7_slcr", MTX_DEF) 75 #define ZSLCR_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); 76 77 #define RD4(sc, off) (bus_read_4((sc)->mem_res, (off))) 78 #define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val))) 79 80 #define ZYNQ_DEFAULT_PS_CLK_FREQUENCY 33333333 /* 33.3 Mhz */ 81 82 83 SYSCTL_NODE(_hw, OID_AUTO, zynq, CTLFLAG_RD, 0, "Xilinx Zynq-7000"); 84 85 static char zynq_bootmode[64]; 86 SYSCTL_STRING(_hw_zynq, OID_AUTO, bootmode, CTLFLAG_RD, zynq_bootmode, 0, 87 "Zynq boot mode"); 88 89 static char zynq_pssid[100]; 90 SYSCTL_STRING(_hw_zynq, OID_AUTO, pssid, CTLFLAG_RD, zynq_pssid, 0, 91 "Zynq PSS IDCODE"); 92 93 static uint32_t zynq_reboot_status; 94 SYSCTL_INT(_hw_zynq, OID_AUTO, reboot_status, CTLFLAG_RD, &zynq_reboot_status, 95 0, "Zynq REBOOT_STATUS register"); 96 97 static int ps_clk_frequency; 98 SYSCTL_INT(_hw_zynq, OID_AUTO, ps_clk_frequency, CTLFLAG_RD, &ps_clk_frequency, 99 0, "Zynq PS_CLK Frequency"); 100 101 static int io_pll_frequency; 102 SYSCTL_INT(_hw_zynq, OID_AUTO, io_pll_frequency, CTLFLAG_RD, &io_pll_frequency, 103 0, "Zynq IO PLL Frequency"); 104 105 static int arm_pll_frequency; 106 SYSCTL_INT(_hw_zynq, OID_AUTO, arm_pll_frequency, CTLFLAG_RD, 107 &arm_pll_frequency, 0, "Zynq ARM PLL Frequency"); 108 109 static int ddr_pll_frequency; 110 SYSCTL_INT(_hw_zynq, OID_AUTO, ddr_pll_frequency, CTLFLAG_RD, 111 &ddr_pll_frequency, 0, "Zynq DDR PLL Frequency"); 112 113 static void 114 zy7_slcr_unlock(struct zy7_slcr_softc *sc) 115 { 116 117 /* Unlock SLCR with magic number. */ 118 WR4(sc, ZY7_SLCR_UNLOCK, ZY7_SLCR_UNLOCK_MAGIC); 119 } 120 121 static void 122 zy7_slcr_lock(struct zy7_slcr_softc *sc) 123 { 124 125 /* Lock SLCR with magic number. */ 126 WR4(sc, ZY7_SLCR_LOCK, ZY7_SLCR_LOCK_MAGIC); 127 } 128 129 130 static void 131 zy7_slcr_cpu_reset(void) 132 { 133 struct zy7_slcr_softc *sc = zy7_slcr_softc_p; 134 135 /* Unlock SLCR registers. */ 136 zy7_slcr_unlock(sc); 137 138 /* This has something to do with a work-around so the fsbl will load 139 * the bitstream after soft-reboot. It's very important. 140 */ 141 WR4(sc, ZY7_SLCR_REBOOT_STAT, 142 RD4(sc, ZY7_SLCR_REBOOT_STAT) & 0xf0ffffff); 143 144 /* Soft reset */ 145 WR4(sc, ZY7_SLCR_PSS_RST_CTRL, ZY7_SLCR_PSS_RST_CTRL_SOFT_RESET); 146 147 for (;;) 148 ; 149 } 150 151 /* Assert PL resets and disable level shifters in preparation of programming 152 * the PL (FPGA) section. Called from zy7_devcfg.c. 153 */ 154 void 155 zy7_slcr_preload_pl(void) 156 { 157 struct zy7_slcr_softc *sc = zy7_slcr_softc_p; 158 159 if (!sc) 160 return; 161 162 ZSLCR_LOCK(sc); 163 164 /* Unlock SLCR registers. */ 165 zy7_slcr_unlock(sc); 166 167 /* Assert top level output resets. */ 168 WR4(sc, ZY7_SLCR_FPGA_RST_CTRL, ZY7_SLCR_FPGA_RST_CTRL_RST_ALL); 169 170 /* Disable all level shifters. */ 171 WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, 0); 172 173 /* Lock SLCR registers. */ 174 zy7_slcr_lock(sc); 175 176 ZSLCR_UNLOCK(sc); 177 } 178 179 /* After PL configuration, enable level shifters and deassert top-level 180 * PL resets. Called from zy7_devcfg.c. Optionally, the level shifters 181 * can be left disabled but that's rare of an FPGA application. That option 182 * is controled by a sysctl in the devcfg driver. 183 */ 184 void 185 zy7_slcr_postload_pl(int en_level_shifters) 186 { 187 struct zy7_slcr_softc *sc = zy7_slcr_softc_p; 188 189 if (!sc) 190 return; 191 192 ZSLCR_LOCK(sc); 193 194 /* Unlock SLCR registers. */ 195 zy7_slcr_unlock(sc); 196 197 if (en_level_shifters) 198 /* Enable level shifters. */ 199 WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, ZY7_SLCR_LVL_SHFTR_EN_ALL); 200 201 /* Deassert top level output resets. */ 202 WR4(sc, ZY7_SLCR_FPGA_RST_CTRL, 0); 203 204 /* Lock SLCR registers. */ 205 zy7_slcr_lock(sc); 206 207 ZSLCR_UNLOCK(sc); 208 } 209 210 /* Override cgem_set_refclk() in gigabit ethernet driver 211 * (sys/dev/cadence/if_cgem.c). This function is called to 212 * request a change in the gem's reference clock speed. 213 */ 214 int 215 cgem_set_ref_clk(int unit, int frequency) 216 { 217 struct zy7_slcr_softc *sc = zy7_slcr_softc_p; 218 int div0, div1; 219 220 if (!sc) 221 return (-1); 222 223 /* Find suitable divisor pairs. Round result to nearest khz 224 * to test for match. 225 */ 226 for (div1 = 1; div1 <= ZY7_SLCR_GEM_CLK_CTRL_DIVISOR1_MAX; div1++) { 227 div0 = (io_pll_frequency + div1 * frequency / 2) / 228 div1 / frequency; 229 if (div0 > 0 && div0 <= ZY7_SLCR_GEM_CLK_CTRL_DIVISOR_MAX && 230 ((io_pll_frequency / div0 / div1) + 500) / 1000 == 231 (frequency + 500) / 1000) 232 break; 233 } 234 235 if (div1 > ZY7_SLCR_GEM_CLK_CTRL_DIVISOR1_MAX) 236 return (-1); 237 238 ZSLCR_LOCK(sc); 239 240 /* Unlock SLCR registers. */ 241 zy7_slcr_unlock(sc); 242 243 /* Modify GEM reference clock. */ 244 WR4(sc, unit ? ZY7_SLCR_GEM1_CLK_CTRL : ZY7_SLCR_GEM0_CLK_CTRL, 245 (div1 << ZY7_SLCR_GEM_CLK_CTRL_DIVISOR1_SHIFT) | 246 (div0 << ZY7_SLCR_GEM_CLK_CTRL_DIVISOR_SHIFT) | 247 ZY7_SLCR_GEM_CLK_CTRL_SRCSEL_IO_PLL | 248 ZY7_SLCR_GEM_CLK_CTRL_CLKACT); 249 250 /* Lock SLCR registers. */ 251 zy7_slcr_lock(sc); 252 253 ZSLCR_UNLOCK(sc); 254 255 return (0); 256 } 257 258 static int 259 zy7_slcr_probe(device_t dev) 260 { 261 262 if (!ofw_bus_status_okay(dev)) 263 return (ENXIO); 264 265 if (!ofw_bus_is_compatible(dev, "xlnx,zy7_slcr")) 266 return (ENXIO); 267 268 device_set_desc(dev, "Zynq-7000 slcr block"); 269 return (0); 270 } 271 272 static int 273 zy7_slcr_attach(device_t dev) 274 { 275 struct zy7_slcr_softc *sc = device_get_softc(dev); 276 int rid; 277 phandle_t node; 278 pcell_t cell; 279 uint32_t bootmode; 280 uint32_t pss_idcode; 281 uint32_t arm_pll_ctrl; 282 uint32_t ddr_pll_ctrl; 283 uint32_t io_pll_ctrl; 284 static char *bootdev_names[] = { 285 "JTAG", "Quad-SPI", "NOR", "(3?)", 286 "NAND", "SD Card", "(6?)", "(7?)" 287 }; 288 289 /* Allow only one attach. */ 290 if (zy7_slcr_softc_p != NULL) 291 return (ENXIO); 292 293 sc->dev = dev; 294 295 ZSLCR_LOCK_INIT(sc); 296 297 /* Get memory resource. */ 298 rid = 0; 299 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 300 RF_ACTIVE); 301 if (sc->mem_res == NULL) { 302 device_printf(dev, "could not allocate memory resources.\n"); 303 return (ENOMEM); 304 } 305 306 /* Hook up cpu_reset. */ 307 zy7_slcr_softc_p = sc; 308 zynq7_cpu_reset = zy7_slcr_cpu_reset; 309 310 /* Read info and set sysctls. */ 311 bootmode = RD4(sc, ZY7_SLCR_BOOT_MODE); 312 snprintf(zynq_bootmode, sizeof(zynq_bootmode), 313 "0x%x: boot device: %s", bootmode, 314 bootdev_names[bootmode & ZY7_SLCR_BOOT_MODE_BOOTDEV_MASK]); 315 316 pss_idcode = RD4(sc, ZY7_SLCR_PSS_IDCODE); 317 snprintf(zynq_pssid, sizeof(zynq_pssid), 318 "0x%x: manufacturer: 0x%x device: 0x%x " 319 "family: 0x%x sub-family: 0x%x rev: 0x%x", 320 pss_idcode, 321 (pss_idcode & ZY7_SLCR_PSS_IDCODE_MNFR_ID_MASK) >> 322 ZY7_SLCR_PSS_IDCODE_MNFR_ID_SHIFT, 323 (pss_idcode & ZY7_SLCR_PSS_IDCODE_DEVICE_MASK) >> 324 ZY7_SLCR_PSS_IDCODE_DEVICE_SHIFT, 325 (pss_idcode & ZY7_SLCR_PSS_IDCODE_FAMILY_MASK) >> 326 ZY7_SLCR_PSS_IDCODE_FAMILY_SHIFT, 327 (pss_idcode & ZY7_SLCR_PSS_IDCODE_SUB_FAMILY_MASK) >> 328 ZY7_SLCR_PSS_IDCODE_SUB_FAMILY_SHIFT, 329 (pss_idcode & ZY7_SLCR_PSS_IDCODE_REVISION_MASK) >> 330 ZY7_SLCR_PSS_IDCODE_REVISION_SHIFT); 331 332 zynq_reboot_status = RD4(sc, ZY7_SLCR_REBOOT_STAT); 333 334 /* Derive PLL frequencies from PS_CLK. */ 335 node = ofw_bus_get_node(dev); 336 if (OF_getprop(node, "clock-frequency", &cell, sizeof(cell)) > 0) 337 ps_clk_frequency = fdt32_to_cpu(cell); 338 else 339 ps_clk_frequency = ZYNQ_DEFAULT_PS_CLK_FREQUENCY; 340 341 arm_pll_ctrl = RD4(sc, ZY7_SLCR_ARM_PLL_CTRL); 342 ddr_pll_ctrl = RD4(sc, ZY7_SLCR_DDR_PLL_CTRL); 343 io_pll_ctrl = RD4(sc, ZY7_SLCR_IO_PLL_CTRL); 344 345 /* Determine ARM PLL frequency. */ 346 if (((arm_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) == 0 && 347 (arm_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_FORCE) != 0) || 348 ((arm_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) != 0 && 349 (bootmode & ZY7_SLCR_BOOT_MODE_PLL_BYPASS) != 0)) 350 /* PLL is bypassed. */ 351 arm_pll_frequency = ps_clk_frequency; 352 else 353 arm_pll_frequency = ps_clk_frequency * 354 ((arm_pll_ctrl & ZY7_SLCR_PLL_CTRL_FDIV_MASK) >> 355 ZY7_SLCR_PLL_CTRL_FDIV_SHIFT); 356 357 /* Determine DDR PLL frequency. */ 358 if (((ddr_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) == 0 && 359 (ddr_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_FORCE) != 0) || 360 ((ddr_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) != 0 && 361 (bootmode & ZY7_SLCR_BOOT_MODE_PLL_BYPASS) != 0)) 362 /* PLL is bypassed. */ 363 ddr_pll_frequency = ps_clk_frequency; 364 else 365 ddr_pll_frequency = ps_clk_frequency * 366 ((ddr_pll_ctrl & ZY7_SLCR_PLL_CTRL_FDIV_MASK) >> 367 ZY7_SLCR_PLL_CTRL_FDIV_SHIFT); 368 369 /* Determine IO PLL frequency. */ 370 if (((io_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) == 0 && 371 (io_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_FORCE) != 0) || 372 ((io_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) != 0 && 373 (bootmode & ZY7_SLCR_BOOT_MODE_PLL_BYPASS) != 0)) 374 /* PLL is bypassed. */ 375 io_pll_frequency = ps_clk_frequency; 376 else 377 io_pll_frequency = ps_clk_frequency * 378 ((io_pll_ctrl & ZY7_SLCR_PLL_CTRL_FDIV_MASK) >> 379 ZY7_SLCR_PLL_CTRL_FDIV_SHIFT); 380 381 /* Lock SLCR registers. */ 382 zy7_slcr_lock(sc); 383 384 return (0); 385 } 386 387 static int 388 zy7_slcr_detach(device_t dev) 389 { 390 struct zy7_slcr_softc *sc = device_get_softc(dev); 391 392 bus_generic_detach(dev); 393 394 /* Release memory resource. */ 395 if (sc->mem_res != NULL) 396 bus_release_resource(dev, SYS_RES_MEMORY, 397 rman_get_rid(sc->mem_res), sc->mem_res); 398 399 zy7_slcr_softc_p = NULL; 400 zynq7_cpu_reset = NULL; 401 402 ZSLCR_LOCK_DESTROY(sc); 403 404 return (0); 405 } 406 407 static device_method_t zy7_slcr_methods[] = { 408 /* device_if */ 409 DEVMETHOD(device_probe, zy7_slcr_probe), 410 DEVMETHOD(device_attach, zy7_slcr_attach), 411 DEVMETHOD(device_detach, zy7_slcr_detach), 412 413 DEVMETHOD_END 414 }; 415 416 static driver_t zy7_slcr_driver = { 417 "zy7_slcr", 418 zy7_slcr_methods, 419 sizeof(struct zy7_slcr_softc), 420 }; 421 static devclass_t zy7_slcr_devclass; 422 423 DRIVER_MODULE(zy7_slcr, simplebus, zy7_slcr_driver, zy7_slcr_devclass, 0, 0); 424 MODULE_VERSION(zy7_slcr, 1); 425