1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2013 Thomas Skibo 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Zynq-700 SLCR driver. Provides hooks for cpu_reset and PL control stuff. 31 * In the future, maybe MIO control, clock control, etc. could go here. 32 * 33 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual. 34 * (v1.4) November 16, 2012. Xilinx doc UG585. 35 */ 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/conf.h> 40 #include <sys/kernel.h> 41 #include <sys/module.h> 42 #include <sys/lock.h> 43 #include <sys/mutex.h> 44 #include <sys/resource.h> 45 #include <sys/sysctl.h> 46 #include <sys/rman.h> 47 48 #include <machine/bus.h> 49 #include <machine/resource.h> 50 #include <machine/stdarg.h> 51 52 #include <dev/ofw/ofw_bus.h> 53 #include <dev/ofw/ofw_bus_subr.h> 54 55 #include <arm/xilinx/zy7_slcr.h> 56 57 struct zy7_slcr_softc { 58 device_t dev; 59 struct mtx sc_mtx; 60 struct resource *mem_res; 61 }; 62 63 static struct zy7_slcr_softc *zy7_slcr_softc_p; 64 extern void (*zynq7_cpu_reset); 65 66 #define ZSLCR_LOCK(sc) mtx_lock(&(sc)->sc_mtx) 67 #define ZSLCR_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx) 68 #define ZSLCR_LOCK_INIT(sc) \ 69 mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev), \ 70 "zy7_slcr", MTX_DEF) 71 #define ZSLCR_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); 72 73 #define RD4(sc, off) (bus_read_4((sc)->mem_res, (off))) 74 #define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val))) 75 76 #define ZYNQ_DEFAULT_PS_CLK_FREQUENCY 33333333 /* 33.3 Mhz */ 77 78 SYSCTL_NODE(_hw, OID_AUTO, zynq, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 79 "Xilinx Zynq-7000"); 80 81 static char zynq_bootmode[64]; 82 SYSCTL_STRING(_hw_zynq, OID_AUTO, bootmode, CTLFLAG_RD, zynq_bootmode, 0, 83 "Zynq boot mode"); 84 85 static char zynq_pssid[100]; 86 SYSCTL_STRING(_hw_zynq, OID_AUTO, pssid, CTLFLAG_RD, zynq_pssid, 0, 87 "Zynq PSS IDCODE"); 88 89 static uint32_t zynq_reboot_status; 90 SYSCTL_INT(_hw_zynq, OID_AUTO, reboot_status, CTLFLAG_RD, &zynq_reboot_status, 91 0, "Zynq REBOOT_STATUS register"); 92 93 static int ps_clk_frequency; 94 SYSCTL_INT(_hw_zynq, OID_AUTO, ps_clk_frequency, CTLFLAG_RD, &ps_clk_frequency, 95 0, "Zynq PS_CLK Frequency"); 96 97 static int io_pll_frequency; 98 SYSCTL_INT(_hw_zynq, OID_AUTO, io_pll_frequency, CTLFLAG_RD, &io_pll_frequency, 99 0, "Zynq IO PLL Frequency"); 100 101 static int arm_pll_frequency; 102 SYSCTL_INT(_hw_zynq, OID_AUTO, arm_pll_frequency, CTLFLAG_RD, 103 &arm_pll_frequency, 0, "Zynq ARM PLL Frequency"); 104 105 static int ddr_pll_frequency; 106 SYSCTL_INT(_hw_zynq, OID_AUTO, ddr_pll_frequency, CTLFLAG_RD, 107 &ddr_pll_frequency, 0, "Zynq DDR PLL Frequency"); 108 109 static void 110 zy7_slcr_unlock(struct zy7_slcr_softc *sc) 111 { 112 113 /* Unlock SLCR with magic number. */ 114 WR4(sc, ZY7_SLCR_UNLOCK, ZY7_SLCR_UNLOCK_MAGIC); 115 } 116 117 static void 118 zy7_slcr_lock(struct zy7_slcr_softc *sc) 119 { 120 121 /* Lock SLCR with magic number. */ 122 WR4(sc, ZY7_SLCR_LOCK, ZY7_SLCR_LOCK_MAGIC); 123 } 124 125 static void 126 zy7_slcr_cpu_reset(void) 127 { 128 struct zy7_slcr_softc *sc = zy7_slcr_softc_p; 129 130 /* Unlock SLCR registers. */ 131 zy7_slcr_unlock(sc); 132 133 /* This has something to do with a work-around so the fsbl will load 134 * the bitstream after soft-reboot. It's very important. 135 */ 136 WR4(sc, ZY7_SLCR_REBOOT_STAT, 137 RD4(sc, ZY7_SLCR_REBOOT_STAT) & 0xf0ffffff); 138 139 /* Soft reset */ 140 WR4(sc, ZY7_SLCR_PSS_RST_CTRL, ZY7_SLCR_PSS_RST_CTRL_SOFT_RESET); 141 142 for (;;) 143 ; 144 } 145 146 /* Assert PL resets and disable level shifters in preparation of programming 147 * the PL (FPGA) section. Called from zy7_devcfg.c. 148 */ 149 void 150 zy7_slcr_preload_pl(void) 151 { 152 struct zy7_slcr_softc *sc = zy7_slcr_softc_p; 153 154 if (!sc) 155 return; 156 157 ZSLCR_LOCK(sc); 158 159 /* Unlock SLCR registers. */ 160 zy7_slcr_unlock(sc); 161 162 /* Assert top level output resets. */ 163 WR4(sc, ZY7_SLCR_FPGA_RST_CTRL, ZY7_SLCR_FPGA_RST_CTRL_RST_ALL); 164 165 /* Disable all level shifters. */ 166 WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, 0); 167 168 /* Lock SLCR registers. */ 169 zy7_slcr_lock(sc); 170 171 ZSLCR_UNLOCK(sc); 172 } 173 174 /* After PL configuration, enable level shifters and deassert top-level 175 * PL resets. Called from zy7_devcfg.c. Optionally, the level shifters 176 * can be left disabled but that's rare of an FPGA application. That option 177 * is controlled by a sysctl in the devcfg driver. 178 */ 179 void 180 zy7_slcr_postload_pl(int en_level_shifters) 181 { 182 struct zy7_slcr_softc *sc = zy7_slcr_softc_p; 183 184 if (!sc) 185 return; 186 187 ZSLCR_LOCK(sc); 188 189 /* Unlock SLCR registers. */ 190 zy7_slcr_unlock(sc); 191 192 if (en_level_shifters) 193 /* Enable level shifters. */ 194 WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, ZY7_SLCR_LVL_SHFTR_EN_ALL); 195 196 /* Deassert top level output resets. */ 197 WR4(sc, ZY7_SLCR_FPGA_RST_CTRL, 0); 198 199 /* Lock SLCR registers. */ 200 zy7_slcr_lock(sc); 201 202 ZSLCR_UNLOCK(sc); 203 } 204 205 /* Override cgem_set_refclk() in gigabit ethernet driver 206 * (sys/dev/cadence/if_cgem.c). This function is called to 207 * request a change in the gem's reference clock speed. 208 */ 209 int 210 cgem_set_ref_clk(int unit, int frequency) 211 { 212 struct zy7_slcr_softc *sc = zy7_slcr_softc_p; 213 int div0, div1; 214 215 if (!sc) 216 return (-1); 217 218 /* Find suitable divisor pairs. Round result to nearest khz 219 * to test for match. 220 */ 221 for (div1 = 1; div1 <= ZY7_SLCR_GEM_CLK_CTRL_DIVISOR1_MAX; div1++) { 222 div0 = (io_pll_frequency + div1 * frequency / 2) / 223 div1 / frequency; 224 if (div0 > 0 && div0 <= ZY7_SLCR_GEM_CLK_CTRL_DIVISOR_MAX && 225 ((io_pll_frequency / div0 / div1) + 500) / 1000 == 226 (frequency + 500) / 1000) 227 break; 228 } 229 230 if (div1 > ZY7_SLCR_GEM_CLK_CTRL_DIVISOR1_MAX) 231 return (-1); 232 233 ZSLCR_LOCK(sc); 234 235 /* Unlock SLCR registers. */ 236 zy7_slcr_unlock(sc); 237 238 /* Modify GEM reference clock. */ 239 WR4(sc, unit ? ZY7_SLCR_GEM1_CLK_CTRL : ZY7_SLCR_GEM0_CLK_CTRL, 240 (div1 << ZY7_SLCR_GEM_CLK_CTRL_DIVISOR1_SHIFT) | 241 (div0 << ZY7_SLCR_GEM_CLK_CTRL_DIVISOR_SHIFT) | 242 ZY7_SLCR_GEM_CLK_CTRL_SRCSEL_IO_PLL | 243 ZY7_SLCR_GEM_CLK_CTRL_CLKACT); 244 245 /* Lock SLCR registers. */ 246 zy7_slcr_lock(sc); 247 248 ZSLCR_UNLOCK(sc); 249 250 return (0); 251 } 252 253 /* 254 * PL clocks management function 255 */ 256 int 257 zy7_pl_fclk_set_source(int unit, int source) 258 { 259 struct zy7_slcr_softc *sc = zy7_slcr_softc_p; 260 uint32_t reg; 261 262 if (!sc) 263 return (-1); 264 265 ZSLCR_LOCK(sc); 266 267 /* Unlock SLCR registers. */ 268 zy7_slcr_unlock(sc); 269 270 /* Modify FPGAx source. */ 271 reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit)); 272 reg &= ~(ZY7_SLCR_FPGA_CLK_CTRL_SRCSEL_MASK); 273 reg |= (source << ZY7_SLCR_FPGA_CLK_CTRL_SRCSEL_SHIFT); 274 WR4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit), reg); 275 276 /* Lock SLCR registers. */ 277 zy7_slcr_lock(sc); 278 279 ZSLCR_UNLOCK(sc); 280 281 return (0); 282 } 283 284 int 285 zy7_pl_fclk_get_source(int unit) 286 { 287 struct zy7_slcr_softc *sc = zy7_slcr_softc_p; 288 uint32_t reg; 289 int source; 290 291 if (!sc) 292 return (-1); 293 294 ZSLCR_LOCK(sc); 295 296 /* Modify GEM reference clock. */ 297 reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit)); 298 source = (reg & ZY7_SLCR_FPGA_CLK_CTRL_SRCSEL_MASK) >> 299 ZY7_SLCR_FPGA_CLK_CTRL_SRCSEL_SHIFT; 300 301 /* ZY7_PL_FCLK_SRC_IO is actually b0x */ 302 if ((source & 2) == 0) 303 source = ZY7_PL_FCLK_SRC_IO; 304 305 ZSLCR_UNLOCK(sc); 306 307 return (source); 308 } 309 310 int 311 zy7_pl_fclk_set_freq(int unit, int frequency) 312 { 313 struct zy7_slcr_softc *sc = zy7_slcr_softc_p; 314 int div0, div1; 315 int base_frequency; 316 uint32_t reg; 317 int source; 318 319 if (!sc) 320 return (-1); 321 322 source = zy7_pl_fclk_get_source(unit); 323 switch (source) { 324 case ZY7_PL_FCLK_SRC_IO: 325 base_frequency = io_pll_frequency; 326 break; 327 328 case ZY7_PL_FCLK_SRC_ARM: 329 base_frequency = arm_pll_frequency; 330 break; 331 332 case ZY7_PL_FCLK_SRC_DDR: 333 base_frequency = ddr_pll_frequency; 334 break; 335 336 default: 337 return (-1); 338 } 339 340 /* Find suitable divisor pairs. Round result to nearest khz 341 * to test for match. 342 */ 343 for (div1 = 1; div1 <= ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR_MAX; div1++) { 344 div0 = (base_frequency + div1 * frequency / 2) / 345 div1 / frequency; 346 if (div0 > 0 && div0 <= ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR_MAX && 347 ((base_frequency / div0 / div1) + 500) / 1000 == 348 (frequency + 500) / 1000) 349 break; 350 } 351 352 if (div1 > ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR_MAX) 353 return (-1); 354 355 ZSLCR_LOCK(sc); 356 357 /* Unlock SLCR registers. */ 358 zy7_slcr_unlock(sc); 359 360 /* Modify FPGAx reference clock. */ 361 reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit)); 362 reg &= ~(ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR1_MASK | 363 ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR0_MASK); 364 reg |= (div1 << ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR1_SHIFT) | 365 (div0 << ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR0_SHIFT); 366 WR4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit), reg); 367 368 /* Lock SLCR registers. */ 369 zy7_slcr_lock(sc); 370 371 ZSLCR_UNLOCK(sc); 372 373 return (base_frequency / div0 / div1); 374 } 375 376 int 377 zy7_pl_fclk_get_freq(int unit) 378 { 379 struct zy7_slcr_softc *sc = zy7_slcr_softc_p; 380 int div0, div1; 381 int base_frequency; 382 int frequency; 383 uint32_t reg; 384 int source; 385 386 if (!sc) 387 return (-1); 388 389 source = zy7_pl_fclk_get_source(unit); 390 switch (source) { 391 case ZY7_PL_FCLK_SRC_IO: 392 base_frequency = io_pll_frequency; 393 break; 394 395 case ZY7_PL_FCLK_SRC_ARM: 396 base_frequency = arm_pll_frequency; 397 break; 398 399 case ZY7_PL_FCLK_SRC_DDR: 400 base_frequency = ddr_pll_frequency; 401 break; 402 403 default: 404 return (-1); 405 } 406 407 ZSLCR_LOCK(sc); 408 409 /* Modify FPGAx reference clock. */ 410 reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit)); 411 div1 = (reg & ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR1_MASK) >> 412 ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR1_SHIFT; 413 div0 = (reg & ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR0_MASK) >> 414 ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR0_SHIFT; 415 416 ZSLCR_UNLOCK(sc); 417 418 if (div0 == 0) 419 div0 = 1; 420 421 if (div1 == 0) 422 div1 = 1; 423 424 frequency = (base_frequency / div0 / div1); 425 /* Round to KHz */ 426 frequency = (frequency + 500) / 1000; 427 frequency = frequency * 1000; 428 429 return (frequency); 430 } 431 432 int 433 zy7_pl_fclk_enable(int unit) 434 { 435 struct zy7_slcr_softc *sc = zy7_slcr_softc_p; 436 437 if (!sc) 438 return (-1); 439 440 ZSLCR_LOCK(sc); 441 442 /* Unlock SLCR registers. */ 443 zy7_slcr_unlock(sc); 444 445 WR4(sc, ZY7_SLCR_FPGA_THR_CTRL(unit), 0); 446 WR4(sc, ZY7_SLCR_FPGA_THR_CNT(unit), 0); 447 448 /* Lock SLCR registers. */ 449 zy7_slcr_lock(sc); 450 451 ZSLCR_UNLOCK(sc); 452 453 return (0); 454 } 455 456 int 457 zy7_pl_fclk_disable(int unit) 458 { 459 struct zy7_slcr_softc *sc = zy7_slcr_softc_p; 460 461 if (!sc) 462 return (-1); 463 464 ZSLCR_LOCK(sc); 465 466 /* Unlock SLCR registers. */ 467 zy7_slcr_unlock(sc); 468 469 WR4(sc, ZY7_SLCR_FPGA_THR_CTRL(unit), 0); 470 WR4(sc, ZY7_SLCR_FPGA_THR_CNT(unit), 1); 471 472 /* Lock SLCR registers. */ 473 zy7_slcr_lock(sc); 474 475 ZSLCR_UNLOCK(sc); 476 477 return (0); 478 } 479 480 int 481 zy7_pl_fclk_enabled(int unit) 482 { 483 struct zy7_slcr_softc *sc = zy7_slcr_softc_p; 484 uint32_t reg; 485 486 if (!sc) 487 return (-1); 488 489 ZSLCR_LOCK(sc); 490 reg = RD4(sc, ZY7_SLCR_FPGA_THR_CNT(unit)); 491 ZSLCR_UNLOCK(sc); 492 493 return !(reg & 1); 494 } 495 496 int 497 zy7_pl_level_shifters_enabled(void) 498 { 499 struct zy7_slcr_softc *sc = zy7_slcr_softc_p; 500 501 uint32_t reg; 502 503 if (!sc) 504 return (-1); 505 506 ZSLCR_LOCK(sc); 507 reg = RD4(sc, ZY7_SLCR_LVL_SHFTR_EN); 508 ZSLCR_UNLOCK(sc); 509 510 return (reg == ZY7_SLCR_LVL_SHFTR_EN_ALL); 511 } 512 513 void 514 zy7_pl_level_shifters_enable(void) 515 { 516 struct zy7_slcr_softc *sc = zy7_slcr_softc_p; 517 518 if (!sc) 519 return; 520 521 ZSLCR_LOCK(sc); 522 zy7_slcr_unlock(sc); 523 WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, ZY7_SLCR_LVL_SHFTR_EN_ALL); 524 zy7_slcr_lock(sc); 525 ZSLCR_UNLOCK(sc); 526 } 527 528 void 529 zy7_pl_level_shifters_disable(void) 530 { 531 struct zy7_slcr_softc *sc = zy7_slcr_softc_p; 532 533 if (!sc) 534 return; 535 536 ZSLCR_LOCK(sc); 537 zy7_slcr_unlock(sc); 538 WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, 0); 539 zy7_slcr_lock(sc); 540 ZSLCR_UNLOCK(sc); 541 } 542 543 static int 544 zy7_slcr_probe(device_t dev) 545 { 546 547 if (!ofw_bus_status_okay(dev)) 548 return (ENXIO); 549 550 if (!ofw_bus_is_compatible(dev, "xlnx,zy7_slcr")) 551 return (ENXIO); 552 553 device_set_desc(dev, "Zynq-7000 slcr block"); 554 return (0); 555 } 556 557 static int 558 zy7_slcr_attach(device_t dev) 559 { 560 struct zy7_slcr_softc *sc = device_get_softc(dev); 561 int rid; 562 phandle_t node; 563 pcell_t cell; 564 uint32_t bootmode; 565 uint32_t pss_idcode; 566 uint32_t arm_pll_ctrl; 567 uint32_t ddr_pll_ctrl; 568 uint32_t io_pll_ctrl; 569 static char *bootdev_names[] = { 570 "JTAG", "Quad-SPI", "NOR", "(3?)", 571 "NAND", "SD Card", "(6?)", "(7?)" 572 }; 573 574 /* Allow only one attach. */ 575 if (zy7_slcr_softc_p != NULL) 576 return (ENXIO); 577 578 sc->dev = dev; 579 580 ZSLCR_LOCK_INIT(sc); 581 582 /* Get memory resource. */ 583 rid = 0; 584 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 585 RF_ACTIVE); 586 if (sc->mem_res == NULL) { 587 device_printf(dev, "could not allocate memory resources.\n"); 588 return (ENOMEM); 589 } 590 591 /* Hook up cpu_reset. */ 592 zy7_slcr_softc_p = sc; 593 zynq7_cpu_reset = zy7_slcr_cpu_reset; 594 595 /* Read info and set sysctls. */ 596 bootmode = RD4(sc, ZY7_SLCR_BOOT_MODE); 597 snprintf(zynq_bootmode, sizeof(zynq_bootmode), 598 "0x%x: boot device: %s", bootmode, 599 bootdev_names[bootmode & ZY7_SLCR_BOOT_MODE_BOOTDEV_MASK]); 600 601 pss_idcode = RD4(sc, ZY7_SLCR_PSS_IDCODE); 602 snprintf(zynq_pssid, sizeof(zynq_pssid), 603 "0x%x: manufacturer: 0x%x device: 0x%x " 604 "family: 0x%x sub-family: 0x%x rev: 0x%x", 605 pss_idcode, 606 (pss_idcode & ZY7_SLCR_PSS_IDCODE_MNFR_ID_MASK) >> 607 ZY7_SLCR_PSS_IDCODE_MNFR_ID_SHIFT, 608 (pss_idcode & ZY7_SLCR_PSS_IDCODE_DEVICE_MASK) >> 609 ZY7_SLCR_PSS_IDCODE_DEVICE_SHIFT, 610 (pss_idcode & ZY7_SLCR_PSS_IDCODE_FAMILY_MASK) >> 611 ZY7_SLCR_PSS_IDCODE_FAMILY_SHIFT, 612 (pss_idcode & ZY7_SLCR_PSS_IDCODE_SUB_FAMILY_MASK) >> 613 ZY7_SLCR_PSS_IDCODE_SUB_FAMILY_SHIFT, 614 (pss_idcode & ZY7_SLCR_PSS_IDCODE_REVISION_MASK) >> 615 ZY7_SLCR_PSS_IDCODE_REVISION_SHIFT); 616 617 zynq_reboot_status = RD4(sc, ZY7_SLCR_REBOOT_STAT); 618 619 /* Derive PLL frequencies from PS_CLK. */ 620 node = ofw_bus_get_node(dev); 621 if (OF_getencprop(node, "clock-frequency", &cell, sizeof(cell)) > 0) 622 ps_clk_frequency = cell; 623 else 624 ps_clk_frequency = ZYNQ_DEFAULT_PS_CLK_FREQUENCY; 625 626 arm_pll_ctrl = RD4(sc, ZY7_SLCR_ARM_PLL_CTRL); 627 ddr_pll_ctrl = RD4(sc, ZY7_SLCR_DDR_PLL_CTRL); 628 io_pll_ctrl = RD4(sc, ZY7_SLCR_IO_PLL_CTRL); 629 630 /* Determine ARM PLL frequency. */ 631 if (((arm_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) == 0 && 632 (arm_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_FORCE) != 0) || 633 ((arm_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) != 0 && 634 (bootmode & ZY7_SLCR_BOOT_MODE_PLL_BYPASS) != 0)) 635 /* PLL is bypassed. */ 636 arm_pll_frequency = ps_clk_frequency; 637 else 638 arm_pll_frequency = ps_clk_frequency * 639 ((arm_pll_ctrl & ZY7_SLCR_PLL_CTRL_FDIV_MASK) >> 640 ZY7_SLCR_PLL_CTRL_FDIV_SHIFT); 641 642 /* Determine DDR PLL frequency. */ 643 if (((ddr_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) == 0 && 644 (ddr_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_FORCE) != 0) || 645 ((ddr_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) != 0 && 646 (bootmode & ZY7_SLCR_BOOT_MODE_PLL_BYPASS) != 0)) 647 /* PLL is bypassed. */ 648 ddr_pll_frequency = ps_clk_frequency; 649 else 650 ddr_pll_frequency = ps_clk_frequency * 651 ((ddr_pll_ctrl & ZY7_SLCR_PLL_CTRL_FDIV_MASK) >> 652 ZY7_SLCR_PLL_CTRL_FDIV_SHIFT); 653 654 /* Determine IO PLL frequency. */ 655 if (((io_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) == 0 && 656 (io_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_FORCE) != 0) || 657 ((io_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) != 0 && 658 (bootmode & ZY7_SLCR_BOOT_MODE_PLL_BYPASS) != 0)) 659 /* PLL is bypassed. */ 660 io_pll_frequency = ps_clk_frequency; 661 else 662 io_pll_frequency = ps_clk_frequency * 663 ((io_pll_ctrl & ZY7_SLCR_PLL_CTRL_FDIV_MASK) >> 664 ZY7_SLCR_PLL_CTRL_FDIV_SHIFT); 665 666 /* Lock SLCR registers. */ 667 zy7_slcr_lock(sc); 668 669 return (0); 670 } 671 672 static int 673 zy7_slcr_detach(device_t dev) 674 { 675 struct zy7_slcr_softc *sc = device_get_softc(dev); 676 677 bus_generic_detach(dev); 678 679 /* Release memory resource. */ 680 if (sc->mem_res != NULL) 681 bus_release_resource(dev, SYS_RES_MEMORY, 682 rman_get_rid(sc->mem_res), sc->mem_res); 683 684 zy7_slcr_softc_p = NULL; 685 zynq7_cpu_reset = NULL; 686 687 ZSLCR_LOCK_DESTROY(sc); 688 689 return (0); 690 } 691 692 static device_method_t zy7_slcr_methods[] = { 693 /* device_if */ 694 DEVMETHOD(device_probe, zy7_slcr_probe), 695 DEVMETHOD(device_attach, zy7_slcr_attach), 696 DEVMETHOD(device_detach, zy7_slcr_detach), 697 698 DEVMETHOD_END 699 }; 700 701 static driver_t zy7_slcr_driver = { 702 "zy7_slcr", 703 zy7_slcr_methods, 704 sizeof(struct zy7_slcr_softc), 705 }; 706 707 DRIVER_MODULE(zy7_slcr, simplebus, zy7_slcr_driver, 0, 0); 708 MODULE_VERSION(zy7_slcr, 1); 709