1 /*- 2 * Copyright (c) 2013 Thomas Skibo 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 /* 30 * Zynq-700 SLCR driver. Provides hooks for cpu_reset and PL control stuff. 31 * In the future, maybe MIO control, clock control, etc. could go here. 32 * 33 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual. 34 * (v1.4) November 16, 2012. Xilinx doc UG585. 35 */ 36 37 #include <sys/cdefs.h> 38 __FBSDID("$FreeBSD$"); 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/conf.h> 43 #include <sys/kernel.h> 44 #include <sys/module.h> 45 #include <sys/lock.h> 46 #include <sys/mutex.h> 47 #include <sys/resource.h> 48 #include <sys/sysctl.h> 49 #include <sys/rman.h> 50 51 #include <machine/bus.h> 52 #include <machine/resource.h> 53 #include <machine/stdarg.h> 54 55 #include <dev/fdt/fdt_common.h> 56 #include <dev/ofw/ofw_bus.h> 57 #include <dev/ofw/ofw_bus_subr.h> 58 59 #include <arm/xilinx/zy7_slcr.h> 60 61 struct zy7_slcr_softc { 62 device_t dev; 63 struct mtx sc_mtx; 64 struct resource *mem_res; 65 }; 66 67 static struct zy7_slcr_softc *zy7_slcr_softc_p; 68 extern void (*zynq7_cpu_reset); 69 70 #define ZSLCR_LOCK(sc) mtx_lock(&(sc)->sc_mtx) 71 #define ZSLCR_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx) 72 #define ZSLCR_LOCK_INIT(sc) \ 73 mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev), \ 74 "zy7_slcr", MTX_SPIN) 75 #define ZSLCR_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); 76 77 #define RD4(sc, off) (bus_read_4((sc)->mem_res, (off))) 78 #define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val))) 79 80 81 SYSCTL_NODE(_hw, OID_AUTO, zynq, CTLFLAG_RD, 0, "Xilinx Zynq-7000"); 82 83 static char zynq_bootmode[64]; 84 SYSCTL_STRING(_hw_zynq, OID_AUTO, bootmode, CTLFLAG_RD, zynq_bootmode, 0, 85 "Zynq boot mode"); 86 87 static char zynq_pssid[80]; 88 SYSCTL_STRING(_hw_zynq, OID_AUTO, pssid, CTLFLAG_RD, zynq_pssid, 0, 89 "Zynq PSS IDCODE"); 90 91 static uint32_t zynq_reboot_status; 92 SYSCTL_INT(_hw_zynq, OID_AUTO, reboot_status, CTLFLAG_RD, &zynq_reboot_status, 93 0, "Zynq REBOOT_STATUS register"); 94 95 static void 96 zy7_slcr_unlock(struct zy7_slcr_softc *sc) 97 { 98 99 /* Unlock SLCR with magic number. */ 100 WR4(sc, ZY7_SLCR_UNLOCK, ZY7_SLCR_UNLOCK_MAGIC); 101 } 102 103 static void 104 zy7_slcr_lock(struct zy7_slcr_softc *sc) 105 { 106 107 /* Lock SLCR with magic number. */ 108 WR4(sc, ZY7_SLCR_LOCK, ZY7_SLCR_LOCK_MAGIC); 109 } 110 111 112 static void 113 zy7_slcr_cpu_reset(void) 114 { 115 struct zy7_slcr_softc *sc = zy7_slcr_softc_p; 116 117 /* Unlock SLCR registers. */ 118 zy7_slcr_unlock(sc); 119 120 /* This has something to do with a work-around so the fsbl will load 121 * the bitstream after soft-reboot. It's very important. 122 */ 123 WR4(sc, ZY7_SLCR_REBOOT_STAT, 124 RD4(sc, ZY7_SLCR_REBOOT_STAT) & 0xf0ffffff); 125 126 /* Soft reset */ 127 WR4(sc, ZY7_SLCR_PSS_RST_CTRL, ZY7_SLCR_PSS_RST_CTRL_SOFT_RESET); 128 129 for (;;) 130 ; 131 } 132 133 /* Assert PL resets and disable level shifters in preparation of programming 134 * the PL (FPGA) section. Called from zy7_devcfg.c. 135 */ 136 void 137 zy7_slcr_preload_pl(void) 138 { 139 struct zy7_slcr_softc *sc = zy7_slcr_softc_p; 140 141 if (!sc) 142 return; 143 144 ZSLCR_LOCK(sc); 145 146 /* Unlock SLCR registers. */ 147 zy7_slcr_unlock(sc); 148 149 /* Assert top level output resets. */ 150 WR4(sc, ZY7_SLCR_FPGA_RST_CTRL, ZY7_SLCR_FPGA_RST_CTRL_RST_ALL); 151 152 /* Disable all level shifters. */ 153 WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, 0); 154 155 /* Lock SLCR registers. */ 156 zy7_slcr_lock(sc); 157 158 ZSLCR_UNLOCK(sc); 159 } 160 161 /* After PL configuration, enable level shifters and deassert top-level 162 * PL resets. Called from zy7_devcfg.c. Optionally, the level shifters 163 * can be left disabled but that's rare of an FPGA application. That option 164 * is controled by a sysctl in the devcfg driver. 165 */ 166 void 167 zy7_slcr_postload_pl(int en_level_shifters) 168 { 169 struct zy7_slcr_softc *sc = zy7_slcr_softc_p; 170 171 if (!sc) 172 return; 173 174 ZSLCR_LOCK(sc); 175 176 /* Unlock SLCR registers. */ 177 zy7_slcr_unlock(sc); 178 179 if (en_level_shifters) 180 /* Enable level shifters. */ 181 WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, ZY7_SLCR_LVL_SHFTR_EN_ALL); 182 183 /* Deassert top level output resets. */ 184 WR4(sc, ZY7_SLCR_FPGA_RST_CTRL, 0); 185 186 /* Lock SLCR registers. */ 187 zy7_slcr_lock(sc); 188 189 ZSLCR_UNLOCK(sc); 190 } 191 192 static int 193 zy7_slcr_probe(device_t dev) 194 { 195 196 if (!ofw_bus_status_okay(dev)) 197 return (ENXIO); 198 199 if (!ofw_bus_is_compatible(dev, "xlnx,zy7_slcr")) 200 return (ENXIO); 201 202 device_set_desc(dev, "Zynq-7000 slcr block"); 203 return (0); 204 } 205 206 static int 207 zy7_slcr_attach(device_t dev) 208 { 209 struct zy7_slcr_softc *sc = device_get_softc(dev); 210 int rid; 211 uint32_t bootmode; 212 uint32_t pss_idcode; 213 static char *bootdev_names[] = { 214 "JTAG", "Quad-SPI", "NOR", "(3?)", 215 "NAND", "SD Card", "(6?)", "(7?)" 216 }; 217 218 /* Allow only one attach. */ 219 if (zy7_slcr_softc_p != NULL) 220 return (ENXIO); 221 222 sc->dev = dev; 223 224 ZSLCR_LOCK_INIT(sc); 225 226 /* Get memory resource. */ 227 rid = 0; 228 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 229 RF_ACTIVE); 230 if (sc->mem_res == NULL) { 231 device_printf(dev, "could not allocate memory resources.\n"); 232 return (ENOMEM); 233 } 234 235 /* Hook up cpu_reset. */ 236 zy7_slcr_softc_p = sc; 237 zynq7_cpu_reset = zy7_slcr_cpu_reset; 238 239 /* Read info and set sysctls. */ 240 bootmode = RD4(sc, ZY7_SLCR_BOOT_MODE); 241 snprintf(zynq_bootmode, sizeof(zynq_bootmode), 242 "0x%x: boot device: %s", bootmode, 243 bootdev_names[bootmode & ZY7_SLCR_BOOT_MODE_BOOTDEV_MASK]); 244 245 pss_idcode = RD4(sc, ZY7_SLCR_PSS_IDCODE); 246 snprintf(zynq_pssid, sizeof(zynq_pssid), 247 "0x%x: manufacturer: 0x%x device: 0x%x " 248 "family: 0x%x sub-family: 0x%x rev: 0x%x", 249 pss_idcode, 250 (pss_idcode & ZY7_SLCR_PSS_IDCODE_MNFR_ID_MASK) >> 251 ZY7_SLCR_PSS_IDCODE_MNFR_ID_SHIFT, 252 (pss_idcode & ZY7_SLCR_PSS_IDCODE_DEVICE_MASK) >> 253 ZY7_SLCR_PSS_IDCODE_DEVICE_SHIFT, 254 (pss_idcode & ZY7_SLCR_PSS_IDCODE_FAMILY_MASK) >> 255 ZY7_SLCR_PSS_IDCODE_FAMILY_SHIFT, 256 (pss_idcode & ZY7_SLCR_PSS_IDCODE_SUB_FAMILY_MASK) >> 257 ZY7_SLCR_PSS_IDCODE_SUB_FAMILY_SHIFT, 258 (pss_idcode & ZY7_SLCR_PSS_IDCODE_REVISION_MASK) >> 259 ZY7_SLCR_PSS_IDCODE_REVISION_SHIFT); 260 261 zynq_reboot_status = RD4(sc, ZY7_SLCR_REBOOT_STAT); 262 263 /* Lock SLCR registers. */ 264 zy7_slcr_lock(sc); 265 266 return (0); 267 } 268 269 static int 270 zy7_slcr_detach(device_t dev) 271 { 272 struct zy7_slcr_softc *sc = device_get_softc(dev); 273 274 bus_generic_detach(dev); 275 276 /* Release memory resource. */ 277 if (sc->mem_res != NULL) 278 bus_release_resource(dev, SYS_RES_MEMORY, 279 rman_get_rid(sc->mem_res), sc->mem_res); 280 281 zy7_slcr_softc_p = NULL; 282 zynq7_cpu_reset = NULL; 283 284 ZSLCR_LOCK_DESTROY(sc); 285 286 return (0); 287 } 288 289 static device_method_t zy7_slcr_methods[] = { 290 /* device_if */ 291 DEVMETHOD(device_probe, zy7_slcr_probe), 292 DEVMETHOD(device_attach, zy7_slcr_attach), 293 DEVMETHOD(device_detach, zy7_slcr_detach), 294 295 DEVMETHOD_END 296 }; 297 298 static driver_t zy7_slcr_driver = { 299 "zy7_slcr", 300 zy7_slcr_methods, 301 sizeof(struct zy7_slcr_softc), 302 }; 303 static devclass_t zy7_slcr_devclass; 304 305 DRIVER_MODULE(zy7_slcr, simplebus, zy7_slcr_driver, zy7_slcr_devclass, 0, 0); 306 MODULE_VERSION(zy7_slcr, 1); 307