1 /*- 2 * Copyright (c) 2013 Thomas Skibo. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23 */ 24 25 #include <sys/cdefs.h> 26 __FBSDID("$FreeBSD$"); 27 #include <sys/param.h> 28 #include <sys/systm.h> 29 #include <sys/bus.h> 30 #include <sys/lock.h> 31 #include <sys/mutex.h> 32 #include <sys/smp.h> 33 34 #include <machine/smp.h> 35 #include <machine/fdt.h> 36 #include <machine/intr.h> 37 38 #include <arm/xilinx/zy7_reg.h> 39 40 #define ZYNQ7_CPU1_ENTRY 0xfffffff0 41 42 void 43 platform_mp_init_secondary(void) 44 { 45 46 gic_init_secondary(); 47 } 48 49 void 50 platform_mp_setmaxid(void) 51 { 52 53 mp_maxid = 1; 54 } 55 56 int 57 platform_mp_probe(void) 58 { 59 60 mp_ncpus = 2; 61 return (1); 62 } 63 64 void 65 platform_mp_start_ap(void) 66 { 67 bus_space_handle_t ocm_handle; 68 69 /* Map in magic location to give entry address to CPU1. */ 70 if (bus_space_map(fdtbus_bs_tag, ZYNQ7_CPU1_ENTRY, 4, 71 0, &ocm_handle) != 0) 72 panic("platform_mp_start_ap: Couldn't map OCM\n"); 73 74 /* Write start address for CPU1. */ 75 bus_space_write_4(fdtbus_bs_tag, ocm_handle, 0, 76 pmap_kextract((vm_offset_t)mpentry)); 77 78 /* 79 * The SCU is enabled by the BOOTROM but I think the second CPU doesn't 80 * turn on filtering until after the wake-up below. I think that's why 81 * things don't work if I don't put these cache ops here. Also, the 82 * magic location, 0xfffffff0, isn't in the SCU's filtering range so it 83 * needs a write-back too. 84 */ 85 cpu_idcache_wbinv_all(); 86 cpu_l2cache_wbinv_all(); 87 88 /* Wake up CPU1. */ 89 armv7_sev(); 90 91 bus_space_unmap(fdtbus_bs_tag, ocm_handle, 4); 92 } 93 94 void 95 platform_ipi_send(cpuset_t cpus, u_int ipi) 96 { 97 98 pic_ipi_send(cpus, ipi); 99 } 100