1 /*-
2 * Copyright (c) 2013 Thomas Skibo. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 */
24
25 #include "opt_platform.h"
26
27 #include <sys/param.h>
28 #include <sys/systm.h>
29 #include <sys/bus.h>
30 #include <sys/lock.h>
31 #include <sys/mutex.h>
32 #include <sys/smp.h>
33
34 #include <vm/vm.h>
35 #include <vm/pmap.h>
36
37 #include <machine/cpu.h>
38 #include <machine/smp.h>
39 #include <machine/fdt.h>
40 #include <machine/intr.h>
41 #include <machine/platformvar.h>
42
43 #include <arm/xilinx/zy7_machdep.h>
44 #include <arm/xilinx/zy7_reg.h>
45 #include <arm/xilinx/zy7_slcr.h>
46
47 #define ZYNQ7_CPU1_ENTRY 0xfffffff0
48
49 #define SCU_CONTROL_REG 0xf8f00000
50 #define SCU_CONTROL_ENABLE 1
51 #define SCU_CONFIG_REG 0xf8f00004
52 #define SCU_CONFIG_N_CPUS_MASK 3
53
54 #define SLCR_PSS_IDCODE 0xf8000530
55
56 void
zynq7_mp_setmaxid(platform_t plat)57 zynq7_mp_setmaxid(platform_t plat)
58 {
59 bus_space_handle_t slcr_handle;
60 int device_id;
61 bus_space_handle_t scu_handle;
62
63 if (mp_ncpus != 0)
64 return;
65
66 /* Map in SLCR PSS_IDCODE register. */
67 if (bus_space_map(fdtbus_bs_tag, SLCR_PSS_IDCODE, 4, 0,
68 &slcr_handle) != 0)
69 panic("%s: Could not map SLCR IDCODE reg.\n", __func__);
70
71 device_id = bus_space_read_4(fdtbus_bs_tag, slcr_handle, 0) &
72 ZY7_SLCR_PSS_IDCODE_DEVICE_MASK;
73
74 bus_space_unmap(fdtbus_bs_tag, slcr_handle, 4);
75
76 /*
77 * Zynq XC7z0xxS single core chips indicate incorrect number of CPUs in
78 * SCU configuration register.
79 */
80 if (device_id == ZY7_SLCR_PSS_IDCODE_DEVICE_7Z007S ||
81 device_id == ZY7_SLCR_PSS_IDCODE_DEVICE_7Z012S ||
82 device_id == ZY7_SLCR_PSS_IDCODE_DEVICE_7Z014S) {
83 mp_maxid = 0;
84 mp_ncpus = 1;
85 return;
86 }
87
88 /* Map in SCU config register. */
89 if (bus_space_map(fdtbus_bs_tag, SCU_CONFIG_REG, 4, 0,
90 &scu_handle) != 0)
91 panic("zynq7_mp_setmaxid: Could not map SCU config reg.\n");
92
93 mp_maxid = bus_space_read_4(fdtbus_bs_tag, scu_handle, 0) &
94 SCU_CONFIG_N_CPUS_MASK;
95 mp_ncpus = mp_maxid + 1;
96
97 bus_space_unmap(fdtbus_bs_tag, scu_handle, 4);
98 }
99
100 void
zynq7_mp_start_ap(platform_t plat)101 zynq7_mp_start_ap(platform_t plat)
102 {
103 bus_space_handle_t scu_handle;
104 bus_space_handle_t ocm_handle;
105 uint32_t scu_ctrl;
106
107 /* Map in SCU control register. */
108 if (bus_space_map(fdtbus_bs_tag, SCU_CONTROL_REG, 4,
109 0, &scu_handle) != 0)
110 panic("%s: Could not map SCU control reg.\n", __func__);
111
112 /* Set SCU enable bit. */
113 scu_ctrl = bus_space_read_4(fdtbus_bs_tag, scu_handle, 0);
114 scu_ctrl |= SCU_CONTROL_ENABLE;
115 bus_space_write_4(fdtbus_bs_tag, scu_handle, 0, scu_ctrl);
116
117 bus_space_unmap(fdtbus_bs_tag, scu_handle, 4);
118
119 /* Map in magic location to give entry address to CPU1. */
120 if (bus_space_map(fdtbus_bs_tag, ZYNQ7_CPU1_ENTRY, 4,
121 0, &ocm_handle) != 0)
122 panic("%s: Could not map OCM\n", __func__);
123
124 /* Write start address for CPU1. */
125 bus_space_write_4(fdtbus_bs_tag, ocm_handle, 0,
126 pmap_kextract((vm_offset_t)mpentry));
127
128 bus_space_unmap(fdtbus_bs_tag, ocm_handle, 4);
129
130 /*
131 * The SCU is enabled above but I think the second CPU doesn't
132 * turn on filtering until after the wake-up below. I think that's why
133 * things don't work if I don't put these cache ops here. Also, the
134 * magic location, 0xfffffff0, isn't in the SCU's filtering range so it
135 * needs a write-back too.
136 */
137 dcache_wbinv_poc_all();
138
139 /* Wake up CPU1. */
140 dsb();
141 sev();
142 }
143