106177e52SIan Lepore /*- 206177e52SIan Lepore * Copyright (c) 2013 Thomas Skibo. All rights reserved. 306177e52SIan Lepore * 406177e52SIan Lepore * Redistribution and use in source and binary forms, with or without 506177e52SIan Lepore * modification, are permitted provided that the following conditions 606177e52SIan Lepore * are met: 706177e52SIan Lepore * 1. Redistributions of source code must retain the above copyright 806177e52SIan Lepore * notice, this list of conditions and the following disclaimer. 906177e52SIan Lepore * 2. Redistributions in binary form must reproduce the above copyright 1006177e52SIan Lepore * notice, this list of conditions and the following disclaimer in the 1106177e52SIan Lepore * documentation and/or other materials provided with the distribution. 1206177e52SIan Lepore * 1306177e52SIan Lepore * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 1406177e52SIan Lepore * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 1506177e52SIan Lepore * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 1606177e52SIan Lepore * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 1706177e52SIan Lepore * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 1806177e52SIan Lepore * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 1906177e52SIan Lepore * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2006177e52SIan Lepore * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2106177e52SIan Lepore * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 2206177e52SIan Lepore * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2306177e52SIan Lepore */ 2406177e52SIan Lepore 2506177e52SIan Lepore #include <sys/cdefs.h> 2606177e52SIan Lepore __FBSDID("$FreeBSD$"); 2706177e52SIan Lepore #include <sys/param.h> 2806177e52SIan Lepore #include <sys/systm.h> 2906177e52SIan Lepore #include <sys/bus.h> 3006177e52SIan Lepore #include <sys/lock.h> 3106177e52SIan Lepore #include <sys/mutex.h> 3206177e52SIan Lepore #include <sys/smp.h> 3306177e52SIan Lepore 34087af50aSAndrew Turner #include <vm/vm.h> 35087af50aSAndrew Turner #include <vm/pmap.h> 36087af50aSAndrew Turner 37a89156f5SMichal Meloun #include <machine/cpu.h> 3806177e52SIan Lepore #include <machine/smp.h> 3906177e52SIan Lepore #include <machine/fdt.h> 4006177e52SIan Lepore #include <machine/intr.h> 4106177e52SIan Lepore 4206177e52SIan Lepore #include <arm/xilinx/zy7_reg.h> 4306177e52SIan Lepore 4406177e52SIan Lepore #define ZYNQ7_CPU1_ENTRY 0xfffffff0 4506177e52SIan Lepore 4697665af9SIan Lepore #define SCU_CONTROL_REG 0xf8f00000 4797665af9SIan Lepore #define SCU_CONTROL_ENABLE (1 << 0) 4897665af9SIan Lepore 4906177e52SIan Lepore void 5006177e52SIan Lepore platform_mp_setmaxid(void) 5106177e52SIan Lepore { 5206177e52SIan Lepore 5306177e52SIan Lepore mp_maxid = 1; 5427f38a8dSTijl Coosemans mp_ncpus = 2; 5506177e52SIan Lepore } 5606177e52SIan Lepore 5706177e52SIan Lepore void 5806177e52SIan Lepore platform_mp_start_ap(void) 5906177e52SIan Lepore { 6097665af9SIan Lepore bus_space_handle_t scu_handle; 6106177e52SIan Lepore bus_space_handle_t ocm_handle; 6297665af9SIan Lepore uint32_t scu_ctrl; 6397665af9SIan Lepore 6497665af9SIan Lepore /* Map in SCU control register. */ 6597665af9SIan Lepore if (bus_space_map(fdtbus_bs_tag, SCU_CONTROL_REG, 4, 6697665af9SIan Lepore 0, &scu_handle) != 0) 6797665af9SIan Lepore panic("platform_mp_start_ap: Couldn't map SCU config reg\n"); 6897665af9SIan Lepore 6997665af9SIan Lepore /* Set SCU enable bit. */ 7097665af9SIan Lepore scu_ctrl = bus_space_read_4(fdtbus_bs_tag, scu_handle, 0); 7197665af9SIan Lepore scu_ctrl |= SCU_CONTROL_ENABLE; 7297665af9SIan Lepore bus_space_write_4(fdtbus_bs_tag, scu_handle, 0, scu_ctrl); 7397665af9SIan Lepore 7497665af9SIan Lepore bus_space_unmap(fdtbus_bs_tag, scu_handle, 4); 7506177e52SIan Lepore 7606177e52SIan Lepore /* Map in magic location to give entry address to CPU1. */ 7706177e52SIan Lepore if (bus_space_map(fdtbus_bs_tag, ZYNQ7_CPU1_ENTRY, 4, 7806177e52SIan Lepore 0, &ocm_handle) != 0) 7906177e52SIan Lepore panic("platform_mp_start_ap: Couldn't map OCM\n"); 8006177e52SIan Lepore 8106177e52SIan Lepore /* Write start address for CPU1. */ 8206177e52SIan Lepore bus_space_write_4(fdtbus_bs_tag, ocm_handle, 0, 8306177e52SIan Lepore pmap_kextract((vm_offset_t)mpentry)); 8406177e52SIan Lepore 8597665af9SIan Lepore bus_space_unmap(fdtbus_bs_tag, ocm_handle, 4); 8697665af9SIan Lepore 8706177e52SIan Lepore /* 8897665af9SIan Lepore * The SCU is enabled above but I think the second CPU doesn't 8906177e52SIan Lepore * turn on filtering until after the wake-up below. I think that's why 9006177e52SIan Lepore * things don't work if I don't put these cache ops here. Also, the 9106177e52SIan Lepore * magic location, 0xfffffff0, isn't in the SCU's filtering range so it 9206177e52SIan Lepore * needs a write-back too. 9306177e52SIan Lepore */ 94a89156f5SMichal Meloun dcache_wbinv_poc_all(); 9506177e52SIan Lepore 9606177e52SIan Lepore /* Wake up CPU1. */ 97*7cc70732SMichal Meloun dsb(); 98*7cc70732SMichal Meloun sev(); 9906177e52SIan Lepore } 100