1 /*- 2 * Copyright (c) 2013 Thomas Skibo 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 /* 30 * A GPIO driver for Xilinx Zynq-7000. 31 * 32 * The GPIO peripheral on Zynq allows controlling 114 general purpose I/Os. 33 * 34 * Pins 53-0 are sent to the MIO. Any MIO pins not used by a PS peripheral are 35 * available as a GPIO pin. Pins 64-127 are sent to the PL (FPGA) section of 36 * Zynq as EMIO signals. 37 * 38 * The hardware provides a way to use IOs as interrupt sources but the 39 * gpio framework doesn't seem to have hooks for this. 40 * 41 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual. 42 * (v1.4) November 16, 2012. Xilinx doc UG585. GPIO is covered in 43 * chater 14. Register definitions are in appendix B.19. 44 */ 45 46 #include <sys/cdefs.h> 47 __FBSDID("$FreeBSD$"); 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/conf.h> 52 #include <sys/bus.h> 53 #include <sys/kernel.h> 54 #include <sys/module.h> 55 #include <sys/lock.h> 56 #include <sys/mutex.h> 57 #include <sys/resource.h> 58 #include <sys/rman.h> 59 #include <sys/gpio.h> 60 61 #include <machine/bus.h> 62 #include <machine/resource.h> 63 #include <machine/stdarg.h> 64 65 #include <dev/gpio/gpiobusvar.h> 66 #include <dev/ofw/ofw_bus.h> 67 #include <dev/ofw/ofw_bus_subr.h> 68 69 #include "gpio_if.h" 70 71 #define NUMBANKS 4 72 #define MAXPIN (32*NUMBANKS) 73 74 #define MIO_PIN 0 /* pins 0-53 go to MIO */ 75 #define NUM_MIO_PINS 54 76 #define EMIO_PIN 64 /* pins 64-127 go to PL */ 77 #define NUM_EMIO_PINS 64 78 79 #define VALID_PIN(u) (((u) >= MIO_PIN && (u) < MIO_PIN + NUM_MIO_PINS) || \ 80 ((u) >= EMIO_PIN && (u) < EMIO_PIN + NUM_EMIO_PINS)) 81 82 #define ZGPIO_LOCK(sc) mtx_lock(&(sc)->sc_mtx) 83 #define ZGPIO_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx) 84 #define ZGPIO_LOCK_INIT(sc) \ 85 mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev), \ 86 "gpio", MTX_DEF) 87 #define ZGPIO_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); 88 89 struct zy7_gpio_softc { 90 device_t dev; 91 device_t busdev; 92 struct mtx sc_mtx; 93 struct resource *mem_res; /* Memory resource */ 94 }; 95 96 #define WR4(sc, off, val) bus_write_4((sc)->mem_res, (off), (val)) 97 #define RD4(sc, off) bus_read_4((sc)->mem_res, (off)) 98 99 100 /* Xilinx Zynq-7000 GPIO register definitions: 101 */ 102 #define ZY7_GPIO_MASK_DATA_LSW(b) (0x0000+8*(b)) /* maskable wr lo */ 103 #define ZY7_GPIO_MASK_DATA_MSW(b) (0x0004+8*(b)) /* maskable wr hi */ 104 #define ZY7_GPIO_DATA(b) (0x0040+4*(b)) /* in/out data */ 105 #define ZY7_GPIO_DATA_RO(b) (0x0060+4*(b)) /* input data */ 106 107 #define ZY7_GPIO_DIRM(b) (0x0204+0x40*(b)) /* direction mode */ 108 #define ZY7_GPIO_OEN(b) (0x0208+0x40*(b)) /* output enable */ 109 #define ZY7_GPIO_INT_MASK(b) (0x020c+0x40*(b)) /* int mask */ 110 #define ZY7_GPIO_INT_EN(b) (0x0210+0x40*(b)) /* int enable */ 111 #define ZY7_GPIO_INT_DIS(b) (0x0214+0x40*(b)) /* int disable */ 112 #define ZY7_GPIO_INT_STAT(b) (0x0218+0x40*(b)) /* int status */ 113 #define ZY7_GPIO_INT_TYPE(b) (0x021c+0x40*(b)) /* int type */ 114 #define ZY7_GPIO_INT_POLARITY(b) (0x0220+0x40*(b)) /* int polarity */ 115 #define ZY7_GPIO_INT_ANY(b) (0x0224+0x40*(b)) /* any edge */ 116 117 static device_t 118 zy7_gpio_get_bus(device_t dev) 119 { 120 struct zy7_gpio_softc *sc; 121 122 sc = device_get_softc(dev); 123 124 return (sc->busdev); 125 } 126 127 static int 128 zy7_gpio_pin_max(device_t dev, int *maxpin) 129 { 130 131 *maxpin = MAXPIN; 132 return (0); 133 } 134 135 /* Get a specific pin's capabilities. */ 136 static int 137 zy7_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 138 { 139 140 if (!VALID_PIN(pin)) 141 return (EINVAL); 142 143 *caps = (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_TRISTATE); 144 145 return (0); 146 } 147 148 /* Get a specific pin's name. */ 149 static int 150 zy7_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 151 { 152 153 if (!VALID_PIN(pin)) 154 return (EINVAL); 155 156 if (pin < NUM_MIO_PINS) { 157 snprintf(name, GPIOMAXNAME, "MIO_%d", pin); 158 name[GPIOMAXNAME - 1] = '\0'; 159 } else { 160 snprintf(name, GPIOMAXNAME, "EMIO_%d", pin - EMIO_PIN); 161 name[GPIOMAXNAME - 1] = '\0'; 162 } 163 164 return (0); 165 } 166 167 /* Get a specific pin's current in/out/tri state. */ 168 static int 169 zy7_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 170 { 171 struct zy7_gpio_softc *sc = device_get_softc(dev); 172 173 if (!VALID_PIN(pin)) 174 return (EINVAL); 175 176 ZGPIO_LOCK(sc); 177 178 if ((RD4(sc, ZY7_GPIO_DIRM(pin >> 5)) & (1 << (pin & 31))) != 0) { 179 /* output */ 180 if ((RD4(sc, ZY7_GPIO_OEN(pin >> 5)) & (1 << (pin & 31))) == 0) 181 *flags = (GPIO_PIN_OUTPUT | GPIO_PIN_TRISTATE); 182 else 183 *flags = GPIO_PIN_OUTPUT; 184 } else 185 /* input */ 186 *flags = GPIO_PIN_INPUT; 187 188 ZGPIO_UNLOCK(sc); 189 190 return (0); 191 } 192 193 /* Set a specific pin's in/out/tri state. */ 194 static int 195 zy7_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 196 { 197 struct zy7_gpio_softc *sc = device_get_softc(dev); 198 199 if (!VALID_PIN(pin)) 200 return (EINVAL); 201 202 ZGPIO_LOCK(sc); 203 204 if ((flags & GPIO_PIN_OUTPUT) != 0) { 205 /* Output. Set or reset OEN too. */ 206 WR4(sc, ZY7_GPIO_DIRM(pin >> 5), 207 RD4(sc, ZY7_GPIO_DIRM(pin >> 5)) | (1 << (pin & 31))); 208 209 if ((flags & GPIO_PIN_TRISTATE) != 0) 210 WR4(sc, ZY7_GPIO_OEN(pin >> 5), 211 RD4(sc, ZY7_GPIO_OEN(pin >> 5)) & 212 ~(1 << (pin & 31))); 213 else 214 WR4(sc, ZY7_GPIO_OEN(pin >> 5), 215 RD4(sc, ZY7_GPIO_OEN(pin >> 5)) | 216 (1 << (pin & 31))); 217 } else { 218 /* Input. Turn off OEN. */ 219 WR4(sc, ZY7_GPIO_DIRM(pin >> 5), 220 RD4(sc, ZY7_GPIO_DIRM(pin >> 5)) & ~(1 << (pin & 31))); 221 WR4(sc, ZY7_GPIO_OEN(pin >> 5), 222 RD4(sc, ZY7_GPIO_OEN(pin >> 5)) & ~(1 << (pin & 31))); 223 } 224 225 ZGPIO_UNLOCK(sc); 226 227 return (0); 228 } 229 230 /* Set a specific output pin's value. */ 231 static int 232 zy7_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) 233 { 234 struct zy7_gpio_softc *sc = device_get_softc(dev); 235 236 if (!VALID_PIN(pin) || value > 1) 237 return (EINVAL); 238 239 /* Fancy register tricks allow atomic set or reset. */ 240 if ((pin & 16) != 0) 241 WR4(sc, ZY7_GPIO_MASK_DATA_MSW(pin >> 5), 242 (0xffff0000 ^ (0x10000 << (pin & 15))) | 243 (value << (pin & 15))); 244 else 245 WR4(sc, ZY7_GPIO_MASK_DATA_LSW(pin >> 5), 246 (0xffff0000 ^ (0x10000 << (pin & 15))) | 247 (value << (pin & 15))); 248 249 return (0); 250 } 251 252 /* Get a specific pin's input value. */ 253 static int 254 zy7_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value) 255 { 256 struct zy7_gpio_softc *sc = device_get_softc(dev); 257 258 if (!VALID_PIN(pin)) 259 return (EINVAL); 260 261 *value = (RD4(sc, ZY7_GPIO_DATA_RO(pin >> 5)) >> (pin & 31)) & 1; 262 263 return (0); 264 } 265 266 /* Toggle a pin's output value. */ 267 static int 268 zy7_gpio_pin_toggle(device_t dev, uint32_t pin) 269 { 270 struct zy7_gpio_softc *sc = device_get_softc(dev); 271 272 if (!VALID_PIN(pin)) 273 return (EINVAL); 274 275 ZGPIO_LOCK(sc); 276 277 WR4(sc, ZY7_GPIO_DATA(pin >> 5), 278 RD4(sc, ZY7_GPIO_DATA(pin >> 5)) ^ (1 << (pin & 31))); 279 280 ZGPIO_UNLOCK(sc); 281 282 return (0); 283 } 284 285 static int 286 zy7_gpio_probe(device_t dev) 287 { 288 289 if (!ofw_bus_status_okay(dev)) 290 return (ENXIO); 291 292 if (!ofw_bus_is_compatible(dev, "xlnx,zy7_gpio")) 293 return (ENXIO); 294 295 device_set_desc(dev, "Zynq-7000 GPIO driver"); 296 return (0); 297 } 298 299 static void 300 zy7_gpio_hw_reset(struct zy7_gpio_softc *sc) 301 { 302 int i; 303 304 for (i = 0; i < NUMBANKS; i++) { 305 WR4(sc, ZY7_GPIO_DATA(i), 0); 306 WR4(sc, ZY7_GPIO_DIRM(i), 0); 307 WR4(sc, ZY7_GPIO_OEN(i), 0); 308 WR4(sc, ZY7_GPIO_INT_DIS(i), 0xffffffff); 309 WR4(sc, ZY7_GPIO_INT_POLARITY(i), 0); 310 WR4(sc, ZY7_GPIO_INT_TYPE(i), 311 i == 1 ? 0x003fffff : 0xffffffff); 312 WR4(sc, ZY7_GPIO_INT_ANY(i), 0); 313 WR4(sc, ZY7_GPIO_INT_STAT(i), 0xffffffff); 314 } 315 } 316 317 static int zy7_gpio_detach(device_t dev); 318 319 static int 320 zy7_gpio_attach(device_t dev) 321 { 322 struct zy7_gpio_softc *sc = device_get_softc(dev); 323 int rid; 324 325 sc->dev = dev; 326 327 ZGPIO_LOCK_INIT(sc); 328 329 /* Allocate memory. */ 330 rid = 0; 331 sc->mem_res = bus_alloc_resource_any(dev, 332 SYS_RES_MEMORY, &rid, RF_ACTIVE); 333 if (sc->mem_res == NULL) { 334 device_printf(dev, "Can't allocate memory for device"); 335 zy7_gpio_detach(dev); 336 return (ENOMEM); 337 } 338 339 /* Completely reset. */ 340 zy7_gpio_hw_reset(sc); 341 342 sc->busdev = gpiobus_attach_bus(dev); 343 if (sc->busdev == NULL) { 344 zy7_gpio_detach(dev); 345 return (ENOMEM); 346 } 347 348 return (0); 349 } 350 351 static int 352 zy7_gpio_detach(device_t dev) 353 { 354 struct zy7_gpio_softc *sc = device_get_softc(dev); 355 356 gpiobus_detach_bus(dev); 357 358 if (sc->mem_res != NULL) { 359 /* Release memory resource. */ 360 bus_release_resource(dev, SYS_RES_MEMORY, 361 rman_get_rid(sc->mem_res), sc->mem_res); 362 } 363 364 ZGPIO_LOCK_DESTROY(sc); 365 366 return (0); 367 } 368 369 static device_method_t zy7_gpio_methods[] = { 370 /* device_if */ 371 DEVMETHOD(device_probe, zy7_gpio_probe), 372 DEVMETHOD(device_attach, zy7_gpio_attach), 373 DEVMETHOD(device_detach, zy7_gpio_detach), 374 375 /* GPIO protocol */ 376 DEVMETHOD(gpio_get_bus, zy7_gpio_get_bus), 377 DEVMETHOD(gpio_pin_max, zy7_gpio_pin_max), 378 DEVMETHOD(gpio_pin_getname, zy7_gpio_pin_getname), 379 DEVMETHOD(gpio_pin_getflags, zy7_gpio_pin_getflags), 380 DEVMETHOD(gpio_pin_getcaps, zy7_gpio_pin_getcaps), 381 DEVMETHOD(gpio_pin_setflags, zy7_gpio_pin_setflags), 382 DEVMETHOD(gpio_pin_get, zy7_gpio_pin_get), 383 DEVMETHOD(gpio_pin_set, zy7_gpio_pin_set), 384 DEVMETHOD(gpio_pin_toggle, zy7_gpio_pin_toggle), 385 386 DEVMETHOD_END 387 }; 388 389 static driver_t zy7_gpio_driver = { 390 "gpio", 391 zy7_gpio_methods, 392 sizeof(struct zy7_gpio_softc), 393 }; 394 static devclass_t zy7_gpio_devclass; 395 396 DRIVER_MODULE(zy7_gpio, simplebus, zy7_gpio_driver, zy7_gpio_devclass, \ 397 NULL, NULL); 398