1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2013 Thomas Skibo 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 /* 32 * A GPIO driver for Xilinx Zynq-7000. 33 * 34 * The GPIO peripheral on Zynq allows controlling 114 general purpose I/Os. 35 * 36 * Pins 53-0 are sent to the MIO. Any MIO pins not used by a PS peripheral are 37 * available as a GPIO pin. Pins 64-127 are sent to the PL (FPGA) section of 38 * Zynq as EMIO signals. 39 * 40 * The hardware provides a way to use IOs as interrupt sources but the 41 * gpio framework doesn't seem to have hooks for this. 42 * 43 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual. 44 * (v1.4) November 16, 2012. Xilinx doc UG585. GPIO is covered in 45 * chater 14. Register definitions are in appendix B.19. 46 */ 47 48 #include <sys/cdefs.h> 49 __FBSDID("$FreeBSD$"); 50 51 #include <sys/param.h> 52 #include <sys/systm.h> 53 #include <sys/conf.h> 54 #include <sys/bus.h> 55 #include <sys/kernel.h> 56 #include <sys/module.h> 57 #include <sys/lock.h> 58 #include <sys/mutex.h> 59 #include <sys/resource.h> 60 #include <sys/rman.h> 61 #include <sys/gpio.h> 62 63 #include <machine/bus.h> 64 #include <machine/resource.h> 65 #include <machine/stdarg.h> 66 67 #include <dev/gpio/gpiobusvar.h> 68 #include <dev/ofw/ofw_bus.h> 69 #include <dev/ofw/ofw_bus_subr.h> 70 71 #include "gpio_if.h" 72 73 #define ZYNQ7_MAX_BANK 4 74 #define ZYNQMP_MAX_BANK 6 75 76 /* Zynq 7000 */ 77 #define ZYNQ7_BANK0_PIN_MIN 0 78 #define ZYNQ7_BANK0_NPIN 32 79 #define ZYNQ7_BANK1_PIN_MIN 32 80 #define ZYNQ7_BANK1_NPIN 22 81 #define ZYNQ7_BANK2_PIN_MIN 64 82 #define ZYNQ7_BANK2_NPIN 32 83 #define ZYNQ7_BANK3_PIN_MIN 96 84 #define ZYNQ7_BANK3_NPIN 32 85 #define ZYNQ7_PIN_MIO_MIN 0 86 #define ZYNQ7_PIN_MIO_MAX 54 87 #define ZYNQ7_PIN_EMIO_MIN 64 88 #define ZYNQ7_PIN_EMIO_MAX 118 89 90 /* ZynqMP */ 91 #define ZYNQMP_BANK0_PIN_MIN 0 92 #define ZYNQMP_BANK0_NPIN 26 93 #define ZYNQMP_BANK1_PIN_MIN 26 94 #define ZYNQMP_BANK1_NPIN 26 95 #define ZYNQMP_BANK2_PIN_MIN 52 96 #define ZYNQMP_BANK2_NPIN 26 97 #define ZYNQMP_BANK3_PIN_MIN 78 98 #define ZYNQMP_BANK3_NPIN 32 99 #define ZYNQMP_BANK4_PIN_MIN 110 100 #define ZYNQMP_BANK4_NPIN 32 101 #define ZYNQMP_BANK5_PIN_MIN 142 102 #define ZYNQMP_BANK5_NPIN 32 103 #define ZYNQMP_PIN_MIO_MIN 0 104 #define ZYNQMP_PIN_MIO_MAX 77 105 #define ZYNQMP_PIN_EMIO_MIN 78 106 #define ZYNQMP_PIN_EMIO_MAX 174 107 108 #define ZYNQ_BANK_NPIN(type, bank) (ZYNQ##type##_BANK##bank##_NPIN) 109 #define ZYNQ_BANK_PIN_MIN(type, bank) (ZYNQ##type##_BANK##bank##_PIN_MIN) 110 #define ZYNQ_BANK_PIN_MAX(type, bank) (ZYNQ##type##_BANK##bank##_PIN_MIN + ZYNQ##type##_BANK##bank##_NPIN - 1) 111 112 #define ZYNQ_PIN_IS_MIO(type, pin) (pin >= ZYNQ##type##_PIN_MIO_MIN && \ 113 pin <= ZYNQ##type##_PIN_MIO_MAX) 114 #define ZYNQ_PIN_IS_EMIO(type, pin) (pin >= ZYNQ##type##_PIN_EMIO_MIN && \ 115 pin <= ZYNQ##type##_PIN_EMIO_MAX) 116 117 #define ZGPIO_LOCK(sc) mtx_lock(&(sc)->sc_mtx) 118 #define ZGPIO_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx) 119 #define ZGPIO_LOCK_INIT(sc) \ 120 mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev), \ 121 "gpio", MTX_DEF) 122 #define ZGPIO_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); 123 124 enum zynq_gpio_type { 125 ZYNQ_7000 = 0, 126 ZYNQMP, 127 }; 128 129 struct zynq_gpio_conf { 130 char *name; 131 enum zynq_gpio_type type; 132 uint32_t nbanks; 133 uint32_t maxpin; 134 uint32_t bank_min[ZYNQMP_MAX_BANK]; 135 uint32_t bank_max[ZYNQMP_MAX_BANK]; 136 }; 137 138 struct zy7_gpio_softc { 139 device_t dev; 140 device_t busdev; 141 struct mtx sc_mtx; 142 struct resource *mem_res; /* Memory resource */ 143 struct zynq_gpio_conf *conf; 144 }; 145 146 static struct zynq_gpio_conf z7_gpio_conf = { 147 .name = "Zynq-7000 GPIO Controller", 148 .type = ZYNQ_7000, 149 .nbanks = ZYNQ7_MAX_BANK, 150 .maxpin = ZYNQ7_PIN_EMIO_MAX, 151 .bank_min[0] = ZYNQ_BANK_PIN_MIN(7, 0), 152 .bank_max[0] = ZYNQ_BANK_PIN_MAX(7, 0), 153 .bank_min[1] = ZYNQ_BANK_PIN_MIN(7, 1), 154 .bank_max[1] = ZYNQ_BANK_PIN_MAX(7, 1), 155 .bank_min[2] = ZYNQ_BANK_PIN_MIN(7, 2), 156 .bank_max[2] = ZYNQ_BANK_PIN_MAX(7, 2), 157 .bank_min[3] = ZYNQ_BANK_PIN_MIN(7, 3), 158 .bank_max[3] = ZYNQ_BANK_PIN_MAX(7, 3), 159 }; 160 161 static struct zynq_gpio_conf zynqmp_gpio_conf = { 162 .name = "ZynqMP GPIO Controller", 163 .type = ZYNQMP, 164 .nbanks = ZYNQMP_MAX_BANK, 165 .maxpin = ZYNQMP_PIN_EMIO_MAX, 166 .bank_min[0] = ZYNQ_BANK_PIN_MIN(MP, 0), 167 .bank_max[0] = ZYNQ_BANK_PIN_MAX(MP, 0), 168 .bank_min[1] = ZYNQ_BANK_PIN_MIN(MP, 1), 169 .bank_max[1] = ZYNQ_BANK_PIN_MAX(MP, 1), 170 .bank_min[2] = ZYNQ_BANK_PIN_MIN(MP, 2), 171 .bank_max[2] = ZYNQ_BANK_PIN_MAX(MP, 2), 172 .bank_min[3] = ZYNQ_BANK_PIN_MIN(MP, 3), 173 .bank_max[3] = ZYNQ_BANK_PIN_MAX(MP, 3), 174 .bank_min[4] = ZYNQ_BANK_PIN_MIN(MP, 4), 175 .bank_max[4] = ZYNQ_BANK_PIN_MAX(MP, 4), 176 .bank_min[5] = ZYNQ_BANK_PIN_MIN(MP, 5), 177 .bank_max[5] = ZYNQ_BANK_PIN_MAX(MP, 5), 178 }; 179 180 static struct ofw_compat_data compat_data[] = { 181 {"xlnx,zy7_gpio", (uintptr_t)&z7_gpio_conf}, 182 {"xlnx,zynqmp-gpio-1.0", (uintptr_t)&zynqmp_gpio_conf}, 183 {NULL, 0}, 184 }; 185 186 #define WR4(sc, off, val) bus_write_4((sc)->mem_res, (off), (val)) 187 #define RD4(sc, off) bus_read_4((sc)->mem_res, (off)) 188 189 /* Xilinx Zynq-7000 GPIO register definitions: 190 */ 191 #define ZY7_GPIO_MASK_DATA_LSW(b) (0x0000+8*(b)) /* maskable wr lo */ 192 #define ZY7_GPIO_MASK_DATA_MSW(b) (0x0004+8*(b)) /* maskable wr hi */ 193 #define ZY7_GPIO_DATA(b) (0x0040+4*(b)) /* in/out data */ 194 #define ZY7_GPIO_DATA_RO(b) (0x0060+4*(b)) /* input data */ 195 196 #define ZY7_GPIO_DIRM(b) (0x0204+0x40*(b)) /* direction mode */ 197 #define ZY7_GPIO_OEN(b) (0x0208+0x40*(b)) /* output enable */ 198 #define ZY7_GPIO_INT_MASK(b) (0x020c+0x40*(b)) /* int mask */ 199 #define ZY7_GPIO_INT_EN(b) (0x0210+0x40*(b)) /* int enable */ 200 #define ZY7_GPIO_INT_DIS(b) (0x0214+0x40*(b)) /* int disable */ 201 #define ZY7_GPIO_INT_STAT(b) (0x0218+0x40*(b)) /* int status */ 202 #define ZY7_GPIO_INT_TYPE(b) (0x021c+0x40*(b)) /* int type */ 203 #define ZY7_GPIO_INT_POLARITY(b) (0x0220+0x40*(b)) /* int polarity */ 204 #define ZY7_GPIO_INT_ANY(b) (0x0224+0x40*(b)) /* any edge */ 205 206 static device_t 207 zy7_gpio_get_bus(device_t dev) 208 { 209 struct zy7_gpio_softc *sc; 210 211 sc = device_get_softc(dev); 212 213 return (sc->busdev); 214 } 215 216 static int 217 zy7_gpio_pin_max(device_t dev, int *maxpin) 218 { 219 struct zy7_gpio_softc *sc; 220 221 sc = device_get_softc(dev); 222 *maxpin = sc->conf->maxpin; 223 return (0); 224 } 225 226 static inline bool 227 zy7_pin_valid(device_t dev, uint32_t pin) 228 { 229 struct zy7_gpio_softc *sc; 230 int i; 231 bool found = false; 232 233 sc = device_get_softc(dev); 234 for (i = 0; i < sc->conf->nbanks; i++) { 235 if (pin >= sc->conf->bank_min[i] && pin <= sc->conf->bank_max[i]) { 236 found = true; 237 break; 238 } 239 } 240 241 return (found); 242 } 243 244 /* Get a specific pin's capabilities. */ 245 static int 246 zy7_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 247 { 248 249 if (!zy7_pin_valid(dev, pin)) 250 return (EINVAL); 251 252 *caps = (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_TRISTATE); 253 254 return (0); 255 } 256 257 /* Get a specific pin's name. */ 258 static int 259 zy7_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 260 { 261 struct zy7_gpio_softc *sc; 262 uint32_t emio_min; 263 bool is_mio; 264 265 sc = device_get_softc(dev); 266 if (!zy7_pin_valid(dev, pin)) 267 return (EINVAL); 268 269 switch (sc->conf->type) { 270 case ZYNQ_7000: 271 is_mio = ZYNQ_PIN_IS_MIO(7, pin); 272 emio_min = ZYNQ7_PIN_EMIO_MIN; 273 break; 274 case ZYNQMP: 275 is_mio = ZYNQ_PIN_IS_MIO(MP, pin); 276 emio_min = ZYNQMP_PIN_EMIO_MIN; 277 break; 278 default: 279 return (EINVAL); 280 } 281 if (is_mio) { 282 snprintf(name, GPIOMAXNAME, "MIO_%d", pin); 283 name[GPIOMAXNAME - 1] = '\0'; 284 } else { 285 snprintf(name, GPIOMAXNAME, "EMIO_%d", pin - emio_min); 286 name[GPIOMAXNAME - 1] = '\0'; 287 } 288 289 return (0); 290 } 291 292 /* Get a specific pin's current in/out/tri state. */ 293 static int 294 zy7_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 295 { 296 struct zy7_gpio_softc *sc = device_get_softc(dev); 297 298 if (!zy7_pin_valid(dev, pin)) 299 return (EINVAL); 300 301 ZGPIO_LOCK(sc); 302 303 if ((RD4(sc, ZY7_GPIO_DIRM(pin >> 5)) & (1 << (pin & 31))) != 0) { 304 /* output */ 305 if ((RD4(sc, ZY7_GPIO_OEN(pin >> 5)) & (1 << (pin & 31))) == 0) 306 *flags = (GPIO_PIN_OUTPUT | GPIO_PIN_TRISTATE); 307 else 308 *flags = GPIO_PIN_OUTPUT; 309 } else 310 /* input */ 311 *flags = GPIO_PIN_INPUT; 312 313 ZGPIO_UNLOCK(sc); 314 315 return (0); 316 } 317 318 /* Set a specific pin's in/out/tri state. */ 319 static int 320 zy7_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 321 { 322 struct zy7_gpio_softc *sc = device_get_softc(dev); 323 324 if (!zy7_pin_valid(dev, pin)) 325 return (EINVAL); 326 327 ZGPIO_LOCK(sc); 328 329 if ((flags & GPIO_PIN_OUTPUT) != 0) { 330 /* Output. Set or reset OEN too. */ 331 WR4(sc, ZY7_GPIO_DIRM(pin >> 5), 332 RD4(sc, ZY7_GPIO_DIRM(pin >> 5)) | (1 << (pin & 31))); 333 334 if ((flags & GPIO_PIN_TRISTATE) != 0) 335 WR4(sc, ZY7_GPIO_OEN(pin >> 5), 336 RD4(sc, ZY7_GPIO_OEN(pin >> 5)) & 337 ~(1 << (pin & 31))); 338 else 339 WR4(sc, ZY7_GPIO_OEN(pin >> 5), 340 RD4(sc, ZY7_GPIO_OEN(pin >> 5)) | 341 (1 << (pin & 31))); 342 } else { 343 /* Input. Turn off OEN. */ 344 WR4(sc, ZY7_GPIO_DIRM(pin >> 5), 345 RD4(sc, ZY7_GPIO_DIRM(pin >> 5)) & ~(1 << (pin & 31))); 346 WR4(sc, ZY7_GPIO_OEN(pin >> 5), 347 RD4(sc, ZY7_GPIO_OEN(pin >> 5)) & ~(1 << (pin & 31))); 348 } 349 350 ZGPIO_UNLOCK(sc); 351 352 return (0); 353 } 354 355 /* Set a specific output pin's value. */ 356 static int 357 zy7_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) 358 { 359 struct zy7_gpio_softc *sc = device_get_softc(dev); 360 361 if (!zy7_pin_valid(dev, pin) || value > 1) 362 return (EINVAL); 363 364 /* Fancy register tricks allow atomic set or reset. */ 365 if ((pin & 16) != 0) 366 WR4(sc, ZY7_GPIO_MASK_DATA_MSW(pin >> 5), 367 (0xffff0000 ^ (0x10000 << (pin & 15))) | 368 (value << (pin & 15))); 369 else 370 WR4(sc, ZY7_GPIO_MASK_DATA_LSW(pin >> 5), 371 (0xffff0000 ^ (0x10000 << (pin & 15))) | 372 (value << (pin & 15))); 373 374 return (0); 375 } 376 377 /* Get a specific pin's input value. */ 378 static int 379 zy7_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value) 380 { 381 struct zy7_gpio_softc *sc = device_get_softc(dev); 382 383 if (!zy7_pin_valid(dev, pin)) 384 return (EINVAL); 385 386 *value = (RD4(sc, ZY7_GPIO_DATA_RO(pin >> 5)) >> (pin & 31)) & 1; 387 388 return (0); 389 } 390 391 /* Toggle a pin's output value. */ 392 static int 393 zy7_gpio_pin_toggle(device_t dev, uint32_t pin) 394 { 395 struct zy7_gpio_softc *sc = device_get_softc(dev); 396 397 if (!zy7_pin_valid(dev, pin)) 398 return (EINVAL); 399 400 ZGPIO_LOCK(sc); 401 402 WR4(sc, ZY7_GPIO_DATA(pin >> 5), 403 RD4(sc, ZY7_GPIO_DATA(pin >> 5)) ^ (1 << (pin & 31))); 404 405 ZGPIO_UNLOCK(sc); 406 407 return (0); 408 } 409 410 static int 411 zy7_gpio_probe(device_t dev) 412 { 413 struct zynq_gpio_conf *conf; 414 415 if (!ofw_bus_status_okay(dev)) 416 return (ENXIO); 417 418 conf = (struct zynq_gpio_conf *)ofw_bus_search_compatible(dev, compat_data)->ocd_data; 419 if (conf == 0) 420 return (ENXIO); 421 422 device_set_desc(dev, conf->name); 423 return (0); 424 } 425 426 static int zy7_gpio_detach(device_t dev); 427 428 static int 429 zy7_gpio_attach(device_t dev) 430 { 431 struct zy7_gpio_softc *sc = device_get_softc(dev); 432 int rid; 433 434 sc->dev = dev; 435 sc->conf = (struct zynq_gpio_conf *)ofw_bus_search_compatible(dev, compat_data)->ocd_data; 436 437 ZGPIO_LOCK_INIT(sc); 438 439 /* Allocate memory. */ 440 rid = 0; 441 sc->mem_res = bus_alloc_resource_any(dev, 442 SYS_RES_MEMORY, &rid, RF_ACTIVE); 443 if (sc->mem_res == NULL) { 444 device_printf(dev, "Can't allocate memory for device"); 445 zy7_gpio_detach(dev); 446 return (ENOMEM); 447 } 448 449 sc->busdev = gpiobus_attach_bus(dev); 450 if (sc->busdev == NULL) { 451 zy7_gpio_detach(dev); 452 return (ENOMEM); 453 } 454 455 return (0); 456 } 457 458 static int 459 zy7_gpio_detach(device_t dev) 460 { 461 struct zy7_gpio_softc *sc = device_get_softc(dev); 462 463 gpiobus_detach_bus(dev); 464 465 if (sc->mem_res != NULL) { 466 /* Release memory resource. */ 467 bus_release_resource(dev, SYS_RES_MEMORY, 468 rman_get_rid(sc->mem_res), sc->mem_res); 469 } 470 471 ZGPIO_LOCK_DESTROY(sc); 472 473 return (0); 474 } 475 476 static device_method_t zy7_gpio_methods[] = { 477 /* device_if */ 478 DEVMETHOD(device_probe, zy7_gpio_probe), 479 DEVMETHOD(device_attach, zy7_gpio_attach), 480 DEVMETHOD(device_detach, zy7_gpio_detach), 481 482 /* GPIO protocol */ 483 DEVMETHOD(gpio_get_bus, zy7_gpio_get_bus), 484 DEVMETHOD(gpio_pin_max, zy7_gpio_pin_max), 485 DEVMETHOD(gpio_pin_getname, zy7_gpio_pin_getname), 486 DEVMETHOD(gpio_pin_getflags, zy7_gpio_pin_getflags), 487 DEVMETHOD(gpio_pin_getcaps, zy7_gpio_pin_getcaps), 488 DEVMETHOD(gpio_pin_setflags, zy7_gpio_pin_setflags), 489 DEVMETHOD(gpio_pin_get, zy7_gpio_pin_get), 490 DEVMETHOD(gpio_pin_set, zy7_gpio_pin_set), 491 DEVMETHOD(gpio_pin_toggle, zy7_gpio_pin_toggle), 492 493 DEVMETHOD_END 494 }; 495 496 static driver_t zy7_gpio_driver = { 497 "gpio", 498 zy7_gpio_methods, 499 sizeof(struct zy7_gpio_softc), 500 }; 501 502 EARLY_DRIVER_MODULE(zy7_gpio, simplebus, zy7_gpio_driver, 0, 0, 503 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE); 504