1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2013 Thomas Skibo 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * A GPIO driver for Xilinx Zynq-7000. 31 * 32 * The GPIO peripheral on Zynq allows controlling 114 general purpose I/Os. 33 * 34 * Pins 53-0 are sent to the MIO. Any MIO pins not used by a PS peripheral are 35 * available as a GPIO pin. Pins 64-127 are sent to the PL (FPGA) section of 36 * Zynq as EMIO signals. 37 * 38 * The hardware provides a way to use IOs as interrupt sources but the 39 * gpio framework doesn't seem to have hooks for this. 40 * 41 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual. 42 * (v1.4) November 16, 2012. Xilinx doc UG585. GPIO is covered in 43 * chater 14. Register definitions are in appendix B.19. 44 */ 45 46 #include <sys/cdefs.h> 47 __FBSDID("$FreeBSD$"); 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/conf.h> 52 #include <sys/bus.h> 53 #include <sys/kernel.h> 54 #include <sys/module.h> 55 #include <sys/lock.h> 56 #include <sys/mutex.h> 57 #include <sys/resource.h> 58 #include <sys/rman.h> 59 #include <sys/gpio.h> 60 61 #include <machine/bus.h> 62 #include <machine/resource.h> 63 #include <machine/stdarg.h> 64 65 #include <dev/gpio/gpiobusvar.h> 66 #include <dev/ofw/ofw_bus.h> 67 #include <dev/ofw/ofw_bus_subr.h> 68 69 #include "gpio_if.h" 70 71 #define ZYNQ7_MAX_BANK 4 72 #define ZYNQMP_MAX_BANK 6 73 74 /* Zynq 7000 */ 75 #define ZYNQ7_BANK0_PIN_MIN 0 76 #define ZYNQ7_BANK0_NPIN 32 77 #define ZYNQ7_BANK1_PIN_MIN 32 78 #define ZYNQ7_BANK1_NPIN 22 79 #define ZYNQ7_BANK2_PIN_MIN 64 80 #define ZYNQ7_BANK2_NPIN 32 81 #define ZYNQ7_BANK3_PIN_MIN 96 82 #define ZYNQ7_BANK3_NPIN 32 83 #define ZYNQ7_PIN_MIO_MIN 0 84 #define ZYNQ7_PIN_MIO_MAX 54 85 #define ZYNQ7_PIN_EMIO_MIN 64 86 #define ZYNQ7_PIN_EMIO_MAX 118 87 88 /* ZynqMP */ 89 #define ZYNQMP_BANK0_PIN_MIN 0 90 #define ZYNQMP_BANK0_NPIN 26 91 #define ZYNQMP_BANK1_PIN_MIN 26 92 #define ZYNQMP_BANK1_NPIN 26 93 #define ZYNQMP_BANK2_PIN_MIN 52 94 #define ZYNQMP_BANK2_NPIN 26 95 #define ZYNQMP_BANK3_PIN_MIN 78 96 #define ZYNQMP_BANK3_NPIN 32 97 #define ZYNQMP_BANK4_PIN_MIN 110 98 #define ZYNQMP_BANK4_NPIN 32 99 #define ZYNQMP_BANK5_PIN_MIN 142 100 #define ZYNQMP_BANK5_NPIN 32 101 #define ZYNQMP_PIN_MIO_MIN 0 102 #define ZYNQMP_PIN_MIO_MAX 77 103 #define ZYNQMP_PIN_EMIO_MIN 78 104 #define ZYNQMP_PIN_EMIO_MAX 174 105 106 #define ZYNQ_BANK_NPIN(type, bank) (ZYNQ##type##_BANK##bank##_NPIN) 107 #define ZYNQ_BANK_PIN_MIN(type, bank) (ZYNQ##type##_BANK##bank##_PIN_MIN) 108 #define ZYNQ_BANK_PIN_MAX(type, bank) (ZYNQ##type##_BANK##bank##_PIN_MIN + ZYNQ##type##_BANK##bank##_NPIN - 1) 109 110 #define ZYNQ_PIN_IS_MIO(type, pin) (pin >= ZYNQ##type##_PIN_MIO_MIN && \ 111 pin <= ZYNQ##type##_PIN_MIO_MAX) 112 #define ZYNQ_PIN_IS_EMIO(type, pin) (pin >= ZYNQ##type##_PIN_EMIO_MIN && \ 113 pin <= ZYNQ##type##_PIN_EMIO_MAX) 114 115 #define ZGPIO_LOCK(sc) mtx_lock(&(sc)->sc_mtx) 116 #define ZGPIO_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx) 117 #define ZGPIO_LOCK_INIT(sc) \ 118 mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev), \ 119 "gpio", MTX_DEF) 120 #define ZGPIO_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); 121 122 enum zynq_gpio_type { 123 ZYNQ_7000 = 0, 124 ZYNQMP, 125 }; 126 127 struct zynq_gpio_conf { 128 char *name; 129 enum zynq_gpio_type type; 130 uint32_t nbanks; 131 uint32_t maxpin; 132 uint32_t bank_min[ZYNQMP_MAX_BANK]; 133 uint32_t bank_max[ZYNQMP_MAX_BANK]; 134 }; 135 136 struct zy7_gpio_softc { 137 device_t dev; 138 device_t busdev; 139 struct mtx sc_mtx; 140 struct resource *mem_res; /* Memory resource */ 141 struct zynq_gpio_conf *conf; 142 }; 143 144 static struct zynq_gpio_conf z7_gpio_conf = { 145 .name = "Zynq-7000 GPIO Controller", 146 .type = ZYNQ_7000, 147 .nbanks = ZYNQ7_MAX_BANK, 148 .maxpin = ZYNQ7_PIN_EMIO_MAX, 149 .bank_min[0] = ZYNQ_BANK_PIN_MIN(7, 0), 150 .bank_max[0] = ZYNQ_BANK_PIN_MAX(7, 0), 151 .bank_min[1] = ZYNQ_BANK_PIN_MIN(7, 1), 152 .bank_max[1] = ZYNQ_BANK_PIN_MAX(7, 1), 153 .bank_min[2] = ZYNQ_BANK_PIN_MIN(7, 2), 154 .bank_max[2] = ZYNQ_BANK_PIN_MAX(7, 2), 155 .bank_min[3] = ZYNQ_BANK_PIN_MIN(7, 3), 156 .bank_max[3] = ZYNQ_BANK_PIN_MAX(7, 3), 157 }; 158 159 static struct zynq_gpio_conf zynqmp_gpio_conf = { 160 .name = "ZynqMP GPIO Controller", 161 .type = ZYNQMP, 162 .nbanks = ZYNQMP_MAX_BANK, 163 .maxpin = ZYNQMP_PIN_EMIO_MAX, 164 .bank_min[0] = ZYNQ_BANK_PIN_MIN(MP, 0), 165 .bank_max[0] = ZYNQ_BANK_PIN_MAX(MP, 0), 166 .bank_min[1] = ZYNQ_BANK_PIN_MIN(MP, 1), 167 .bank_max[1] = ZYNQ_BANK_PIN_MAX(MP, 1), 168 .bank_min[2] = ZYNQ_BANK_PIN_MIN(MP, 2), 169 .bank_max[2] = ZYNQ_BANK_PIN_MAX(MP, 2), 170 .bank_min[3] = ZYNQ_BANK_PIN_MIN(MP, 3), 171 .bank_max[3] = ZYNQ_BANK_PIN_MAX(MP, 3), 172 .bank_min[4] = ZYNQ_BANK_PIN_MIN(MP, 4), 173 .bank_max[4] = ZYNQ_BANK_PIN_MAX(MP, 4), 174 .bank_min[5] = ZYNQ_BANK_PIN_MIN(MP, 5), 175 .bank_max[5] = ZYNQ_BANK_PIN_MAX(MP, 5), 176 }; 177 178 static struct ofw_compat_data compat_data[] = { 179 {"xlnx,zy7_gpio", (uintptr_t)&z7_gpio_conf}, 180 {"xlnx,zynqmp-gpio-1.0", (uintptr_t)&zynqmp_gpio_conf}, 181 {NULL, 0}, 182 }; 183 184 #define WR4(sc, off, val) bus_write_4((sc)->mem_res, (off), (val)) 185 #define RD4(sc, off) bus_read_4((sc)->mem_res, (off)) 186 187 /* Xilinx Zynq-7000 GPIO register definitions: 188 */ 189 #define ZY7_GPIO_MASK_DATA_LSW(b) (0x0000+8*(b)) /* maskable wr lo */ 190 #define ZY7_GPIO_MASK_DATA_MSW(b) (0x0004+8*(b)) /* maskable wr hi */ 191 #define ZY7_GPIO_DATA(b) (0x0040+4*(b)) /* in/out data */ 192 #define ZY7_GPIO_DATA_RO(b) (0x0060+4*(b)) /* input data */ 193 194 #define ZY7_GPIO_DIRM(b) (0x0204+0x40*(b)) /* direction mode */ 195 #define ZY7_GPIO_OEN(b) (0x0208+0x40*(b)) /* output enable */ 196 #define ZY7_GPIO_INT_MASK(b) (0x020c+0x40*(b)) /* int mask */ 197 #define ZY7_GPIO_INT_EN(b) (0x0210+0x40*(b)) /* int enable */ 198 #define ZY7_GPIO_INT_DIS(b) (0x0214+0x40*(b)) /* int disable */ 199 #define ZY7_GPIO_INT_STAT(b) (0x0218+0x40*(b)) /* int status */ 200 #define ZY7_GPIO_INT_TYPE(b) (0x021c+0x40*(b)) /* int type */ 201 #define ZY7_GPIO_INT_POLARITY(b) (0x0220+0x40*(b)) /* int polarity */ 202 #define ZY7_GPIO_INT_ANY(b) (0x0224+0x40*(b)) /* any edge */ 203 204 static device_t 205 zy7_gpio_get_bus(device_t dev) 206 { 207 struct zy7_gpio_softc *sc; 208 209 sc = device_get_softc(dev); 210 211 return (sc->busdev); 212 } 213 214 static int 215 zy7_gpio_pin_max(device_t dev, int *maxpin) 216 { 217 struct zy7_gpio_softc *sc; 218 219 sc = device_get_softc(dev); 220 *maxpin = sc->conf->maxpin; 221 return (0); 222 } 223 224 static inline bool 225 zy7_pin_valid(device_t dev, uint32_t pin) 226 { 227 struct zy7_gpio_softc *sc; 228 int i; 229 bool found = false; 230 231 sc = device_get_softc(dev); 232 for (i = 0; i < sc->conf->nbanks; i++) { 233 if (pin >= sc->conf->bank_min[i] && pin <= sc->conf->bank_max[i]) { 234 found = true; 235 break; 236 } 237 } 238 239 return (found); 240 } 241 242 /* Get a specific pin's capabilities. */ 243 static int 244 zy7_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 245 { 246 247 if (!zy7_pin_valid(dev, pin)) 248 return (EINVAL); 249 250 *caps = (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_TRISTATE); 251 252 return (0); 253 } 254 255 /* Get a specific pin's name. */ 256 static int 257 zy7_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 258 { 259 struct zy7_gpio_softc *sc; 260 uint32_t emio_min; 261 bool is_mio; 262 263 sc = device_get_softc(dev); 264 if (!zy7_pin_valid(dev, pin)) 265 return (EINVAL); 266 267 switch (sc->conf->type) { 268 case ZYNQ_7000: 269 is_mio = ZYNQ_PIN_IS_MIO(7, pin); 270 emio_min = ZYNQ7_PIN_EMIO_MIN; 271 break; 272 case ZYNQMP: 273 is_mio = ZYNQ_PIN_IS_MIO(MP, pin); 274 emio_min = ZYNQMP_PIN_EMIO_MIN; 275 break; 276 default: 277 return (EINVAL); 278 } 279 if (is_mio) { 280 snprintf(name, GPIOMAXNAME, "MIO_%d", pin); 281 name[GPIOMAXNAME - 1] = '\0'; 282 } else { 283 snprintf(name, GPIOMAXNAME, "EMIO_%d", pin - emio_min); 284 name[GPIOMAXNAME - 1] = '\0'; 285 } 286 287 return (0); 288 } 289 290 /* Get a specific pin's current in/out/tri state. */ 291 static int 292 zy7_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 293 { 294 struct zy7_gpio_softc *sc = device_get_softc(dev); 295 296 if (!zy7_pin_valid(dev, pin)) 297 return (EINVAL); 298 299 ZGPIO_LOCK(sc); 300 301 if ((RD4(sc, ZY7_GPIO_DIRM(pin >> 5)) & (1 << (pin & 31))) != 0) { 302 /* output */ 303 if ((RD4(sc, ZY7_GPIO_OEN(pin >> 5)) & (1 << (pin & 31))) == 0) 304 *flags = (GPIO_PIN_OUTPUT | GPIO_PIN_TRISTATE); 305 else 306 *flags = GPIO_PIN_OUTPUT; 307 } else 308 /* input */ 309 *flags = GPIO_PIN_INPUT; 310 311 ZGPIO_UNLOCK(sc); 312 313 return (0); 314 } 315 316 /* Set a specific pin's in/out/tri state. */ 317 static int 318 zy7_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 319 { 320 struct zy7_gpio_softc *sc = device_get_softc(dev); 321 322 if (!zy7_pin_valid(dev, pin)) 323 return (EINVAL); 324 325 ZGPIO_LOCK(sc); 326 327 if ((flags & GPIO_PIN_OUTPUT) != 0) { 328 /* Output. Set or reset OEN too. */ 329 WR4(sc, ZY7_GPIO_DIRM(pin >> 5), 330 RD4(sc, ZY7_GPIO_DIRM(pin >> 5)) | (1 << (pin & 31))); 331 332 if ((flags & GPIO_PIN_TRISTATE) != 0) 333 WR4(sc, ZY7_GPIO_OEN(pin >> 5), 334 RD4(sc, ZY7_GPIO_OEN(pin >> 5)) & 335 ~(1 << (pin & 31))); 336 else 337 WR4(sc, ZY7_GPIO_OEN(pin >> 5), 338 RD4(sc, ZY7_GPIO_OEN(pin >> 5)) | 339 (1 << (pin & 31))); 340 } else { 341 /* Input. Turn off OEN. */ 342 WR4(sc, ZY7_GPIO_DIRM(pin >> 5), 343 RD4(sc, ZY7_GPIO_DIRM(pin >> 5)) & ~(1 << (pin & 31))); 344 WR4(sc, ZY7_GPIO_OEN(pin >> 5), 345 RD4(sc, ZY7_GPIO_OEN(pin >> 5)) & ~(1 << (pin & 31))); 346 } 347 348 ZGPIO_UNLOCK(sc); 349 350 return (0); 351 } 352 353 /* Set a specific output pin's value. */ 354 static int 355 zy7_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) 356 { 357 struct zy7_gpio_softc *sc = device_get_softc(dev); 358 359 if (!zy7_pin_valid(dev, pin) || value > 1) 360 return (EINVAL); 361 362 /* Fancy register tricks allow atomic set or reset. */ 363 if ((pin & 16) != 0) 364 WR4(sc, ZY7_GPIO_MASK_DATA_MSW(pin >> 5), 365 (0xffff0000 ^ (0x10000 << (pin & 15))) | 366 (value << (pin & 15))); 367 else 368 WR4(sc, ZY7_GPIO_MASK_DATA_LSW(pin >> 5), 369 (0xffff0000 ^ (0x10000 << (pin & 15))) | 370 (value << (pin & 15))); 371 372 return (0); 373 } 374 375 /* Get a specific pin's input value. */ 376 static int 377 zy7_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value) 378 { 379 struct zy7_gpio_softc *sc = device_get_softc(dev); 380 381 if (!zy7_pin_valid(dev, pin)) 382 return (EINVAL); 383 384 *value = (RD4(sc, ZY7_GPIO_DATA_RO(pin >> 5)) >> (pin & 31)) & 1; 385 386 return (0); 387 } 388 389 /* Toggle a pin's output value. */ 390 static int 391 zy7_gpio_pin_toggle(device_t dev, uint32_t pin) 392 { 393 struct zy7_gpio_softc *sc = device_get_softc(dev); 394 395 if (!zy7_pin_valid(dev, pin)) 396 return (EINVAL); 397 398 ZGPIO_LOCK(sc); 399 400 WR4(sc, ZY7_GPIO_DATA(pin >> 5), 401 RD4(sc, ZY7_GPIO_DATA(pin >> 5)) ^ (1 << (pin & 31))); 402 403 ZGPIO_UNLOCK(sc); 404 405 return (0); 406 } 407 408 static int 409 zy7_gpio_probe(device_t dev) 410 { 411 struct zynq_gpio_conf *conf; 412 413 if (!ofw_bus_status_okay(dev)) 414 return (ENXIO); 415 416 conf = (struct zynq_gpio_conf *)ofw_bus_search_compatible(dev, compat_data)->ocd_data; 417 if (conf == 0) 418 return (ENXIO); 419 420 device_set_desc(dev, conf->name); 421 return (0); 422 } 423 424 static int zy7_gpio_detach(device_t dev); 425 426 static int 427 zy7_gpio_attach(device_t dev) 428 { 429 struct zy7_gpio_softc *sc = device_get_softc(dev); 430 int rid; 431 432 sc->dev = dev; 433 sc->conf = (struct zynq_gpio_conf *)ofw_bus_search_compatible(dev, compat_data)->ocd_data; 434 435 ZGPIO_LOCK_INIT(sc); 436 437 /* Allocate memory. */ 438 rid = 0; 439 sc->mem_res = bus_alloc_resource_any(dev, 440 SYS_RES_MEMORY, &rid, RF_ACTIVE); 441 if (sc->mem_res == NULL) { 442 device_printf(dev, "Can't allocate memory for device"); 443 zy7_gpio_detach(dev); 444 return (ENOMEM); 445 } 446 447 sc->busdev = gpiobus_attach_bus(dev); 448 if (sc->busdev == NULL) { 449 zy7_gpio_detach(dev); 450 return (ENOMEM); 451 } 452 453 return (0); 454 } 455 456 static int 457 zy7_gpio_detach(device_t dev) 458 { 459 struct zy7_gpio_softc *sc = device_get_softc(dev); 460 461 gpiobus_detach_bus(dev); 462 463 if (sc->mem_res != NULL) { 464 /* Release memory resource. */ 465 bus_release_resource(dev, SYS_RES_MEMORY, 466 rman_get_rid(sc->mem_res), sc->mem_res); 467 } 468 469 ZGPIO_LOCK_DESTROY(sc); 470 471 return (0); 472 } 473 474 static device_method_t zy7_gpio_methods[] = { 475 /* device_if */ 476 DEVMETHOD(device_probe, zy7_gpio_probe), 477 DEVMETHOD(device_attach, zy7_gpio_attach), 478 DEVMETHOD(device_detach, zy7_gpio_detach), 479 480 /* GPIO protocol */ 481 DEVMETHOD(gpio_get_bus, zy7_gpio_get_bus), 482 DEVMETHOD(gpio_pin_max, zy7_gpio_pin_max), 483 DEVMETHOD(gpio_pin_getname, zy7_gpio_pin_getname), 484 DEVMETHOD(gpio_pin_getflags, zy7_gpio_pin_getflags), 485 DEVMETHOD(gpio_pin_getcaps, zy7_gpio_pin_getcaps), 486 DEVMETHOD(gpio_pin_setflags, zy7_gpio_pin_setflags), 487 DEVMETHOD(gpio_pin_get, zy7_gpio_pin_get), 488 DEVMETHOD(gpio_pin_set, zy7_gpio_pin_set), 489 DEVMETHOD(gpio_pin_toggle, zy7_gpio_pin_toggle), 490 491 DEVMETHOD_END 492 }; 493 494 static driver_t zy7_gpio_driver = { 495 "gpio", 496 zy7_gpio_methods, 497 sizeof(struct zy7_gpio_softc), 498 }; 499 500 EARLY_DRIVER_MODULE(zy7_gpio, simplebus, zy7_gpio_driver, 0, 0, 501 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE); 502