1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2013 Thomas Skibo 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 /* 32 * A GPIO driver for Xilinx Zynq-7000. 33 * 34 * The GPIO peripheral on Zynq allows controlling 114 general purpose I/Os. 35 * 36 * Pins 53-0 are sent to the MIO. Any MIO pins not used by a PS peripheral are 37 * available as a GPIO pin. Pins 64-127 are sent to the PL (FPGA) section of 38 * Zynq as EMIO signals. 39 * 40 * The hardware provides a way to use IOs as interrupt sources but the 41 * gpio framework doesn't seem to have hooks for this. 42 * 43 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual. 44 * (v1.4) November 16, 2012. Xilinx doc UG585. GPIO is covered in 45 * chater 14. Register definitions are in appendix B.19. 46 */ 47 48 #include <sys/cdefs.h> 49 __FBSDID("$FreeBSD$"); 50 51 #include <sys/param.h> 52 #include <sys/systm.h> 53 #include <sys/conf.h> 54 #include <sys/bus.h> 55 #include <sys/kernel.h> 56 #include <sys/module.h> 57 #include <sys/lock.h> 58 #include <sys/mutex.h> 59 #include <sys/resource.h> 60 #include <sys/rman.h> 61 #include <sys/gpio.h> 62 63 #include <machine/bus.h> 64 #include <machine/resource.h> 65 #include <machine/stdarg.h> 66 67 #include <dev/gpio/gpiobusvar.h> 68 #include <dev/ofw/ofw_bus.h> 69 #include <dev/ofw/ofw_bus_subr.h> 70 71 #include "gpio_if.h" 72 73 #define NUMBANKS 4 74 #define MAXPIN (32*NUMBANKS) 75 76 #define MIO_PIN 0 /* pins 0-53 go to MIO */ 77 #define NUM_MIO_PINS 54 78 #define EMIO_PIN 64 /* pins 64-127 go to PL */ 79 #define NUM_EMIO_PINS 64 80 81 #define VALID_PIN(u) (((u) >= MIO_PIN && (u) < MIO_PIN + NUM_MIO_PINS) || \ 82 ((u) >= EMIO_PIN && (u) < EMIO_PIN + NUM_EMIO_PINS)) 83 84 #define ZGPIO_LOCK(sc) mtx_lock(&(sc)->sc_mtx) 85 #define ZGPIO_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx) 86 #define ZGPIO_LOCK_INIT(sc) \ 87 mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev), \ 88 "gpio", MTX_DEF) 89 #define ZGPIO_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); 90 91 struct zy7_gpio_softc { 92 device_t dev; 93 device_t busdev; 94 struct mtx sc_mtx; 95 struct resource *mem_res; /* Memory resource */ 96 }; 97 98 #define WR4(sc, off, val) bus_write_4((sc)->mem_res, (off), (val)) 99 #define RD4(sc, off) bus_read_4((sc)->mem_res, (off)) 100 101 102 /* Xilinx Zynq-7000 GPIO register definitions: 103 */ 104 #define ZY7_GPIO_MASK_DATA_LSW(b) (0x0000+8*(b)) /* maskable wr lo */ 105 #define ZY7_GPIO_MASK_DATA_MSW(b) (0x0004+8*(b)) /* maskable wr hi */ 106 #define ZY7_GPIO_DATA(b) (0x0040+4*(b)) /* in/out data */ 107 #define ZY7_GPIO_DATA_RO(b) (0x0060+4*(b)) /* input data */ 108 109 #define ZY7_GPIO_DIRM(b) (0x0204+0x40*(b)) /* direction mode */ 110 #define ZY7_GPIO_OEN(b) (0x0208+0x40*(b)) /* output enable */ 111 #define ZY7_GPIO_INT_MASK(b) (0x020c+0x40*(b)) /* int mask */ 112 #define ZY7_GPIO_INT_EN(b) (0x0210+0x40*(b)) /* int enable */ 113 #define ZY7_GPIO_INT_DIS(b) (0x0214+0x40*(b)) /* int disable */ 114 #define ZY7_GPIO_INT_STAT(b) (0x0218+0x40*(b)) /* int status */ 115 #define ZY7_GPIO_INT_TYPE(b) (0x021c+0x40*(b)) /* int type */ 116 #define ZY7_GPIO_INT_POLARITY(b) (0x0220+0x40*(b)) /* int polarity */ 117 #define ZY7_GPIO_INT_ANY(b) (0x0224+0x40*(b)) /* any edge */ 118 119 static device_t 120 zy7_gpio_get_bus(device_t dev) 121 { 122 struct zy7_gpio_softc *sc; 123 124 sc = device_get_softc(dev); 125 126 return (sc->busdev); 127 } 128 129 static int 130 zy7_gpio_pin_max(device_t dev, int *maxpin) 131 { 132 133 *maxpin = MAXPIN; 134 return (0); 135 } 136 137 /* Get a specific pin's capabilities. */ 138 static int 139 zy7_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 140 { 141 142 if (!VALID_PIN(pin)) 143 return (EINVAL); 144 145 *caps = (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_TRISTATE); 146 147 return (0); 148 } 149 150 /* Get a specific pin's name. */ 151 static int 152 zy7_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 153 { 154 155 if (!VALID_PIN(pin)) 156 return (EINVAL); 157 158 if (pin < NUM_MIO_PINS) { 159 snprintf(name, GPIOMAXNAME, "MIO_%d", pin); 160 name[GPIOMAXNAME - 1] = '\0'; 161 } else { 162 snprintf(name, GPIOMAXNAME, "EMIO_%d", pin - EMIO_PIN); 163 name[GPIOMAXNAME - 1] = '\0'; 164 } 165 166 return (0); 167 } 168 169 /* Get a specific pin's current in/out/tri state. */ 170 static int 171 zy7_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 172 { 173 struct zy7_gpio_softc *sc = device_get_softc(dev); 174 175 if (!VALID_PIN(pin)) 176 return (EINVAL); 177 178 ZGPIO_LOCK(sc); 179 180 if ((RD4(sc, ZY7_GPIO_DIRM(pin >> 5)) & (1 << (pin & 31))) != 0) { 181 /* output */ 182 if ((RD4(sc, ZY7_GPIO_OEN(pin >> 5)) & (1 << (pin & 31))) == 0) 183 *flags = (GPIO_PIN_OUTPUT | GPIO_PIN_TRISTATE); 184 else 185 *flags = GPIO_PIN_OUTPUT; 186 } else 187 /* input */ 188 *flags = GPIO_PIN_INPUT; 189 190 ZGPIO_UNLOCK(sc); 191 192 return (0); 193 } 194 195 /* Set a specific pin's in/out/tri state. */ 196 static int 197 zy7_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 198 { 199 struct zy7_gpio_softc *sc = device_get_softc(dev); 200 201 if (!VALID_PIN(pin)) 202 return (EINVAL); 203 204 ZGPIO_LOCK(sc); 205 206 if ((flags & GPIO_PIN_OUTPUT) != 0) { 207 /* Output. Set or reset OEN too. */ 208 WR4(sc, ZY7_GPIO_DIRM(pin >> 5), 209 RD4(sc, ZY7_GPIO_DIRM(pin >> 5)) | (1 << (pin & 31))); 210 211 if ((flags & GPIO_PIN_TRISTATE) != 0) 212 WR4(sc, ZY7_GPIO_OEN(pin >> 5), 213 RD4(sc, ZY7_GPIO_OEN(pin >> 5)) & 214 ~(1 << (pin & 31))); 215 else 216 WR4(sc, ZY7_GPIO_OEN(pin >> 5), 217 RD4(sc, ZY7_GPIO_OEN(pin >> 5)) | 218 (1 << (pin & 31))); 219 } else { 220 /* Input. Turn off OEN. */ 221 WR4(sc, ZY7_GPIO_DIRM(pin >> 5), 222 RD4(sc, ZY7_GPIO_DIRM(pin >> 5)) & ~(1 << (pin & 31))); 223 WR4(sc, ZY7_GPIO_OEN(pin >> 5), 224 RD4(sc, ZY7_GPIO_OEN(pin >> 5)) & ~(1 << (pin & 31))); 225 } 226 227 ZGPIO_UNLOCK(sc); 228 229 return (0); 230 } 231 232 /* Set a specific output pin's value. */ 233 static int 234 zy7_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) 235 { 236 struct zy7_gpio_softc *sc = device_get_softc(dev); 237 238 if (!VALID_PIN(pin) || value > 1) 239 return (EINVAL); 240 241 /* Fancy register tricks allow atomic set or reset. */ 242 if ((pin & 16) != 0) 243 WR4(sc, ZY7_GPIO_MASK_DATA_MSW(pin >> 5), 244 (0xffff0000 ^ (0x10000 << (pin & 15))) | 245 (value << (pin & 15))); 246 else 247 WR4(sc, ZY7_GPIO_MASK_DATA_LSW(pin >> 5), 248 (0xffff0000 ^ (0x10000 << (pin & 15))) | 249 (value << (pin & 15))); 250 251 return (0); 252 } 253 254 /* Get a specific pin's input value. */ 255 static int 256 zy7_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value) 257 { 258 struct zy7_gpio_softc *sc = device_get_softc(dev); 259 260 if (!VALID_PIN(pin)) 261 return (EINVAL); 262 263 *value = (RD4(sc, ZY7_GPIO_DATA_RO(pin >> 5)) >> (pin & 31)) & 1; 264 265 return (0); 266 } 267 268 /* Toggle a pin's output value. */ 269 static int 270 zy7_gpio_pin_toggle(device_t dev, uint32_t pin) 271 { 272 struct zy7_gpio_softc *sc = device_get_softc(dev); 273 274 if (!VALID_PIN(pin)) 275 return (EINVAL); 276 277 ZGPIO_LOCK(sc); 278 279 WR4(sc, ZY7_GPIO_DATA(pin >> 5), 280 RD4(sc, ZY7_GPIO_DATA(pin >> 5)) ^ (1 << (pin & 31))); 281 282 ZGPIO_UNLOCK(sc); 283 284 return (0); 285 } 286 287 static int 288 zy7_gpio_probe(device_t dev) 289 { 290 291 if (!ofw_bus_status_okay(dev)) 292 return (ENXIO); 293 294 if (!ofw_bus_is_compatible(dev, "xlnx,zy7_gpio")) 295 return (ENXIO); 296 297 device_set_desc(dev, "Zynq-7000 GPIO driver"); 298 return (0); 299 } 300 301 static void 302 zy7_gpio_hw_reset(struct zy7_gpio_softc *sc) 303 { 304 int i; 305 306 for (i = 0; i < NUMBANKS; i++) { 307 WR4(sc, ZY7_GPIO_DATA(i), 0); 308 WR4(sc, ZY7_GPIO_DIRM(i), 0); 309 WR4(sc, ZY7_GPIO_OEN(i), 0); 310 WR4(sc, ZY7_GPIO_INT_DIS(i), 0xffffffff); 311 WR4(sc, ZY7_GPIO_INT_POLARITY(i), 0); 312 WR4(sc, ZY7_GPIO_INT_TYPE(i), 313 i == 1 ? 0x003fffff : 0xffffffff); 314 WR4(sc, ZY7_GPIO_INT_ANY(i), 0); 315 WR4(sc, ZY7_GPIO_INT_STAT(i), 0xffffffff); 316 } 317 } 318 319 static int zy7_gpio_detach(device_t dev); 320 321 static int 322 zy7_gpio_attach(device_t dev) 323 { 324 struct zy7_gpio_softc *sc = device_get_softc(dev); 325 int rid; 326 327 sc->dev = dev; 328 329 ZGPIO_LOCK_INIT(sc); 330 331 /* Allocate memory. */ 332 rid = 0; 333 sc->mem_res = bus_alloc_resource_any(dev, 334 SYS_RES_MEMORY, &rid, RF_ACTIVE); 335 if (sc->mem_res == NULL) { 336 device_printf(dev, "Can't allocate memory for device"); 337 zy7_gpio_detach(dev); 338 return (ENOMEM); 339 } 340 341 /* Completely reset. */ 342 zy7_gpio_hw_reset(sc); 343 344 sc->busdev = gpiobus_attach_bus(dev); 345 if (sc->busdev == NULL) { 346 zy7_gpio_detach(dev); 347 return (ENOMEM); 348 } 349 350 return (0); 351 } 352 353 static int 354 zy7_gpio_detach(device_t dev) 355 { 356 struct zy7_gpio_softc *sc = device_get_softc(dev); 357 358 gpiobus_detach_bus(dev); 359 360 if (sc->mem_res != NULL) { 361 /* Release memory resource. */ 362 bus_release_resource(dev, SYS_RES_MEMORY, 363 rman_get_rid(sc->mem_res), sc->mem_res); 364 } 365 366 ZGPIO_LOCK_DESTROY(sc); 367 368 return (0); 369 } 370 371 static device_method_t zy7_gpio_methods[] = { 372 /* device_if */ 373 DEVMETHOD(device_probe, zy7_gpio_probe), 374 DEVMETHOD(device_attach, zy7_gpio_attach), 375 DEVMETHOD(device_detach, zy7_gpio_detach), 376 377 /* GPIO protocol */ 378 DEVMETHOD(gpio_get_bus, zy7_gpio_get_bus), 379 DEVMETHOD(gpio_pin_max, zy7_gpio_pin_max), 380 DEVMETHOD(gpio_pin_getname, zy7_gpio_pin_getname), 381 DEVMETHOD(gpio_pin_getflags, zy7_gpio_pin_getflags), 382 DEVMETHOD(gpio_pin_getcaps, zy7_gpio_pin_getcaps), 383 DEVMETHOD(gpio_pin_setflags, zy7_gpio_pin_setflags), 384 DEVMETHOD(gpio_pin_get, zy7_gpio_pin_get), 385 DEVMETHOD(gpio_pin_set, zy7_gpio_pin_set), 386 DEVMETHOD(gpio_pin_toggle, zy7_gpio_pin_toggle), 387 388 DEVMETHOD_END 389 }; 390 391 static driver_t zy7_gpio_driver = { 392 "gpio", 393 zy7_gpio_methods, 394 sizeof(struct zy7_gpio_softc), 395 }; 396 static devclass_t zy7_gpio_devclass; 397 398 DRIVER_MODULE(zy7_gpio, simplebus, zy7_gpio_driver, zy7_gpio_devclass, \ 399 NULL, NULL); 400