1 /*- 2 * Copyright (c) 2013 Thomas Skibo 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 /* 30 * A GPIO driver for Xilinx Zynq-7000. 31 * 32 * The GPIO peripheral on Zynq allows controlling 114 general purpose I/Os. 33 * 34 * Pins 53-0 are sent to the MIO. Any MIO pins not used by a PS peripheral are 35 * available as a GPIO pin. Pins 64-127 are sent to the PL (FPGA) section of 36 * Zynq as EMIO signals. 37 * 38 * The hardware provides a way to use IOs as interrupt sources but the 39 * gpio framework doesn't seem to have hooks for this. 40 * 41 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual. 42 * (v1.4) November 16, 2012. Xilinx doc UG585. GPIO is covered in 43 * chater 14. Register definitions are in appendix B.19. 44 */ 45 46 #include <sys/cdefs.h> 47 __FBSDID("$FreeBSD$"); 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/conf.h> 52 #include <sys/bus.h> 53 #include <sys/kernel.h> 54 #include <sys/module.h> 55 #include <sys/lock.h> 56 #include <sys/mutex.h> 57 #include <sys/resource.h> 58 #include <sys/rman.h> 59 #include <sys/gpio.h> 60 61 #include <machine/bus.h> 62 #include <machine/resource.h> 63 #include <machine/stdarg.h> 64 65 #include <dev/fdt/fdt_common.h> 66 #include <dev/gpio/gpiobusvar.h> 67 #include <dev/ofw/ofw_bus.h> 68 #include <dev/ofw/ofw_bus_subr.h> 69 70 #include "gpio_if.h" 71 72 #define NUMBANKS 4 73 #define MAXPIN (32*NUMBANKS) 74 75 #define MIO_PIN 0 /* pins 0-53 go to MIO */ 76 #define NUM_MIO_PINS 54 77 #define EMIO_PIN 64 /* pins 64-127 go to PL */ 78 #define NUM_EMIO_PINS 64 79 80 #define VALID_PIN(u) (((u) >= MIO_PIN && (u) < MIO_PIN + NUM_MIO_PINS) || \ 81 ((u) >= EMIO_PIN && (u) < EMIO_PIN + NUM_EMIO_PINS)) 82 83 #define ZGPIO_LOCK(sc) mtx_lock(&(sc)->sc_mtx) 84 #define ZGPIO_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx) 85 #define ZGPIO_LOCK_INIT(sc) \ 86 mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev), \ 87 "gpio", MTX_DEF) 88 #define ZGPIO_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); 89 90 struct zy7_gpio_softc { 91 device_t dev; 92 device_t busdev; 93 struct mtx sc_mtx; 94 struct resource *mem_res; /* Memory resource */ 95 }; 96 97 #define WR4(sc, off, val) bus_write_4((sc)->mem_res, (off), (val)) 98 #define RD4(sc, off) bus_read_4((sc)->mem_res, (off)) 99 100 101 /* Xilinx Zynq-7000 GPIO register definitions: 102 */ 103 #define ZY7_GPIO_MASK_DATA_LSW(b) (0x0000+8*(b)) /* maskable wr lo */ 104 #define ZY7_GPIO_MASK_DATA_MSW(b) (0x0004+8*(b)) /* maskable wr hi */ 105 #define ZY7_GPIO_DATA(b) (0x0040+4*(b)) /* in/out data */ 106 #define ZY7_GPIO_DATA_RO(b) (0x0060+4*(b)) /* input data */ 107 108 #define ZY7_GPIO_DIRM(b) (0x0204+0x40*(b)) /* direction mode */ 109 #define ZY7_GPIO_OEN(b) (0x0208+0x40*(b)) /* output enable */ 110 #define ZY7_GPIO_INT_MASK(b) (0x020c+0x40*(b)) /* int mask */ 111 #define ZY7_GPIO_INT_EN(b) (0x0210+0x40*(b)) /* int enable */ 112 #define ZY7_GPIO_INT_DIS(b) (0x0214+0x40*(b)) /* int disable */ 113 #define ZY7_GPIO_INT_STAT(b) (0x0218+0x40*(b)) /* int status */ 114 #define ZY7_GPIO_INT_TYPE(b) (0x021c+0x40*(b)) /* int type */ 115 #define ZY7_GPIO_INT_POLARITY(b) (0x0220+0x40*(b)) /* int polarity */ 116 #define ZY7_GPIO_INT_ANY(b) (0x0224+0x40*(b)) /* any edge */ 117 118 static device_t 119 zy7_gpio_get_bus(device_t dev) 120 { 121 struct zy7_gpio_softc *sc; 122 123 sc = device_get_softc(dev); 124 125 return (sc->busdev); 126 } 127 128 static int 129 zy7_gpio_pin_max(device_t dev, int *maxpin) 130 { 131 132 *maxpin = MAXPIN; 133 return (0); 134 } 135 136 /* Get a specific pin's capabilities. */ 137 static int 138 zy7_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 139 { 140 141 if (!VALID_PIN(pin)) 142 return (EINVAL); 143 144 *caps = (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_TRISTATE); 145 146 return (0); 147 } 148 149 /* Get a specific pin's name. */ 150 static int 151 zy7_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 152 { 153 154 if (!VALID_PIN(pin)) 155 return (EINVAL); 156 157 if (pin < NUM_MIO_PINS) { 158 snprintf(name, GPIOMAXNAME, "MIO_%d", pin); 159 name[GPIOMAXNAME - 1] = '\0'; 160 } else { 161 snprintf(name, GPIOMAXNAME, "EMIO_%d", pin - EMIO_PIN); 162 name[GPIOMAXNAME - 1] = '\0'; 163 } 164 165 return (0); 166 } 167 168 /* Get a specific pin's current in/out/tri state. */ 169 static int 170 zy7_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 171 { 172 struct zy7_gpio_softc *sc = device_get_softc(dev); 173 174 if (!VALID_PIN(pin)) 175 return (EINVAL); 176 177 ZGPIO_LOCK(sc); 178 179 if ((RD4(sc, ZY7_GPIO_DIRM(pin >> 5)) & (1 << (pin & 31))) != 0) { 180 /* output */ 181 if ((RD4(sc, ZY7_GPIO_OEN(pin >> 5)) & (1 << (pin & 31))) == 0) 182 *flags = (GPIO_PIN_OUTPUT | GPIO_PIN_TRISTATE); 183 else 184 *flags = GPIO_PIN_OUTPUT; 185 } else 186 /* input */ 187 *flags = GPIO_PIN_INPUT; 188 189 ZGPIO_UNLOCK(sc); 190 191 return (0); 192 } 193 194 /* Set a specific pin's in/out/tri state. */ 195 static int 196 zy7_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 197 { 198 struct zy7_gpio_softc *sc = device_get_softc(dev); 199 200 if (!VALID_PIN(pin)) 201 return (EINVAL); 202 203 ZGPIO_LOCK(sc); 204 205 if ((flags & GPIO_PIN_OUTPUT) != 0) { 206 /* Output. Set or reset OEN too. */ 207 WR4(sc, ZY7_GPIO_DIRM(pin >> 5), 208 RD4(sc, ZY7_GPIO_DIRM(pin >> 5)) | (1 << (pin & 31))); 209 210 if ((flags & GPIO_PIN_TRISTATE) != 0) 211 WR4(sc, ZY7_GPIO_OEN(pin >> 5), 212 RD4(sc, ZY7_GPIO_OEN(pin >> 5)) & 213 ~(1 << (pin & 31))); 214 else 215 WR4(sc, ZY7_GPIO_OEN(pin >> 5), 216 RD4(sc, ZY7_GPIO_OEN(pin >> 5)) | 217 (1 << (pin & 31))); 218 } else { 219 /* Input. Turn off OEN. */ 220 WR4(sc, ZY7_GPIO_DIRM(pin >> 5), 221 RD4(sc, ZY7_GPIO_DIRM(pin >> 5)) & ~(1 << (pin & 31))); 222 WR4(sc, ZY7_GPIO_OEN(pin >> 5), 223 RD4(sc, ZY7_GPIO_OEN(pin >> 5)) & ~(1 << (pin & 31))); 224 } 225 226 ZGPIO_UNLOCK(sc); 227 228 return (0); 229 } 230 231 /* Set a specific output pin's value. */ 232 static int 233 zy7_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) 234 { 235 struct zy7_gpio_softc *sc = device_get_softc(dev); 236 237 if (!VALID_PIN(pin) || value > 1) 238 return (EINVAL); 239 240 /* Fancy register tricks allow atomic set or reset. */ 241 if ((pin & 16) != 0) 242 WR4(sc, ZY7_GPIO_MASK_DATA_MSW(pin >> 5), 243 (0xffff0000 ^ (0x10000 << (pin & 15))) | 244 (value << (pin & 15))); 245 else 246 WR4(sc, ZY7_GPIO_MASK_DATA_LSW(pin >> 5), 247 (0xffff0000 ^ (0x10000 << (pin & 15))) | 248 (value << (pin & 15))); 249 250 return (0); 251 } 252 253 /* Get a specific pin's input value. */ 254 static int 255 zy7_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value) 256 { 257 struct zy7_gpio_softc *sc = device_get_softc(dev); 258 259 if (!VALID_PIN(pin)) 260 return (EINVAL); 261 262 *value = (RD4(sc, ZY7_GPIO_DATA_RO(pin >> 5)) >> (pin & 31)) & 1; 263 264 return (0); 265 } 266 267 /* Toggle a pin's output value. */ 268 static int 269 zy7_gpio_pin_toggle(device_t dev, uint32_t pin) 270 { 271 struct zy7_gpio_softc *sc = device_get_softc(dev); 272 273 if (!VALID_PIN(pin)) 274 return (EINVAL); 275 276 ZGPIO_LOCK(sc); 277 278 WR4(sc, ZY7_GPIO_DATA(pin >> 5), 279 RD4(sc, ZY7_GPIO_DATA(pin >> 5)) ^ (1 << (pin & 31))); 280 281 ZGPIO_UNLOCK(sc); 282 283 return (0); 284 } 285 286 static int 287 zy7_gpio_probe(device_t dev) 288 { 289 290 if (!ofw_bus_status_okay(dev)) 291 return (ENXIO); 292 293 if (!ofw_bus_is_compatible(dev, "xlnx,zy7_gpio")) 294 return (ENXIO); 295 296 device_set_desc(dev, "Zynq-7000 GPIO driver"); 297 return (0); 298 } 299 300 static void 301 zy7_gpio_hw_reset(struct zy7_gpio_softc *sc) 302 { 303 int i; 304 305 for (i = 0; i < NUMBANKS; i++) { 306 WR4(sc, ZY7_GPIO_DATA(i), 0); 307 WR4(sc, ZY7_GPIO_DIRM(i), 0); 308 WR4(sc, ZY7_GPIO_OEN(i), 0); 309 WR4(sc, ZY7_GPIO_INT_DIS(i), 0xffffffff); 310 WR4(sc, ZY7_GPIO_INT_POLARITY(i), 0); 311 WR4(sc, ZY7_GPIO_INT_TYPE(i), 312 i == 1 ? 0x003fffff : 0xffffffff); 313 WR4(sc, ZY7_GPIO_INT_ANY(i), 0); 314 WR4(sc, ZY7_GPIO_INT_STAT(i), 0xffffffff); 315 } 316 } 317 318 static int zy7_gpio_detach(device_t dev); 319 320 static int 321 zy7_gpio_attach(device_t dev) 322 { 323 struct zy7_gpio_softc *sc = device_get_softc(dev); 324 int rid; 325 326 sc->dev = dev; 327 328 ZGPIO_LOCK_INIT(sc); 329 330 /* Allocate memory. */ 331 rid = 0; 332 sc->mem_res = bus_alloc_resource_any(dev, 333 SYS_RES_MEMORY, &rid, RF_ACTIVE); 334 if (sc->mem_res == NULL) { 335 device_printf(dev, "Can't allocate memory for device"); 336 zy7_gpio_detach(dev); 337 return (ENOMEM); 338 } 339 340 /* Completely reset. */ 341 zy7_gpio_hw_reset(sc); 342 343 sc->busdev = gpiobus_attach_bus(dev); 344 if (sc->busdev == NULL) { 345 zy7_gpio_detach(dev); 346 return (ENOMEM); 347 } 348 349 return (0); 350 } 351 352 static int 353 zy7_gpio_detach(device_t dev) 354 { 355 struct zy7_gpio_softc *sc = device_get_softc(dev); 356 357 gpiobus_detach_bus(dev); 358 359 if (sc->mem_res != NULL) { 360 /* Release memory resource. */ 361 bus_release_resource(dev, SYS_RES_MEMORY, 362 rman_get_rid(sc->mem_res), sc->mem_res); 363 } 364 365 ZGPIO_LOCK_DESTROY(sc); 366 367 return (0); 368 } 369 370 static device_method_t zy7_gpio_methods[] = { 371 /* device_if */ 372 DEVMETHOD(device_probe, zy7_gpio_probe), 373 DEVMETHOD(device_attach, zy7_gpio_attach), 374 DEVMETHOD(device_detach, zy7_gpio_detach), 375 376 /* GPIO protocol */ 377 DEVMETHOD(gpio_get_bus, zy7_gpio_get_bus), 378 DEVMETHOD(gpio_pin_max, zy7_gpio_pin_max), 379 DEVMETHOD(gpio_pin_getname, zy7_gpio_pin_getname), 380 DEVMETHOD(gpio_pin_getflags, zy7_gpio_pin_getflags), 381 DEVMETHOD(gpio_pin_getcaps, zy7_gpio_pin_getcaps), 382 DEVMETHOD(gpio_pin_setflags, zy7_gpio_pin_setflags), 383 DEVMETHOD(gpio_pin_get, zy7_gpio_pin_get), 384 DEVMETHOD(gpio_pin_set, zy7_gpio_pin_set), 385 DEVMETHOD(gpio_pin_toggle, zy7_gpio_pin_toggle), 386 387 DEVMETHOD_END 388 }; 389 390 static driver_t zy7_gpio_driver = { 391 "gpio", 392 zy7_gpio_methods, 393 sizeof(struct zy7_gpio_softc), 394 }; 395 static devclass_t zy7_gpio_devclass; 396 397 DRIVER_MODULE(zy7_gpio, simplebus, zy7_gpio_driver, zy7_gpio_devclass, \ 398 NULL, NULL); 399