xref: /freebsd/sys/arm/xilinx/uart_dev_cdnc.c (revision ec273ebf3b6aed5fba8c56b6ece5ad8693a48ea7)
1 /*-
2  * Copyright (c) 2005 M. Warner Losh
3  * Copyright (c) 2005 Olivier Houchard
4  * Copyright (c) 2012 Thomas Skibo
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  *
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  *
17  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27  * SUCH DAMAGE.
28  */
29 
30 /* A driver for the Cadence AMBA UART as used by the Xilinx Zynq-7000.
31  *
32  * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
33  * (v1.4) November 16, 2012.  Xilinx doc UG585.  UART is covered in Ch. 19
34  * and register definitions are in appendix B.33.
35  */
36 
37 
38 #include <sys/cdefs.h>
39 __FBSDID("$FreeBSD$");
40 
41 #include <sys/param.h>
42 #include <sys/systm.h>
43 #include <sys/bus.h>
44 #include <sys/conf.h>
45 #include <sys/cons.h>
46 #include <sys/tty.h>
47 #include <machine/bus.h>
48 
49 #include <dev/uart/uart.h>
50 #include <dev/uart/uart_cpu.h>
51 #include <dev/uart/uart_bus.h>
52 
53 #include "uart_if.h"
54 
55 #define	UART_FIFO_SIZE	64
56 
57 #define	RD4(bas, reg)		\
58 	bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs((bas), (reg)))
59 #define	WR4(bas, reg, value)	\
60 	bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs((bas), (reg)), \
61 			  (value))
62 
63 /* Register definitions for Cadence UART Controller.
64  */
65 #define CDNC_UART_CTRL_REG	0x00		/* Control Register. */
66 #define CDNC_UART_CTRL_REG_STOPBRK	(1<<8)
67 #define CDNC_UART_CTRL_REG_STARTBRK	(1<<7)
68 #define CDNC_UART_CTRL_REG_TORST	(1<<6)
69 #define CDNC_UART_CTRL_REG_TX_DIS	(1<<5)
70 #define CDNC_UART_CTRL_REG_TX_EN	(1<<4)
71 #define CDNC_UART_CTRL_REG_RX_DIS	(1<<3)
72 #define CDNC_UART_CTRL_REG_RX_EN	(1<<2)
73 #define CDNC_UART_CTRL_REG_TXRST	(1<<1)
74 #define CDNC_UART_CTRL_REG_RXRST	(1<<0)
75 
76 #define CDNC_UART_MODE_REG	0x04		/* Mode Register. */
77 #define CDNC_UART_MODE_REG_CHMOD_R_LOOP	(3<<8)	/* [9:8] - channel mode */
78 #define CDNC_UART_MODE_REG_CHMOD_L_LOOP	(2<<8)
79 #define CDNC_UART_MODE_REG_CHMOD_AUTECHO (1<<8)
80 #define CDNC_UART_MODE_REG_STOP2	(2<<6)	/* [7:6] - stop bits */
81 #define CDNC_UART_MODE_REG_PAR_NONE	(4<<3)	/* [5:3] - parity type */
82 #define CDNC_UART_MODE_REG_PAR_MARK	(3<<3)
83 #define CDNC_UART_MODE_REG_PAR_SPACE	(2<<3)
84 #define CDNC_UART_MODE_REG_PAR_ODD	(1<<3)
85 #define CDNC_UART_MODE_REG_PAR_EVEN	(0<<3)
86 #define CDNC_UART_MODE_REG_6BIT		(3<<1)	/* [2:1] - character len */
87 #define CDNC_UART_MODE_REG_7BIT		(2<<1)
88 #define CDNC_UART_MODE_REG_8BIT		(0<<1)
89 #define CDNC_UART_MODE_REG_CLKSEL	(1<<0)
90 
91 #define CDNC_UART_IEN_REG	0x08		/* Interrupt registers. */
92 #define CDNC_UART_IDIS_REG	0x0C
93 #define CDNC_UART_IMASK_REG	0x10
94 #define CDNC_UART_ISTAT_REG	0x14
95 #define CDNC_UART_INT_TXOVR		(1<<12)
96 #define CDNC_UART_INT_TXNRLYFUL		(1<<11)	/* tx "nearly" full */
97 #define CDNC_UART_INT_TXTRIG		(1<<10)
98 #define CDNC_UART_INT_DMSI		(1<<9)	/* delta modem status */
99 #define CDNC_UART_INT_RXTMOUT		(1<<8)
100 #define CDNC_UART_INT_PARITY		(1<<7)
101 #define CDNC_UART_INT_FRAMING		(1<<6)
102 #define CDNC_UART_INT_RXOVR		(1<<5)
103 #define CDNC_UART_INT_TXFULL		(1<<4)
104 #define CDNC_UART_INT_TXEMPTY		(1<<3)
105 #define CDNC_UART_INT_RXFULL		(1<<2)
106 #define CDNC_UART_INT_RXEMPTY		(1<<1)
107 #define CDNC_UART_INT_RXTRIG		(1<<0)
108 #define CDNC_UART_INT_ALL		0x1FFF
109 
110 #define CDNC_UART_BAUDGEN_REG	0x18
111 #define CDNC_UART_RX_TIMEO_REG	0x1C
112 #define CDNC_UART_RX_WATER_REG	0x20
113 
114 #define CDNC_UART_MODEM_CTRL_REG 0x24
115 #define CDNC_UART_MODEM_CTRL_REG_FCM	(1<<5)	/* automatic flow control */
116 #define CDNC_UART_MODEM_CTRL_REG_RTS	(1<<1)
117 #define CDNC_UART_MODEM_CTRL_REG_DTR	(1<<0)
118 
119 #define CDNC_UART_MODEM_STAT_REG 0x28
120 #define CDNC_UART_MODEM_STAT_REG_FCMS	(1<<8)	/* flow control mode (rw) */
121 #define CDNC_UART_MODEM_STAT_REG_DCD	(1<<7)
122 #define CDNC_UART_MODEM_STAT_REG_RI	(1<<6)
123 #define CDNC_UART_MODEM_STAT_REG_DSR	(1<<5)
124 #define CDNC_UART_MODEM_STAT_REG_CTS	(1<<4)
125 #define CDNC_UART_MODEM_STAT_REG_DDCD	(1<<3)	/* change in DCD (w1tc) */
126 #define CDNC_UART_MODEM_STAT_REG_TERI	(1<<2)	/* trail edge ring (w1tc) */
127 #define CDNC_UART_MODEM_STAT_REG_DDSR	(1<<1)	/* change in DSR (w1tc) */
128 #define CDNC_UART_MODEM_STAT_REG_DCTS	(1<<0)	/* change in CTS (w1tc) */
129 
130 #define CDNC_UART_CHAN_STAT_REG	0x2C		/* Channel status register. */
131 #define CDNC_UART_CHAN_STAT_REG_TXNRLYFUL (1<<14) /* tx "nearly" full */
132 #define CDNC_UART_CHAN_STAT_REG_TXTRIG	(1<<13)
133 #define CDNC_UART_CHAN_STAT_REG_FDELT	(1<<12)
134 #define CDNC_UART_CHAN_STAT_REG_TXACTIVE (1<<11)
135 #define CDNC_UART_CHAN_STAT_REG_RXACTIVE (1<<10)
136 #define CDNC_UART_CHAN_STAT_REG_TXFULL	(1<<4)
137 #define CDNC_UART_CHAN_STAT_REG_TXEMPTY	(1<<3)
138 #define CDNC_UART_CHAN_STAT_REG_RXEMPTY	(1<<1)
139 #define CDNC_UART_CHAN_STAT_REG_RXTRIG	(1<<0)
140 
141 #define CDNC_UART_FIFO		0x30		/* Data FIFO (tx and rx) */
142 #define CDNC_UART_BAUDDIV_REG	0x34
143 #define CDNC_UART_FLOWDEL_REG	0x38
144 #define CDNC_UART_TX_WATER_REG	0x44
145 
146 
147 /*
148  * Low-level UART interface.
149  */
150 static int cdnc_uart_probe(struct uart_bas *bas);
151 static void cdnc_uart_init(struct uart_bas *bas, int, int, int, int);
152 static void cdnc_uart_term(struct uart_bas *bas);
153 static void cdnc_uart_putc(struct uart_bas *bas, int);
154 static int cdnc_uart_rxready(struct uart_bas *bas);
155 static int cdnc_uart_getc(struct uart_bas *bas, struct mtx *mtx);
156 
157 extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs;
158 
159 static struct uart_ops cdnc_uart_ops = {
160 	.probe = cdnc_uart_probe,
161 	.init = cdnc_uart_init,
162 	.term = cdnc_uart_term,
163 	.putc = cdnc_uart_putc,
164 	.rxready = cdnc_uart_rxready,
165 	.getc = cdnc_uart_getc,
166 };
167 
168 #define	SIGCHG(c, i, s, d)				\
169 	if (c) {					\
170 		i |= (i & s) ? s : s | d;		\
171 	} else {					\
172 		i = (i & s) ? (i & ~s) | d : i;		\
173 	}
174 
175 static int
176 cdnc_uart_probe(struct uart_bas *bas)
177 {
178 
179 	return (0);
180 }
181 
182 static int
183 cdnc_uart_set_baud(struct uart_bas *bas, int baudrate)
184 {
185 	uint32_t baudgen, bauddiv;
186 	uint32_t best_bauddiv, best_baudgen, best_error;
187 	uint32_t baud_out, err;
188 
189 	best_bauddiv = 0;
190 	best_baudgen = 0;
191 	best_error = ~0;
192 
193 	/* Try all possible bauddiv values and pick best match. */
194 	for (bauddiv = 4; bauddiv <= 255; bauddiv++) {
195 		baudgen = (bas->rclk + (baudrate * (bauddiv + 1)) / 2) /
196 			(baudrate * (bauddiv + 1));
197 		if (baudgen < 1 || baudgen > 0xffff)
198 			continue;
199 
200 		baud_out = bas->rclk / (baudgen * (bauddiv + 1));
201 		err = baud_out > baudrate ?
202 			baud_out - baudrate : baudrate - baud_out;
203 
204 		if (err < best_error) {
205 			best_error = err;
206 			best_bauddiv = bauddiv;
207 			best_baudgen = baudgen;
208 		}
209 	}
210 
211 	if (best_bauddiv > 0) {
212 		WR4(bas, CDNC_UART_BAUDDIV_REG, best_bauddiv);
213 		WR4(bas, CDNC_UART_BAUDGEN_REG, best_baudgen);
214 		return (0);
215 	} else
216 		return (-1); /* out of range */
217 }
218 
219 static int
220 cdnc_uart_set_params(struct uart_bas *bas, int baudrate, int databits,
221 		      int stopbits, int parity)
222 {
223 	uint32_t mode_reg_value = 0;
224 
225 	switch (databits) {
226 	case 6:
227 		mode_reg_value |= CDNC_UART_MODE_REG_6BIT;
228 		break;
229 	case 7:
230 		mode_reg_value |= CDNC_UART_MODE_REG_7BIT;
231 		break;
232 	case 8:
233 	default:
234 		mode_reg_value |= CDNC_UART_MODE_REG_8BIT;
235 		break;
236 	}
237 
238 	if (stopbits == 2)
239 		mode_reg_value |= CDNC_UART_MODE_REG_STOP2;
240 
241 	switch (parity) {
242 	case UART_PARITY_MARK:
243 		mode_reg_value |= CDNC_UART_MODE_REG_PAR_MARK;
244 		break;
245 	case UART_PARITY_SPACE:
246 		mode_reg_value |= CDNC_UART_MODE_REG_PAR_SPACE;
247 		break;
248 	case UART_PARITY_ODD:
249 		mode_reg_value |= CDNC_UART_MODE_REG_PAR_ODD;
250 		break;
251 	case UART_PARITY_EVEN:
252 		mode_reg_value |= CDNC_UART_MODE_REG_PAR_EVEN;
253 		break;
254 	case UART_PARITY_NONE:
255 	default:
256 		mode_reg_value |= CDNC_UART_MODE_REG_PAR_NONE;
257 		break;
258 	}
259 
260 	WR4(bas, CDNC_UART_MODE_REG, mode_reg_value);
261 
262 	if (baudrate > 0 && cdnc_uart_set_baud(bas, baudrate) < 0)
263 		return (EINVAL);
264 
265 	return(0);
266 }
267 
268 static void
269 cdnc_uart_hw_init(struct uart_bas *bas)
270 {
271 
272 	/* Reset RX and TX. */
273 	WR4(bas, CDNC_UART_CTRL_REG,
274 	    CDNC_UART_CTRL_REG_RXRST | CDNC_UART_CTRL_REG_TXRST);
275 
276 	/* Interrupts all off. */
277 	WR4(bas, CDNC_UART_IDIS_REG, CDNC_UART_INT_ALL);
278 	WR4(bas, CDNC_UART_ISTAT_REG, CDNC_UART_INT_ALL);
279 
280 	/* Clear delta bits. */
281 	WR4(bas, CDNC_UART_MODEM_STAT_REG,
282 	    CDNC_UART_MODEM_STAT_REG_DDCD | CDNC_UART_MODEM_STAT_REG_TERI |
283 	    CDNC_UART_MODEM_STAT_REG_DDSR | CDNC_UART_MODEM_STAT_REG_DCTS);
284 
285 	/* RX FIFO water level, stale timeout */
286 	WR4(bas, CDNC_UART_RX_WATER_REG, UART_FIFO_SIZE/2);
287 	WR4(bas, CDNC_UART_RX_TIMEO_REG, 10);
288 
289 	/* TX FIFO water level (not used.) */
290 	WR4(bas, CDNC_UART_TX_WATER_REG, UART_FIFO_SIZE/2);
291 
292 	/* Bring RX and TX online. */
293 	WR4(bas, CDNC_UART_CTRL_REG,
294 	    CDNC_UART_CTRL_REG_RX_EN | CDNC_UART_CTRL_REG_TX_EN |
295 	    CDNC_UART_CTRL_REG_TORST | CDNC_UART_CTRL_REG_STOPBRK);
296 
297 	/* Set DTR and RTS. */
298 	WR4(bas, CDNC_UART_MODEM_CTRL_REG, CDNC_UART_MODEM_CTRL_REG_DTR |
299 	    CDNC_UART_MODEM_CTRL_REG_RTS);
300 }
301 
302 /*
303  * Initialize this device for use as a console.
304  */
305 static void
306 cdnc_uart_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
307 	      int parity)
308 {
309 
310 	/* Initialize hardware. */
311 	cdnc_uart_hw_init(bas);
312 
313 	/* Set baudrate, parameters. */
314 	(void)cdnc_uart_set_params(bas, baudrate, databits, stopbits, parity);
315 }
316 
317 /*
318  * Free resources now that we're no longer the console.  This appears to
319  * be never called, and I'm unsure quite what to do if I am called.
320  */
321 static void
322 cdnc_uart_term(struct uart_bas *bas)
323 {
324 
325 	/* XXX */
326 }
327 
328 /*
329  * Put a character of console output (so we do it here polling rather than
330  * interrutp driven).
331  */
332 static void
333 cdnc_uart_putc(struct uart_bas *bas, int c)
334 {
335 
336 	/* Wait for room. */
337 	while ((RD4(bas,CDNC_UART_CHAN_STAT_REG) &
338 		CDNC_UART_CHAN_STAT_REG_TXFULL) != 0)
339 		;
340 
341 	WR4(bas, CDNC_UART_FIFO, c);
342 
343 	while ((RD4(bas,CDNC_UART_CHAN_STAT_REG) &
344 		CDNC_UART_CHAN_STAT_REG_TXEMPTY) == 0)
345 		;
346 }
347 
348 /*
349  * Check for a character available.
350  */
351 static int
352 cdnc_uart_rxready(struct uart_bas *bas)
353 {
354 
355 	return ((RD4(bas, CDNC_UART_CHAN_STAT_REG) &
356 		 CDNC_UART_CHAN_STAT_REG_RXEMPTY) == 0);
357 }
358 
359 /*
360  * Block waiting for a character.
361  */
362 static int
363 cdnc_uart_getc(struct uart_bas *bas, struct mtx *mtx)
364 {
365 	int c;
366 
367 	uart_lock(mtx);
368 
369 	while ((RD4(bas, CDNC_UART_CHAN_STAT_REG) &
370 		CDNC_UART_CHAN_STAT_REG_RXEMPTY) != 0) {
371 		uart_unlock(mtx);
372 		DELAY(4);
373 		uart_lock(mtx);
374 	}
375 
376 	c = RD4(bas, CDNC_UART_FIFO);
377 
378 	uart_unlock(mtx);
379 
380 	c &= 0xff;
381 	return (c);
382 }
383 
384 /*****************************************************************************/
385 /*
386  * High-level UART interface.
387  */
388 
389 static int cdnc_uart_bus_probe(struct uart_softc *sc);
390 static int cdnc_uart_bus_attach(struct uart_softc *sc);
391 static int cdnc_uart_bus_flush(struct uart_softc *, int);
392 static int cdnc_uart_bus_getsig(struct uart_softc *);
393 static int cdnc_uart_bus_ioctl(struct uart_softc *, int, intptr_t);
394 static int cdnc_uart_bus_ipend(struct uart_softc *);
395 static int cdnc_uart_bus_param(struct uart_softc *, int, int, int, int);
396 static int cdnc_uart_bus_receive(struct uart_softc *);
397 static int cdnc_uart_bus_setsig(struct uart_softc *, int);
398 static int cdnc_uart_bus_transmit(struct uart_softc *);
399 static void cdnc_uart_bus_grab(struct uart_softc *);
400 static void cdnc_uart_bus_ungrab(struct uart_softc *);
401 
402 static kobj_method_t cdnc_uart_bus_methods[] = {
403 	KOBJMETHOD(uart_probe,		cdnc_uart_bus_probe),
404 	KOBJMETHOD(uart_attach, 	cdnc_uart_bus_attach),
405 	KOBJMETHOD(uart_flush,		cdnc_uart_bus_flush),
406 	KOBJMETHOD(uart_getsig,		cdnc_uart_bus_getsig),
407 	KOBJMETHOD(uart_ioctl,		cdnc_uart_bus_ioctl),
408 	KOBJMETHOD(uart_ipend,		cdnc_uart_bus_ipend),
409 	KOBJMETHOD(uart_param,		cdnc_uart_bus_param),
410 	KOBJMETHOD(uart_receive,	cdnc_uart_bus_receive),
411 	KOBJMETHOD(uart_setsig,		cdnc_uart_bus_setsig),
412 	KOBJMETHOD(uart_transmit,	cdnc_uart_bus_transmit),
413 	KOBJMETHOD(uart_grab,		cdnc_uart_bus_grab),
414 	KOBJMETHOD(uart_ungrab,		cdnc_uart_bus_ungrab),
415 
416 	KOBJMETHOD_END
417 };
418 
419 int
420 cdnc_uart_bus_probe(struct uart_softc *sc)
421 {
422 
423 	sc->sc_txfifosz = UART_FIFO_SIZE;
424 	sc->sc_rxfifosz = UART_FIFO_SIZE;
425 	sc->sc_hwiflow = 0;
426 	sc->sc_hwoflow = 0;
427 
428 	device_set_desc(sc->sc_dev, "Cadence UART");
429 
430 	return (0);
431 }
432 
433 static int
434 cdnc_uart_bus_attach(struct uart_softc *sc)
435 {
436 	struct uart_bas *bas = &sc->sc_bas;
437 	struct uart_devinfo *di;
438 
439 	if (sc->sc_sysdev != NULL) {
440 		di = sc->sc_sysdev;
441 		(void)cdnc_uart_set_params(bas, di->baudrate, di->databits,
442 					   di->stopbits, di->parity);
443 	} else
444 		cdnc_uart_hw_init(bas);
445 
446 	(void)cdnc_uart_bus_getsig(sc);
447 
448 	/* Enable interrupts. */
449 	WR4(bas, CDNC_UART_IEN_REG,
450 	    CDNC_UART_INT_RXTRIG | CDNC_UART_INT_RXTMOUT |
451 	    CDNC_UART_INT_TXOVR | CDNC_UART_INT_RXOVR |
452 	    CDNC_UART_INT_DMSI);
453 
454 	return (0);
455 }
456 
457 static int
458 cdnc_uart_bus_transmit(struct uart_softc *sc)
459 {
460 	int i;
461 	struct uart_bas *bas = &sc->sc_bas;
462 
463 	uart_lock(sc->sc_hwmtx);
464 
465 	/* Clear sticky TXEMPTY status bit. */
466 	WR4(bas, CDNC_UART_ISTAT_REG, CDNC_UART_INT_TXEMPTY);
467 
468 	for (i = 0; i < sc->sc_txdatasz; i++)
469 		WR4(bas, CDNC_UART_FIFO, sc->sc_txbuf[i]);
470 
471 	/* Enable TX empty interrupt. */
472 	WR4(bas, CDNC_UART_IEN_REG, CDNC_UART_INT_TXEMPTY);
473 	sc->sc_txbusy = 1;
474 
475 	uart_unlock(sc->sc_hwmtx);
476 
477 	return (0);
478 }
479 
480 static int
481 cdnc_uart_bus_setsig(struct uart_softc *sc, int sig)
482 {
483 	struct uart_bas *bas = &sc->sc_bas;
484 	uint32_t new, old, modem_ctrl;
485 
486 	do {
487 		old = sc->sc_hwsig;
488 		new = old;
489 		if (sig & SER_DDTR) {
490 			SIGCHG(sig & SER_DTR, new, SER_DTR, SER_DDTR);
491 		}
492 		if (sig & SER_DRTS) {
493 			SIGCHG(sig & SER_RTS, new, SER_RTS, SER_DRTS);
494 		}
495 	} while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
496 	uart_lock(sc->sc_hwmtx);
497 	modem_ctrl = RD4(bas, CDNC_UART_MODEM_CTRL_REG) &
498 		~(CDNC_UART_MODEM_CTRL_REG_DTR | CDNC_UART_MODEM_CTRL_REG_RTS);
499 	if ((new & SER_DTR) != 0)
500 		modem_ctrl |= CDNC_UART_MODEM_CTRL_REG_DTR;
501 	if ((new & SER_RTS) != 0)
502 		modem_ctrl |= CDNC_UART_MODEM_CTRL_REG_RTS;
503 	WR4(bas, CDNC_UART_MODEM_CTRL_REG, modem_ctrl);
504 
505 	uart_unlock(sc->sc_hwmtx);
506 	return (0);
507 }
508 
509 static int
510 cdnc_uart_bus_receive(struct uart_softc *sc)
511 {
512 	struct uart_bas *bas = &sc->sc_bas;
513 	uint32_t status;
514 	int c, c_status = 0;
515 
516 	uart_lock(sc->sc_hwmtx);
517 
518 	/* Check for parity or framing errors and clear the status bits. */
519 	status = RD4(bas, CDNC_UART_ISTAT_REG);
520 	if ((status & (CDNC_UART_INT_FRAMING | CDNC_UART_INT_PARITY)) != 0) {
521 		WR4(bas, CDNC_UART_ISTAT_REG,
522 		    status & (CDNC_UART_INT_FRAMING | CDNC_UART_INT_PARITY));
523 		if ((status & CDNC_UART_INT_PARITY) != 0)
524 			c_status |= UART_STAT_PARERR;
525 		if ((status & CDNC_UART_INT_FRAMING) != 0)
526 			c_status |= UART_STAT_FRAMERR;
527 	}
528 
529 	while ((RD4(bas, CDNC_UART_CHAN_STAT_REG) &
530 		CDNC_UART_CHAN_STAT_REG_RXEMPTY) == 0) {
531 		c = RD4(bas, CDNC_UART_FIFO) & 0xff;
532 #ifdef KDB
533 		/* Detect break and drop into debugger. */
534 		if (c == 0 && (c_status & UART_STAT_FRAMERR) != 0 &&
535 		    sc->sc_sysdev != NULL &&
536 		    sc->sc_sysdev->type == UART_DEV_CONSOLE) {
537 			kdb_break();
538 			WR4(bas, CDNC_UART_ISTAT_REG, CDNC_UART_INT_FRAMING);
539 		}
540 #endif
541 		uart_rx_put(sc, c | c_status);
542 	}
543 
544 	uart_unlock(sc->sc_hwmtx);
545 
546 	return (0);
547 }
548 
549 static int
550 cdnc_uart_bus_param(struct uart_softc *sc, int baudrate, int databits,
551 		   int stopbits, int parity)
552 {
553 
554 	return (cdnc_uart_set_params(&sc->sc_bas, baudrate,
555 				    databits, stopbits, parity));
556 }
557 
558 static int
559 cdnc_uart_bus_ipend(struct uart_softc *sc)
560 {
561 	int ipend = 0;
562 	struct uart_bas *bas = &sc->sc_bas;
563 	uint32_t istatus;
564 
565 	uart_lock(sc->sc_hwmtx);
566 
567 	istatus = RD4(bas, CDNC_UART_ISTAT_REG);
568 
569 	/* Clear interrupt bits. */
570 	WR4(bas, CDNC_UART_ISTAT_REG, istatus &
571 	    (CDNC_UART_INT_RXTRIG | CDNC_UART_INT_RXTMOUT |
572 	     CDNC_UART_INT_TXOVR | CDNC_UART_INT_RXOVR |
573 	     CDNC_UART_INT_TXEMPTY | CDNC_UART_INT_DMSI));
574 
575 	/* Receive data. */
576 	if ((istatus & (CDNC_UART_INT_RXTRIG | CDNC_UART_INT_RXTMOUT)) != 0)
577 		ipend |= SER_INT_RXREADY;
578 
579 	/* Transmit fifo empty. */
580 	if (sc->sc_txbusy && (istatus & CDNC_UART_INT_TXEMPTY) != 0) {
581 		/* disable txempty interrupt. */
582 		WR4(bas, CDNC_UART_IDIS_REG, CDNC_UART_INT_TXEMPTY);
583 		ipend |= SER_INT_TXIDLE;
584 	}
585 
586 	/* TX Overflow. */
587 	if ((istatus & CDNC_UART_INT_TXOVR) != 0)
588 		ipend |= SER_INT_OVERRUN;
589 
590 	/* RX Overflow. */
591 	if ((istatus & CDNC_UART_INT_RXOVR) != 0)
592 		ipend |= SER_INT_OVERRUN;
593 
594 	/* Modem signal change. */
595 	if ((istatus & CDNC_UART_INT_DMSI) != 0) {
596 		WR4(bas, CDNC_UART_MODEM_STAT_REG,
597 		    CDNC_UART_MODEM_STAT_REG_DDCD |
598 		    CDNC_UART_MODEM_STAT_REG_TERI |
599 		    CDNC_UART_MODEM_STAT_REG_DDSR |
600 		    CDNC_UART_MODEM_STAT_REG_DCTS);
601 		ipend |= SER_INT_SIGCHG;
602 	}
603 
604 	uart_unlock(sc->sc_hwmtx);
605 	return (ipend);
606 }
607 
608 static int
609 cdnc_uart_bus_flush(struct uart_softc *sc, int what)
610 {
611 
612 	return (0);
613 }
614 
615 static int
616 cdnc_uart_bus_getsig(struct uart_softc *sc)
617 {
618 	struct uart_bas *bas = &sc->sc_bas;
619 	uint32_t new, old, sig;
620 	uint8_t modem_status;
621 
622 	do {
623 		old = sc->sc_hwsig;
624 		sig = old;
625 		uart_lock(sc->sc_hwmtx);
626 		modem_status = RD4(bas, CDNC_UART_MODEM_STAT_REG);
627 		uart_unlock(sc->sc_hwmtx);
628 		SIGCHG(modem_status & CDNC_UART_MODEM_STAT_REG_DSR,
629 		       sig, SER_DSR, SER_DDSR);
630 		SIGCHG(modem_status & CDNC_UART_MODEM_STAT_REG_CTS,
631 		       sig, SER_CTS, SER_DCTS);
632 		SIGCHG(modem_status & CDNC_UART_MODEM_STAT_REG_DCD,
633 		       sig, SER_DCD, SER_DDCD);
634 		SIGCHG(modem_status & CDNC_UART_MODEM_STAT_REG_RI,
635 		       sig, SER_RI,  SER_DRI);
636 		new = sig & ~SER_MASK_DELTA;
637 	} while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
638 	return (sig);
639 }
640 
641 static int
642 cdnc_uart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
643 {
644 	struct uart_bas *bas = &sc->sc_bas;
645 	uint32_t uart_ctrl, modem_ctrl;
646 	int error = 0;
647 
648 	uart_lock(sc->sc_hwmtx);
649 
650 	switch (request) {
651 	case UART_IOCTL_BREAK:
652 		uart_ctrl = RD4(bas, CDNC_UART_CTRL_REG);
653 		if (data) {
654 			uart_ctrl |= CDNC_UART_CTRL_REG_STARTBRK;
655 			uart_ctrl &= ~CDNC_UART_CTRL_REG_STOPBRK;
656 		} else {
657 			uart_ctrl |= CDNC_UART_CTRL_REG_STOPBRK;
658 			uart_ctrl &= ~CDNC_UART_CTRL_REG_STARTBRK;
659 		}
660 		WR4(bas, CDNC_UART_CTRL_REG, uart_ctrl);
661 		break;
662 	case UART_IOCTL_IFLOW:
663 		modem_ctrl = RD4(bas, CDNC_UART_MODEM_CTRL_REG);
664 		if (data)
665 			modem_ctrl |= CDNC_UART_MODEM_CTRL_REG_RTS;
666 		else
667 			modem_ctrl &= ~CDNC_UART_MODEM_CTRL_REG_RTS;
668 		WR4(bas, CDNC_UART_MODEM_CTRL_REG, modem_ctrl);
669 		break;
670 	default:
671 		error = EINVAL;
672 		break;
673 	}
674 
675 	uart_unlock(sc->sc_hwmtx);
676 
677 	return (error);
678 }
679 
680 static void
681 cdnc_uart_bus_grab(struct uart_softc *sc)
682 {
683 
684 	/* Enable interrupts. */
685 	WR4(&sc->sc_bas, CDNC_UART_IEN_REG,
686 	    CDNC_UART_INT_TXOVR | CDNC_UART_INT_RXOVR |
687 	    CDNC_UART_INT_DMSI);
688 }
689 
690 static void
691 cdnc_uart_bus_ungrab(struct uart_softc *sc)
692 {
693 
694 	/* Enable interrupts. */
695 	WR4(&sc->sc_bas, CDNC_UART_IEN_REG,
696 	    CDNC_UART_INT_RXTRIG | CDNC_UART_INT_RXTMOUT |
697 	    CDNC_UART_INT_TXOVR | CDNC_UART_INT_RXOVR |
698 	    CDNC_UART_INT_DMSI);
699 }
700 
701 struct uart_class uart_cdnc_class = {
702 	"cdnc_uart",
703 	cdnc_uart_bus_methods,
704 	sizeof(struct uart_softc),
705 	.uc_ops = &cdnc_uart_ops,
706 	.uc_range = 8
707 };
708