1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2005 Olivier Houchard All rights reserved. 5 * Copyright (c) 2012 Thomas Skibo All rights reserved. 6 * Copyright (c) 2005 M. Warner Losh <imp@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* A driver for the Cadence AMBA UART as used by the Xilinx Zynq-7000. 32 * 33 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual. 34 * (v1.4) November 16, 2012. Xilinx doc UG585. UART is covered in Ch. 19 35 * and register definitions are in appendix B.33. 36 */ 37 38 #include <sys/cdefs.h> 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/bus.h> 42 #include <sys/conf.h> 43 #include <sys/cons.h> 44 #include <machine/bus.h> 45 46 #include <dev/uart/uart.h> 47 #include <dev/uart/uart_cpu.h> 48 #include <dev/uart/uart_cpu_fdt.h> 49 #include <dev/uart/uart_bus.h> 50 51 #include "uart_if.h" 52 53 #define UART_FIFO_SIZE 64 54 55 #define RD4(bas, reg) \ 56 bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs((bas), (reg))) 57 #define WR4(bas, reg, value) \ 58 bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs((bas), (reg)), \ 59 (value)) 60 61 /* Register definitions for Cadence UART Controller. 62 */ 63 #define CDNC_UART_CTRL_REG 0x00 /* Control Register. */ 64 #define CDNC_UART_CTRL_REG_STOPBRK (1<<8) 65 #define CDNC_UART_CTRL_REG_STARTBRK (1<<7) 66 #define CDNC_UART_CTRL_REG_TORST (1<<6) 67 #define CDNC_UART_CTRL_REG_TX_DIS (1<<5) 68 #define CDNC_UART_CTRL_REG_TX_EN (1<<4) 69 #define CDNC_UART_CTRL_REG_RX_DIS (1<<3) 70 #define CDNC_UART_CTRL_REG_RX_EN (1<<2) 71 #define CDNC_UART_CTRL_REG_TXRST (1<<1) 72 #define CDNC_UART_CTRL_REG_RXRST (1<<0) 73 74 #define CDNC_UART_MODE_REG 0x04 /* Mode Register. */ 75 #define CDNC_UART_MODE_REG_CHMOD_R_LOOP (3<<8) /* [9:8] - channel mode */ 76 #define CDNC_UART_MODE_REG_CHMOD_L_LOOP (2<<8) 77 #define CDNC_UART_MODE_REG_CHMOD_AUTECHO (1<<8) 78 #define CDNC_UART_MODE_REG_STOP2 (2<<6) /* [7:6] - stop bits */ 79 #define CDNC_UART_MODE_REG_PAR_NONE (4<<3) /* [5:3] - parity type */ 80 #define CDNC_UART_MODE_REG_PAR_MARK (3<<3) 81 #define CDNC_UART_MODE_REG_PAR_SPACE (2<<3) 82 #define CDNC_UART_MODE_REG_PAR_ODD (1<<3) 83 #define CDNC_UART_MODE_REG_PAR_EVEN (0<<3) 84 #define CDNC_UART_MODE_REG_6BIT (3<<1) /* [2:1] - character len */ 85 #define CDNC_UART_MODE_REG_7BIT (2<<1) 86 #define CDNC_UART_MODE_REG_8BIT (0<<1) 87 #define CDNC_UART_MODE_REG_CLKSEL (1<<0) 88 89 #define CDNC_UART_IEN_REG 0x08 /* Interrupt registers. */ 90 #define CDNC_UART_IDIS_REG 0x0C 91 #define CDNC_UART_IMASK_REG 0x10 92 #define CDNC_UART_ISTAT_REG 0x14 93 #define CDNC_UART_INT_TXOVR (1<<12) 94 #define CDNC_UART_INT_TXNRLYFUL (1<<11) /* tx "nearly" full */ 95 #define CDNC_UART_INT_TXTRIG (1<<10) 96 #define CDNC_UART_INT_DMSI (1<<9) /* delta modem status */ 97 #define CDNC_UART_INT_RXTMOUT (1<<8) 98 #define CDNC_UART_INT_PARITY (1<<7) 99 #define CDNC_UART_INT_FRAMING (1<<6) 100 #define CDNC_UART_INT_RXOVR (1<<5) 101 #define CDNC_UART_INT_TXFULL (1<<4) 102 #define CDNC_UART_INT_TXEMPTY (1<<3) 103 #define CDNC_UART_INT_RXFULL (1<<2) 104 #define CDNC_UART_INT_RXEMPTY (1<<1) 105 #define CDNC_UART_INT_RXTRIG (1<<0) 106 #define CDNC_UART_INT_ALL 0x1FFF 107 108 #define CDNC_UART_BAUDGEN_REG 0x18 109 #define CDNC_UART_RX_TIMEO_REG 0x1C 110 #define CDNC_UART_RX_WATER_REG 0x20 111 112 #define CDNC_UART_MODEM_CTRL_REG 0x24 113 #define CDNC_UART_MODEM_CTRL_REG_FCM (1<<5) /* automatic flow control */ 114 #define CDNC_UART_MODEM_CTRL_REG_RTS (1<<1) 115 #define CDNC_UART_MODEM_CTRL_REG_DTR (1<<0) 116 117 #define CDNC_UART_MODEM_STAT_REG 0x28 118 #define CDNC_UART_MODEM_STAT_REG_FCMS (1<<8) /* flow control mode (rw) */ 119 #define CDNC_UART_MODEM_STAT_REG_DCD (1<<7) 120 #define CDNC_UART_MODEM_STAT_REG_RI (1<<6) 121 #define CDNC_UART_MODEM_STAT_REG_DSR (1<<5) 122 #define CDNC_UART_MODEM_STAT_REG_CTS (1<<4) 123 #define CDNC_UART_MODEM_STAT_REG_DDCD (1<<3) /* change in DCD (w1tc) */ 124 #define CDNC_UART_MODEM_STAT_REG_TERI (1<<2) /* trail edge ring (w1tc) */ 125 #define CDNC_UART_MODEM_STAT_REG_DDSR (1<<1) /* change in DSR (w1tc) */ 126 #define CDNC_UART_MODEM_STAT_REG_DCTS (1<<0) /* change in CTS (w1tc) */ 127 128 #define CDNC_UART_CHAN_STAT_REG 0x2C /* Channel status register. */ 129 #define CDNC_UART_CHAN_STAT_REG_TXNRLYFUL (1<<14) /* tx "nearly" full */ 130 #define CDNC_UART_CHAN_STAT_REG_TXTRIG (1<<13) 131 #define CDNC_UART_CHAN_STAT_REG_FDELT (1<<12) 132 #define CDNC_UART_CHAN_STAT_REG_TXACTIVE (1<<11) 133 #define CDNC_UART_CHAN_STAT_REG_RXACTIVE (1<<10) 134 #define CDNC_UART_CHAN_STAT_REG_TXFULL (1<<4) 135 #define CDNC_UART_CHAN_STAT_REG_TXEMPTY (1<<3) 136 #define CDNC_UART_CHAN_STAT_REG_RXEMPTY (1<<1) 137 #define CDNC_UART_CHAN_STAT_REG_RXTRIG (1<<0) 138 139 #define CDNC_UART_FIFO 0x30 /* Data FIFO (tx and rx) */ 140 #define CDNC_UART_BAUDDIV_REG 0x34 141 #define CDNC_UART_FLOWDEL_REG 0x38 142 #define CDNC_UART_TX_WATER_REG 0x44 143 144 /* 145 * Low-level UART interface. 146 */ 147 static int cdnc_uart_probe(struct uart_bas *bas); 148 static void cdnc_uart_init(struct uart_bas *bas, int, int, int, int); 149 static void cdnc_uart_term(struct uart_bas *bas); 150 static void cdnc_uart_putc(struct uart_bas *bas, int); 151 static int cdnc_uart_rxready(struct uart_bas *bas); 152 static int cdnc_uart_getc(struct uart_bas *bas, struct mtx *mtx); 153 154 extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs; 155 156 static struct uart_ops cdnc_uart_ops = { 157 .probe = cdnc_uart_probe, 158 .init = cdnc_uart_init, 159 .term = cdnc_uart_term, 160 .putc = cdnc_uart_putc, 161 .rxready = cdnc_uart_rxready, 162 .getc = cdnc_uart_getc, 163 }; 164 165 #define SIGCHG(c, i, s, d) \ 166 if (c) { \ 167 i |= (i & s) ? s : s | d; \ 168 } else { \ 169 i = (i & s) ? (i & ~s) | d : i; \ 170 } 171 172 static int 173 cdnc_uart_probe(struct uart_bas *bas) 174 { 175 176 return (0); 177 } 178 179 static int 180 cdnc_uart_set_baud(struct uart_bas *bas, int baudrate) 181 { 182 uint32_t baudgen, bauddiv; 183 uint32_t best_bauddiv, best_baudgen, best_error; 184 uint32_t baud_out, err; 185 186 best_bauddiv = 0; 187 best_baudgen = 0; 188 best_error = ~0; 189 190 /* Try all possible bauddiv values and pick best match. */ 191 for (bauddiv = 4; bauddiv <= 255; bauddiv++) { 192 baudgen = (bas->rclk + (baudrate * (bauddiv + 1)) / 2) / 193 (baudrate * (bauddiv + 1)); 194 if (baudgen < 1 || baudgen > 0xffff) 195 continue; 196 197 baud_out = bas->rclk / (baudgen * (bauddiv + 1)); 198 err = baud_out > baudrate ? 199 baud_out - baudrate : baudrate - baud_out; 200 201 if (err < best_error) { 202 best_error = err; 203 best_bauddiv = bauddiv; 204 best_baudgen = baudgen; 205 } 206 } 207 208 if (best_bauddiv > 0) { 209 WR4(bas, CDNC_UART_BAUDDIV_REG, best_bauddiv); 210 WR4(bas, CDNC_UART_BAUDGEN_REG, best_baudgen); 211 return (0); 212 } else 213 return (-1); /* out of range */ 214 } 215 216 static int 217 cdnc_uart_set_params(struct uart_bas *bas, int baudrate, int databits, 218 int stopbits, int parity) 219 { 220 uint32_t mode_reg_value = 0; 221 222 switch (databits) { 223 case 6: 224 mode_reg_value |= CDNC_UART_MODE_REG_6BIT; 225 break; 226 case 7: 227 mode_reg_value |= CDNC_UART_MODE_REG_7BIT; 228 break; 229 case 8: 230 default: 231 mode_reg_value |= CDNC_UART_MODE_REG_8BIT; 232 break; 233 } 234 235 if (stopbits == 2) 236 mode_reg_value |= CDNC_UART_MODE_REG_STOP2; 237 238 switch (parity) { 239 case UART_PARITY_MARK: 240 mode_reg_value |= CDNC_UART_MODE_REG_PAR_MARK; 241 break; 242 case UART_PARITY_SPACE: 243 mode_reg_value |= CDNC_UART_MODE_REG_PAR_SPACE; 244 break; 245 case UART_PARITY_ODD: 246 mode_reg_value |= CDNC_UART_MODE_REG_PAR_ODD; 247 break; 248 case UART_PARITY_EVEN: 249 mode_reg_value |= CDNC_UART_MODE_REG_PAR_EVEN; 250 break; 251 case UART_PARITY_NONE: 252 default: 253 mode_reg_value |= CDNC_UART_MODE_REG_PAR_NONE; 254 break; 255 } 256 257 WR4(bas, CDNC_UART_MODE_REG, mode_reg_value); 258 259 if (baudrate > 0 && cdnc_uart_set_baud(bas, baudrate) < 0) 260 return (EINVAL); 261 262 return(0); 263 } 264 265 static void 266 cdnc_uart_hw_init(struct uart_bas *bas) 267 { 268 269 /* Reset RX and TX. */ 270 WR4(bas, CDNC_UART_CTRL_REG, 271 CDNC_UART_CTRL_REG_RXRST | CDNC_UART_CTRL_REG_TXRST); 272 273 /* Interrupts all off. */ 274 WR4(bas, CDNC_UART_IDIS_REG, CDNC_UART_INT_ALL); 275 WR4(bas, CDNC_UART_ISTAT_REG, CDNC_UART_INT_ALL); 276 277 /* Clear delta bits. */ 278 WR4(bas, CDNC_UART_MODEM_STAT_REG, 279 CDNC_UART_MODEM_STAT_REG_DDCD | CDNC_UART_MODEM_STAT_REG_TERI | 280 CDNC_UART_MODEM_STAT_REG_DDSR | CDNC_UART_MODEM_STAT_REG_DCTS); 281 282 /* RX FIFO water level, stale timeout */ 283 WR4(bas, CDNC_UART_RX_WATER_REG, UART_FIFO_SIZE/2); 284 WR4(bas, CDNC_UART_RX_TIMEO_REG, 10); 285 286 /* TX FIFO water level (not used.) */ 287 WR4(bas, CDNC_UART_TX_WATER_REG, UART_FIFO_SIZE/2); 288 289 /* Bring RX and TX online. */ 290 WR4(bas, CDNC_UART_CTRL_REG, 291 CDNC_UART_CTRL_REG_RX_EN | CDNC_UART_CTRL_REG_TX_EN | 292 CDNC_UART_CTRL_REG_TORST | CDNC_UART_CTRL_REG_STOPBRK); 293 294 /* Set DTR and RTS. */ 295 WR4(bas, CDNC_UART_MODEM_CTRL_REG, CDNC_UART_MODEM_CTRL_REG_DTR | 296 CDNC_UART_MODEM_CTRL_REG_RTS); 297 } 298 299 /* 300 * Initialize this device for use as a console. 301 */ 302 static void 303 cdnc_uart_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 304 int parity) 305 { 306 307 /* Initialize hardware. */ 308 cdnc_uart_hw_init(bas); 309 310 /* Set baudrate, parameters. */ 311 (void)cdnc_uart_set_params(bas, baudrate, databits, stopbits, parity); 312 } 313 314 /* 315 * Free resources now that we're no longer the console. This appears to 316 * be never called, and I'm unsure quite what to do if I am called. 317 */ 318 static void 319 cdnc_uart_term(struct uart_bas *bas) 320 { 321 322 /* XXX */ 323 } 324 325 /* 326 * Put a character of console output (so we do it here polling rather than 327 * interrupt driven). 328 */ 329 static void 330 cdnc_uart_putc(struct uart_bas *bas, int c) 331 { 332 333 /* Wait for room. */ 334 while ((RD4(bas,CDNC_UART_CHAN_STAT_REG) & 335 CDNC_UART_CHAN_STAT_REG_TXFULL) != 0) 336 ; 337 338 WR4(bas, CDNC_UART_FIFO, c); 339 340 while ((RD4(bas,CDNC_UART_CHAN_STAT_REG) & 341 CDNC_UART_CHAN_STAT_REG_TXEMPTY) == 0) 342 ; 343 } 344 345 /* 346 * Check for a character available. 347 */ 348 static int 349 cdnc_uart_rxready(struct uart_bas *bas) 350 { 351 352 return ((RD4(bas, CDNC_UART_CHAN_STAT_REG) & 353 CDNC_UART_CHAN_STAT_REG_RXEMPTY) == 0); 354 } 355 356 /* 357 * Block waiting for a character. 358 */ 359 static int 360 cdnc_uart_getc(struct uart_bas *bas, struct mtx *mtx) 361 { 362 int c; 363 364 uart_lock(mtx); 365 366 while ((RD4(bas, CDNC_UART_CHAN_STAT_REG) & 367 CDNC_UART_CHAN_STAT_REG_RXEMPTY) != 0) { 368 uart_unlock(mtx); 369 DELAY(4); 370 uart_lock(mtx); 371 } 372 373 c = RD4(bas, CDNC_UART_FIFO); 374 375 uart_unlock(mtx); 376 377 c &= 0xff; 378 return (c); 379 } 380 381 /*****************************************************************************/ 382 /* 383 * High-level UART interface. 384 */ 385 386 static int cdnc_uart_bus_probe(struct uart_softc *sc); 387 static int cdnc_uart_bus_attach(struct uart_softc *sc); 388 static int cdnc_uart_bus_flush(struct uart_softc *, int); 389 static int cdnc_uart_bus_getsig(struct uart_softc *); 390 static int cdnc_uart_bus_ioctl(struct uart_softc *, int, intptr_t); 391 static int cdnc_uart_bus_ipend(struct uart_softc *); 392 static int cdnc_uart_bus_param(struct uart_softc *, int, int, int, int); 393 static int cdnc_uart_bus_receive(struct uart_softc *); 394 static int cdnc_uart_bus_setsig(struct uart_softc *, int); 395 static int cdnc_uart_bus_transmit(struct uart_softc *); 396 static void cdnc_uart_bus_grab(struct uart_softc *); 397 static void cdnc_uart_bus_ungrab(struct uart_softc *); 398 399 static kobj_method_t cdnc_uart_bus_methods[] = { 400 KOBJMETHOD(uart_probe, cdnc_uart_bus_probe), 401 KOBJMETHOD(uart_attach, cdnc_uart_bus_attach), 402 KOBJMETHOD(uart_flush, cdnc_uart_bus_flush), 403 KOBJMETHOD(uart_getsig, cdnc_uart_bus_getsig), 404 KOBJMETHOD(uart_ioctl, cdnc_uart_bus_ioctl), 405 KOBJMETHOD(uart_ipend, cdnc_uart_bus_ipend), 406 KOBJMETHOD(uart_param, cdnc_uart_bus_param), 407 KOBJMETHOD(uart_receive, cdnc_uart_bus_receive), 408 KOBJMETHOD(uart_setsig, cdnc_uart_bus_setsig), 409 KOBJMETHOD(uart_transmit, cdnc_uart_bus_transmit), 410 KOBJMETHOD(uart_grab, cdnc_uart_bus_grab), 411 KOBJMETHOD(uart_ungrab, cdnc_uart_bus_ungrab), 412 413 KOBJMETHOD_END 414 }; 415 416 int 417 cdnc_uart_bus_probe(struct uart_softc *sc) 418 { 419 420 sc->sc_txfifosz = UART_FIFO_SIZE; 421 sc->sc_rxfifosz = UART_FIFO_SIZE; 422 sc->sc_hwiflow = 0; 423 sc->sc_hwoflow = 0; 424 425 device_set_desc(sc->sc_dev, "Cadence UART"); 426 427 return (0); 428 } 429 430 static int 431 cdnc_uart_bus_attach(struct uart_softc *sc) 432 { 433 struct uart_bas *bas = &sc->sc_bas; 434 struct uart_devinfo *di; 435 436 if (sc->sc_sysdev != NULL) { 437 di = sc->sc_sysdev; 438 (void)cdnc_uart_set_params(bas, di->baudrate, di->databits, 439 di->stopbits, di->parity); 440 } else 441 cdnc_uart_hw_init(bas); 442 443 (void)cdnc_uart_bus_getsig(sc); 444 445 /* Enable interrupts. */ 446 WR4(bas, CDNC_UART_IEN_REG, 447 CDNC_UART_INT_RXTRIG | CDNC_UART_INT_RXTMOUT | 448 CDNC_UART_INT_TXOVR | CDNC_UART_INT_RXOVR | 449 CDNC_UART_INT_DMSI); 450 451 return (0); 452 } 453 454 static int 455 cdnc_uart_bus_transmit(struct uart_softc *sc) 456 { 457 int i; 458 struct uart_bas *bas = &sc->sc_bas; 459 460 uart_lock(sc->sc_hwmtx); 461 462 /* Clear sticky TXEMPTY status bit. */ 463 WR4(bas, CDNC_UART_ISTAT_REG, CDNC_UART_INT_TXEMPTY); 464 465 for (i = 0; i < sc->sc_txdatasz; i++) 466 WR4(bas, CDNC_UART_FIFO, sc->sc_txbuf[i]); 467 468 /* Enable TX empty interrupt. */ 469 WR4(bas, CDNC_UART_IEN_REG, CDNC_UART_INT_TXEMPTY); 470 sc->sc_txbusy = 1; 471 472 uart_unlock(sc->sc_hwmtx); 473 474 return (0); 475 } 476 477 static int 478 cdnc_uart_bus_setsig(struct uart_softc *sc, int sig) 479 { 480 struct uart_bas *bas = &sc->sc_bas; 481 uint32_t new, old, modem_ctrl; 482 483 do { 484 old = sc->sc_hwsig; 485 new = old; 486 if (sig & SER_DDTR) { 487 SIGCHG(sig & SER_DTR, new, SER_DTR, SER_DDTR); 488 } 489 if (sig & SER_DRTS) { 490 SIGCHG(sig & SER_RTS, new, SER_RTS, SER_DRTS); 491 } 492 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 493 uart_lock(sc->sc_hwmtx); 494 modem_ctrl = RD4(bas, CDNC_UART_MODEM_CTRL_REG) & 495 ~(CDNC_UART_MODEM_CTRL_REG_DTR | CDNC_UART_MODEM_CTRL_REG_RTS); 496 if ((new & SER_DTR) != 0) 497 modem_ctrl |= CDNC_UART_MODEM_CTRL_REG_DTR; 498 if ((new & SER_RTS) != 0) 499 modem_ctrl |= CDNC_UART_MODEM_CTRL_REG_RTS; 500 WR4(bas, CDNC_UART_MODEM_CTRL_REG, modem_ctrl); 501 502 uart_unlock(sc->sc_hwmtx); 503 return (0); 504 } 505 506 static int 507 cdnc_uart_bus_receive(struct uart_softc *sc) 508 { 509 struct uart_bas *bas = &sc->sc_bas; 510 uint32_t status; 511 int c, c_status = 0; 512 513 uart_lock(sc->sc_hwmtx); 514 515 /* Check for parity or framing errors and clear the status bits. */ 516 status = RD4(bas, CDNC_UART_ISTAT_REG); 517 if ((status & (CDNC_UART_INT_FRAMING | CDNC_UART_INT_PARITY)) != 0) { 518 WR4(bas, CDNC_UART_ISTAT_REG, 519 status & (CDNC_UART_INT_FRAMING | CDNC_UART_INT_PARITY)); 520 if ((status & CDNC_UART_INT_PARITY) != 0) 521 c_status |= UART_STAT_PARERR; 522 if ((status & CDNC_UART_INT_FRAMING) != 0) 523 c_status |= UART_STAT_FRAMERR; 524 } 525 526 while ((RD4(bas, CDNC_UART_CHAN_STAT_REG) & 527 CDNC_UART_CHAN_STAT_REG_RXEMPTY) == 0) { 528 c = RD4(bas, CDNC_UART_FIFO) & 0xff; 529 #ifdef KDB 530 /* Detect break and drop into debugger. */ 531 if (c == 0 && (c_status & UART_STAT_FRAMERR) != 0 && 532 sc->sc_sysdev != NULL && 533 sc->sc_sysdev->type == UART_DEV_CONSOLE) { 534 kdb_break(); 535 WR4(bas, CDNC_UART_ISTAT_REG, CDNC_UART_INT_FRAMING); 536 } 537 #endif 538 uart_rx_put(sc, c | c_status); 539 } 540 541 uart_unlock(sc->sc_hwmtx); 542 543 return (0); 544 } 545 546 static int 547 cdnc_uart_bus_param(struct uart_softc *sc, int baudrate, int databits, 548 int stopbits, int parity) 549 { 550 551 return (cdnc_uart_set_params(&sc->sc_bas, baudrate, 552 databits, stopbits, parity)); 553 } 554 555 static int 556 cdnc_uart_bus_ipend(struct uart_softc *sc) 557 { 558 int ipend = 0; 559 struct uart_bas *bas = &sc->sc_bas; 560 uint32_t istatus; 561 562 uart_lock(sc->sc_hwmtx); 563 564 istatus = RD4(bas, CDNC_UART_ISTAT_REG); 565 566 /* Clear interrupt bits. */ 567 WR4(bas, CDNC_UART_ISTAT_REG, istatus & 568 (CDNC_UART_INT_RXTRIG | CDNC_UART_INT_RXTMOUT | 569 CDNC_UART_INT_TXOVR | CDNC_UART_INT_RXOVR | 570 CDNC_UART_INT_TXEMPTY | CDNC_UART_INT_DMSI)); 571 572 /* Receive data. */ 573 if ((istatus & (CDNC_UART_INT_RXTRIG | CDNC_UART_INT_RXTMOUT)) != 0) 574 ipend |= SER_INT_RXREADY; 575 576 /* Transmit fifo empty. */ 577 if (sc->sc_txbusy && (istatus & CDNC_UART_INT_TXEMPTY) != 0) { 578 /* disable txempty interrupt. */ 579 WR4(bas, CDNC_UART_IDIS_REG, CDNC_UART_INT_TXEMPTY); 580 ipend |= SER_INT_TXIDLE; 581 } 582 583 /* TX Overflow. */ 584 if ((istatus & CDNC_UART_INT_TXOVR) != 0) 585 ipend |= SER_INT_OVERRUN; 586 587 /* RX Overflow. */ 588 if ((istatus & CDNC_UART_INT_RXOVR) != 0) 589 ipend |= SER_INT_OVERRUN; 590 591 /* Modem signal change. */ 592 if ((istatus & CDNC_UART_INT_DMSI) != 0) { 593 WR4(bas, CDNC_UART_MODEM_STAT_REG, 594 CDNC_UART_MODEM_STAT_REG_DDCD | 595 CDNC_UART_MODEM_STAT_REG_TERI | 596 CDNC_UART_MODEM_STAT_REG_DDSR | 597 CDNC_UART_MODEM_STAT_REG_DCTS); 598 ipend |= SER_INT_SIGCHG; 599 } 600 601 uart_unlock(sc->sc_hwmtx); 602 return (ipend); 603 } 604 605 static int 606 cdnc_uart_bus_flush(struct uart_softc *sc, int what) 607 { 608 609 return (0); 610 } 611 612 static int 613 cdnc_uart_bus_getsig(struct uart_softc *sc) 614 { 615 struct uart_bas *bas = &sc->sc_bas; 616 uint32_t new, old, sig; 617 uint8_t modem_status; 618 619 do { 620 old = sc->sc_hwsig; 621 sig = old; 622 uart_lock(sc->sc_hwmtx); 623 modem_status = RD4(bas, CDNC_UART_MODEM_STAT_REG); 624 uart_unlock(sc->sc_hwmtx); 625 SIGCHG(modem_status & CDNC_UART_MODEM_STAT_REG_DSR, 626 sig, SER_DSR, SER_DDSR); 627 SIGCHG(modem_status & CDNC_UART_MODEM_STAT_REG_CTS, 628 sig, SER_CTS, SER_DCTS); 629 SIGCHG(modem_status & CDNC_UART_MODEM_STAT_REG_DCD, 630 sig, SER_DCD, SER_DDCD); 631 SIGCHG(modem_status & CDNC_UART_MODEM_STAT_REG_RI, 632 sig, SER_RI, SER_DRI); 633 new = sig & ~SER_MASK_DELTA; 634 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 635 return (sig); 636 } 637 638 static int 639 cdnc_uart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 640 { 641 struct uart_bas *bas = &sc->sc_bas; 642 uint32_t uart_ctrl, modem_ctrl; 643 int error = 0; 644 645 uart_lock(sc->sc_hwmtx); 646 647 switch (request) { 648 case UART_IOCTL_BREAK: 649 uart_ctrl = RD4(bas, CDNC_UART_CTRL_REG); 650 if (data) { 651 uart_ctrl |= CDNC_UART_CTRL_REG_STARTBRK; 652 uart_ctrl &= ~CDNC_UART_CTRL_REG_STOPBRK; 653 } else { 654 uart_ctrl |= CDNC_UART_CTRL_REG_STOPBRK; 655 uart_ctrl &= ~CDNC_UART_CTRL_REG_STARTBRK; 656 } 657 WR4(bas, CDNC_UART_CTRL_REG, uart_ctrl); 658 break; 659 case UART_IOCTL_IFLOW: 660 modem_ctrl = RD4(bas, CDNC_UART_MODEM_CTRL_REG); 661 if (data) 662 modem_ctrl |= CDNC_UART_MODEM_CTRL_REG_RTS; 663 else 664 modem_ctrl &= ~CDNC_UART_MODEM_CTRL_REG_RTS; 665 WR4(bas, CDNC_UART_MODEM_CTRL_REG, modem_ctrl); 666 break; 667 default: 668 error = EINVAL; 669 break; 670 } 671 672 uart_unlock(sc->sc_hwmtx); 673 674 return (error); 675 } 676 677 static void 678 cdnc_uart_bus_grab(struct uart_softc *sc) 679 { 680 681 /* Enable interrupts. */ 682 WR4(&sc->sc_bas, CDNC_UART_IEN_REG, 683 CDNC_UART_INT_TXOVR | CDNC_UART_INT_RXOVR | 684 CDNC_UART_INT_DMSI); 685 } 686 687 static void 688 cdnc_uart_bus_ungrab(struct uart_softc *sc) 689 { 690 691 /* Enable interrupts. */ 692 WR4(&sc->sc_bas, CDNC_UART_IEN_REG, 693 CDNC_UART_INT_RXTRIG | CDNC_UART_INT_RXTMOUT | 694 CDNC_UART_INT_TXOVR | CDNC_UART_INT_RXOVR | 695 CDNC_UART_INT_DMSI); 696 } 697 698 static struct uart_class uart_cdnc_class = { 699 "cdnc_uart", 700 cdnc_uart_bus_methods, 701 sizeof(struct uart_softc), 702 .uc_ops = &cdnc_uart_ops, 703 .uc_range = 8 704 }; 705 706 static struct ofw_compat_data compat_data[] = { 707 {"cadence,uart", (uintptr_t)&uart_cdnc_class}, 708 {"cdns,uart-r1p12", (uintptr_t)&uart_cdnc_class}, 709 {"xlnx,xuartps", (uintptr_t)&uart_cdnc_class}, 710 {NULL, (uintptr_t)NULL}, 711 }; 712 UART_FDT_CLASS_AND_DEVICE(compat_data); 713