1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2005 Olivier Houchard All rights reserved. 5 * Copyright (c) 2012 Thomas Skibo All rights reserved. 6 * Copyright (c) 2005 M. Warner Losh <imp@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* A driver for the Cadence AMBA UART as used by the Xilinx Zynq-7000. 32 * 33 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual. 34 * (v1.4) November 16, 2012. Xilinx doc UG585. UART is covered in Ch. 19 35 * and register definitions are in appendix B.33. 36 */ 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/bus.h> 41 #include <sys/conf.h> 42 #include <sys/cons.h> 43 #include <machine/bus.h> 44 45 #include <dev/uart/uart.h> 46 #include <dev/uart/uart_cpu.h> 47 #include <dev/uart/uart_cpu_fdt.h> 48 #include <dev/uart/uart_bus.h> 49 50 #include "uart_if.h" 51 52 #define UART_FIFO_SIZE 64 53 54 #define RD4(bas, reg) \ 55 bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs((bas), (reg))) 56 #define WR4(bas, reg, value) \ 57 bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs((bas), (reg)), \ 58 (value)) 59 60 /* Register definitions for Cadence UART Controller. 61 */ 62 #define CDNC_UART_CTRL_REG 0x00 /* Control Register. */ 63 #define CDNC_UART_CTRL_REG_STOPBRK (1<<8) 64 #define CDNC_UART_CTRL_REG_STARTBRK (1<<7) 65 #define CDNC_UART_CTRL_REG_TORST (1<<6) 66 #define CDNC_UART_CTRL_REG_TX_DIS (1<<5) 67 #define CDNC_UART_CTRL_REG_TX_EN (1<<4) 68 #define CDNC_UART_CTRL_REG_RX_DIS (1<<3) 69 #define CDNC_UART_CTRL_REG_RX_EN (1<<2) 70 #define CDNC_UART_CTRL_REG_TXRST (1<<1) 71 #define CDNC_UART_CTRL_REG_RXRST (1<<0) 72 73 #define CDNC_UART_MODE_REG 0x04 /* Mode Register. */ 74 #define CDNC_UART_MODE_REG_CHMOD_R_LOOP (3<<8) /* [9:8] - channel mode */ 75 #define CDNC_UART_MODE_REG_CHMOD_L_LOOP (2<<8) 76 #define CDNC_UART_MODE_REG_CHMOD_AUTECHO (1<<8) 77 #define CDNC_UART_MODE_REG_STOP2 (2<<6) /* [7:6] - stop bits */ 78 #define CDNC_UART_MODE_REG_PAR_NONE (4<<3) /* [5:3] - parity type */ 79 #define CDNC_UART_MODE_REG_PAR_MARK (3<<3) 80 #define CDNC_UART_MODE_REG_PAR_SPACE (2<<3) 81 #define CDNC_UART_MODE_REG_PAR_ODD (1<<3) 82 #define CDNC_UART_MODE_REG_PAR_EVEN (0<<3) 83 #define CDNC_UART_MODE_REG_6BIT (3<<1) /* [2:1] - character len */ 84 #define CDNC_UART_MODE_REG_7BIT (2<<1) 85 #define CDNC_UART_MODE_REG_8BIT (0<<1) 86 #define CDNC_UART_MODE_REG_CLKSEL (1<<0) 87 88 #define CDNC_UART_IEN_REG 0x08 /* Interrupt registers. */ 89 #define CDNC_UART_IDIS_REG 0x0C 90 #define CDNC_UART_IMASK_REG 0x10 91 #define CDNC_UART_ISTAT_REG 0x14 92 #define CDNC_UART_INT_TXOVR (1<<12) 93 #define CDNC_UART_INT_TXNRLYFUL (1<<11) /* tx "nearly" full */ 94 #define CDNC_UART_INT_TXTRIG (1<<10) 95 #define CDNC_UART_INT_DMSI (1<<9) /* delta modem status */ 96 #define CDNC_UART_INT_RXTMOUT (1<<8) 97 #define CDNC_UART_INT_PARITY (1<<7) 98 #define CDNC_UART_INT_FRAMING (1<<6) 99 #define CDNC_UART_INT_RXOVR (1<<5) 100 #define CDNC_UART_INT_TXFULL (1<<4) 101 #define CDNC_UART_INT_TXEMPTY (1<<3) 102 #define CDNC_UART_INT_RXFULL (1<<2) 103 #define CDNC_UART_INT_RXEMPTY (1<<1) 104 #define CDNC_UART_INT_RXTRIG (1<<0) 105 #define CDNC_UART_INT_ALL 0x1FFF 106 107 #define CDNC_UART_BAUDGEN_REG 0x18 108 #define CDNC_UART_RX_TIMEO_REG 0x1C 109 #define CDNC_UART_RX_WATER_REG 0x20 110 111 #define CDNC_UART_MODEM_CTRL_REG 0x24 112 #define CDNC_UART_MODEM_CTRL_REG_FCM (1<<5) /* automatic flow control */ 113 #define CDNC_UART_MODEM_CTRL_REG_RTS (1<<1) 114 #define CDNC_UART_MODEM_CTRL_REG_DTR (1<<0) 115 116 #define CDNC_UART_MODEM_STAT_REG 0x28 117 #define CDNC_UART_MODEM_STAT_REG_FCMS (1<<8) /* flow control mode (rw) */ 118 #define CDNC_UART_MODEM_STAT_REG_DCD (1<<7) 119 #define CDNC_UART_MODEM_STAT_REG_RI (1<<6) 120 #define CDNC_UART_MODEM_STAT_REG_DSR (1<<5) 121 #define CDNC_UART_MODEM_STAT_REG_CTS (1<<4) 122 #define CDNC_UART_MODEM_STAT_REG_DDCD (1<<3) /* change in DCD (w1tc) */ 123 #define CDNC_UART_MODEM_STAT_REG_TERI (1<<2) /* trail edge ring (w1tc) */ 124 #define CDNC_UART_MODEM_STAT_REG_DDSR (1<<1) /* change in DSR (w1tc) */ 125 #define CDNC_UART_MODEM_STAT_REG_DCTS (1<<0) /* change in CTS (w1tc) */ 126 127 #define CDNC_UART_CHAN_STAT_REG 0x2C /* Channel status register. */ 128 #define CDNC_UART_CHAN_STAT_REG_TXNRLYFUL (1<<14) /* tx "nearly" full */ 129 #define CDNC_UART_CHAN_STAT_REG_TXTRIG (1<<13) 130 #define CDNC_UART_CHAN_STAT_REG_FDELT (1<<12) 131 #define CDNC_UART_CHAN_STAT_REG_TXACTIVE (1<<11) 132 #define CDNC_UART_CHAN_STAT_REG_RXACTIVE (1<<10) 133 #define CDNC_UART_CHAN_STAT_REG_TXFULL (1<<4) 134 #define CDNC_UART_CHAN_STAT_REG_TXEMPTY (1<<3) 135 #define CDNC_UART_CHAN_STAT_REG_RXEMPTY (1<<1) 136 #define CDNC_UART_CHAN_STAT_REG_RXTRIG (1<<0) 137 138 #define CDNC_UART_FIFO 0x30 /* Data FIFO (tx and rx) */ 139 #define CDNC_UART_BAUDDIV_REG 0x34 140 #define CDNC_UART_FLOWDEL_REG 0x38 141 #define CDNC_UART_TX_WATER_REG 0x44 142 143 /* 144 * Low-level UART interface. 145 */ 146 static int cdnc_uart_probe(struct uart_bas *bas); 147 static void cdnc_uart_init(struct uart_bas *bas, int, int, int, int); 148 static void cdnc_uart_term(struct uart_bas *bas); 149 static void cdnc_uart_putc(struct uart_bas *bas, int); 150 static int cdnc_uart_rxready(struct uart_bas *bas); 151 static int cdnc_uart_getc(struct uart_bas *bas, struct mtx *mtx); 152 153 extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs; 154 155 static struct uart_ops cdnc_uart_ops = { 156 .probe = cdnc_uart_probe, 157 .init = cdnc_uart_init, 158 .term = cdnc_uart_term, 159 .putc = cdnc_uart_putc, 160 .rxready = cdnc_uart_rxready, 161 .getc = cdnc_uart_getc, 162 }; 163 164 #define SIGCHG(c, i, s, d) \ 165 if (c) { \ 166 i |= (i & s) ? s : s | d; \ 167 } else { \ 168 i = (i & s) ? (i & ~s) | d : i; \ 169 } 170 171 static int 172 cdnc_uart_probe(struct uart_bas *bas) 173 { 174 175 return (0); 176 } 177 178 static int 179 cdnc_uart_set_baud(struct uart_bas *bas, int baudrate) 180 { 181 uint32_t baudgen, bauddiv; 182 uint32_t best_bauddiv, best_baudgen, best_error; 183 uint32_t baud_out, err; 184 185 best_bauddiv = 0; 186 best_baudgen = 0; 187 best_error = ~0; 188 189 /* Try all possible bauddiv values and pick best match. */ 190 for (bauddiv = 4; bauddiv <= 255; bauddiv++) { 191 baudgen = (bas->rclk + (baudrate * (bauddiv + 1)) / 2) / 192 (baudrate * (bauddiv + 1)); 193 if (baudgen < 1 || baudgen > 0xffff) 194 continue; 195 196 baud_out = bas->rclk / (baudgen * (bauddiv + 1)); 197 err = baud_out > baudrate ? 198 baud_out - baudrate : baudrate - baud_out; 199 200 if (err < best_error) { 201 best_error = err; 202 best_bauddiv = bauddiv; 203 best_baudgen = baudgen; 204 } 205 } 206 207 if (best_bauddiv > 0) { 208 WR4(bas, CDNC_UART_BAUDDIV_REG, best_bauddiv); 209 WR4(bas, CDNC_UART_BAUDGEN_REG, best_baudgen); 210 return (0); 211 } else 212 return (-1); /* out of range */ 213 } 214 215 static int 216 cdnc_uart_set_params(struct uart_bas *bas, int baudrate, int databits, 217 int stopbits, int parity) 218 { 219 uint32_t mode_reg_value = 0; 220 221 switch (databits) { 222 case 6: 223 mode_reg_value |= CDNC_UART_MODE_REG_6BIT; 224 break; 225 case 7: 226 mode_reg_value |= CDNC_UART_MODE_REG_7BIT; 227 break; 228 case 8: 229 default: 230 mode_reg_value |= CDNC_UART_MODE_REG_8BIT; 231 break; 232 } 233 234 if (stopbits == 2) 235 mode_reg_value |= CDNC_UART_MODE_REG_STOP2; 236 237 switch (parity) { 238 case UART_PARITY_MARK: 239 mode_reg_value |= CDNC_UART_MODE_REG_PAR_MARK; 240 break; 241 case UART_PARITY_SPACE: 242 mode_reg_value |= CDNC_UART_MODE_REG_PAR_SPACE; 243 break; 244 case UART_PARITY_ODD: 245 mode_reg_value |= CDNC_UART_MODE_REG_PAR_ODD; 246 break; 247 case UART_PARITY_EVEN: 248 mode_reg_value |= CDNC_UART_MODE_REG_PAR_EVEN; 249 break; 250 case UART_PARITY_NONE: 251 default: 252 mode_reg_value |= CDNC_UART_MODE_REG_PAR_NONE; 253 break; 254 } 255 256 WR4(bas, CDNC_UART_MODE_REG, mode_reg_value); 257 258 if (baudrate > 0 && cdnc_uart_set_baud(bas, baudrate) < 0) 259 return (EINVAL); 260 261 return(0); 262 } 263 264 static void 265 cdnc_uart_hw_init(struct uart_bas *bas) 266 { 267 268 /* Reset RX and TX. */ 269 WR4(bas, CDNC_UART_CTRL_REG, 270 CDNC_UART_CTRL_REG_RXRST | CDNC_UART_CTRL_REG_TXRST); 271 272 /* Interrupts all off. */ 273 WR4(bas, CDNC_UART_IDIS_REG, CDNC_UART_INT_ALL); 274 WR4(bas, CDNC_UART_ISTAT_REG, CDNC_UART_INT_ALL); 275 276 /* Clear delta bits. */ 277 WR4(bas, CDNC_UART_MODEM_STAT_REG, 278 CDNC_UART_MODEM_STAT_REG_DDCD | CDNC_UART_MODEM_STAT_REG_TERI | 279 CDNC_UART_MODEM_STAT_REG_DDSR | CDNC_UART_MODEM_STAT_REG_DCTS); 280 281 /* RX FIFO water level, stale timeout */ 282 WR4(bas, CDNC_UART_RX_WATER_REG, UART_FIFO_SIZE/2); 283 WR4(bas, CDNC_UART_RX_TIMEO_REG, 10); 284 285 /* TX FIFO water level (not used.) */ 286 WR4(bas, CDNC_UART_TX_WATER_REG, UART_FIFO_SIZE/2); 287 288 /* Bring RX and TX online. */ 289 WR4(bas, CDNC_UART_CTRL_REG, 290 CDNC_UART_CTRL_REG_RX_EN | CDNC_UART_CTRL_REG_TX_EN | 291 CDNC_UART_CTRL_REG_TORST | CDNC_UART_CTRL_REG_STOPBRK); 292 293 /* Set DTR and RTS. */ 294 WR4(bas, CDNC_UART_MODEM_CTRL_REG, CDNC_UART_MODEM_CTRL_REG_DTR | 295 CDNC_UART_MODEM_CTRL_REG_RTS); 296 } 297 298 /* 299 * Initialize this device for use as a console. 300 */ 301 static void 302 cdnc_uart_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 303 int parity) 304 { 305 306 /* Initialize hardware. */ 307 cdnc_uart_hw_init(bas); 308 309 /* Set baudrate, parameters. */ 310 (void)cdnc_uart_set_params(bas, baudrate, databits, stopbits, parity); 311 } 312 313 /* 314 * Free resources now that we're no longer the console. This appears to 315 * be never called, and I'm unsure quite what to do if I am called. 316 */ 317 static void 318 cdnc_uart_term(struct uart_bas *bas) 319 { 320 321 /* XXX */ 322 } 323 324 /* 325 * Put a character of console output (so we do it here polling rather than 326 * interrupt driven). 327 */ 328 static void 329 cdnc_uart_putc(struct uart_bas *bas, int c) 330 { 331 332 /* Wait for room. */ 333 while ((RD4(bas,CDNC_UART_CHAN_STAT_REG) & 334 CDNC_UART_CHAN_STAT_REG_TXFULL) != 0) 335 ; 336 337 WR4(bas, CDNC_UART_FIFO, c); 338 339 while ((RD4(bas,CDNC_UART_CHAN_STAT_REG) & 340 CDNC_UART_CHAN_STAT_REG_TXEMPTY) == 0) 341 ; 342 } 343 344 /* 345 * Check for a character available. 346 */ 347 static int 348 cdnc_uart_rxready(struct uart_bas *bas) 349 { 350 351 return ((RD4(bas, CDNC_UART_CHAN_STAT_REG) & 352 CDNC_UART_CHAN_STAT_REG_RXEMPTY) == 0); 353 } 354 355 /* 356 * Block waiting for a character. 357 */ 358 static int 359 cdnc_uart_getc(struct uart_bas *bas, struct mtx *mtx) 360 { 361 int c; 362 363 uart_lock(mtx); 364 365 while ((RD4(bas, CDNC_UART_CHAN_STAT_REG) & 366 CDNC_UART_CHAN_STAT_REG_RXEMPTY) != 0) { 367 uart_unlock(mtx); 368 DELAY(4); 369 uart_lock(mtx); 370 } 371 372 c = RD4(bas, CDNC_UART_FIFO); 373 374 uart_unlock(mtx); 375 376 c &= 0xff; 377 return (c); 378 } 379 380 /*****************************************************************************/ 381 /* 382 * High-level UART interface. 383 */ 384 385 static int cdnc_uart_bus_probe(struct uart_softc *sc); 386 static int cdnc_uart_bus_attach(struct uart_softc *sc); 387 static int cdnc_uart_bus_flush(struct uart_softc *, int); 388 static int cdnc_uart_bus_getsig(struct uart_softc *); 389 static int cdnc_uart_bus_ioctl(struct uart_softc *, int, intptr_t); 390 static int cdnc_uart_bus_ipend(struct uart_softc *); 391 static int cdnc_uart_bus_param(struct uart_softc *, int, int, int, int); 392 static int cdnc_uart_bus_receive(struct uart_softc *); 393 static int cdnc_uart_bus_setsig(struct uart_softc *, int); 394 static int cdnc_uart_bus_transmit(struct uart_softc *); 395 static void cdnc_uart_bus_grab(struct uart_softc *); 396 static void cdnc_uart_bus_ungrab(struct uart_softc *); 397 398 static kobj_method_t cdnc_uart_bus_methods[] = { 399 KOBJMETHOD(uart_probe, cdnc_uart_bus_probe), 400 KOBJMETHOD(uart_attach, cdnc_uart_bus_attach), 401 KOBJMETHOD(uart_flush, cdnc_uart_bus_flush), 402 KOBJMETHOD(uart_getsig, cdnc_uart_bus_getsig), 403 KOBJMETHOD(uart_ioctl, cdnc_uart_bus_ioctl), 404 KOBJMETHOD(uart_ipend, cdnc_uart_bus_ipend), 405 KOBJMETHOD(uart_param, cdnc_uart_bus_param), 406 KOBJMETHOD(uart_receive, cdnc_uart_bus_receive), 407 KOBJMETHOD(uart_setsig, cdnc_uart_bus_setsig), 408 KOBJMETHOD(uart_transmit, cdnc_uart_bus_transmit), 409 KOBJMETHOD(uart_grab, cdnc_uart_bus_grab), 410 KOBJMETHOD(uart_ungrab, cdnc_uart_bus_ungrab), 411 412 KOBJMETHOD_END 413 }; 414 415 int 416 cdnc_uart_bus_probe(struct uart_softc *sc) 417 { 418 419 sc->sc_txfifosz = UART_FIFO_SIZE; 420 sc->sc_rxfifosz = UART_FIFO_SIZE; 421 sc->sc_hwiflow = 0; 422 sc->sc_hwoflow = 0; 423 424 device_set_desc(sc->sc_dev, "Cadence UART"); 425 426 return (0); 427 } 428 429 static int 430 cdnc_uart_bus_attach(struct uart_softc *sc) 431 { 432 struct uart_bas *bas = &sc->sc_bas; 433 struct uart_devinfo *di; 434 435 if (sc->sc_sysdev != NULL) { 436 di = sc->sc_sysdev; 437 (void)cdnc_uart_set_params(bas, di->baudrate, di->databits, 438 di->stopbits, di->parity); 439 } else 440 cdnc_uart_hw_init(bas); 441 442 (void)cdnc_uart_bus_getsig(sc); 443 444 /* Enable interrupts. */ 445 WR4(bas, CDNC_UART_IEN_REG, 446 CDNC_UART_INT_RXTRIG | CDNC_UART_INT_RXTMOUT | 447 CDNC_UART_INT_TXOVR | CDNC_UART_INT_RXOVR | 448 CDNC_UART_INT_DMSI); 449 450 return (0); 451 } 452 453 static int 454 cdnc_uart_bus_transmit(struct uart_softc *sc) 455 { 456 int i; 457 struct uart_bas *bas = &sc->sc_bas; 458 459 uart_lock(sc->sc_hwmtx); 460 461 /* Clear sticky TXEMPTY status bit. */ 462 WR4(bas, CDNC_UART_ISTAT_REG, CDNC_UART_INT_TXEMPTY); 463 464 for (i = 0; i < sc->sc_txdatasz; i++) 465 WR4(bas, CDNC_UART_FIFO, sc->sc_txbuf[i]); 466 467 /* Enable TX empty interrupt. */ 468 WR4(bas, CDNC_UART_IEN_REG, CDNC_UART_INT_TXEMPTY); 469 sc->sc_txbusy = 1; 470 471 uart_unlock(sc->sc_hwmtx); 472 473 return (0); 474 } 475 476 static int 477 cdnc_uart_bus_setsig(struct uart_softc *sc, int sig) 478 { 479 struct uart_bas *bas = &sc->sc_bas; 480 uint32_t new, old, modem_ctrl; 481 482 do { 483 old = sc->sc_hwsig; 484 new = old; 485 if (sig & SER_DDTR) { 486 SIGCHG(sig & SER_DTR, new, SER_DTR, SER_DDTR); 487 } 488 if (sig & SER_DRTS) { 489 SIGCHG(sig & SER_RTS, new, SER_RTS, SER_DRTS); 490 } 491 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 492 uart_lock(sc->sc_hwmtx); 493 modem_ctrl = RD4(bas, CDNC_UART_MODEM_CTRL_REG) & 494 ~(CDNC_UART_MODEM_CTRL_REG_DTR | CDNC_UART_MODEM_CTRL_REG_RTS); 495 if ((new & SER_DTR) != 0) 496 modem_ctrl |= CDNC_UART_MODEM_CTRL_REG_DTR; 497 if ((new & SER_RTS) != 0) 498 modem_ctrl |= CDNC_UART_MODEM_CTRL_REG_RTS; 499 WR4(bas, CDNC_UART_MODEM_CTRL_REG, modem_ctrl); 500 501 uart_unlock(sc->sc_hwmtx); 502 return (0); 503 } 504 505 static int 506 cdnc_uart_bus_receive(struct uart_softc *sc) 507 { 508 struct uart_bas *bas = &sc->sc_bas; 509 uint32_t status; 510 int c, c_status = 0; 511 512 uart_lock(sc->sc_hwmtx); 513 514 /* Check for parity or framing errors and clear the status bits. */ 515 status = RD4(bas, CDNC_UART_ISTAT_REG); 516 if ((status & (CDNC_UART_INT_FRAMING | CDNC_UART_INT_PARITY)) != 0) { 517 WR4(bas, CDNC_UART_ISTAT_REG, 518 status & (CDNC_UART_INT_FRAMING | CDNC_UART_INT_PARITY)); 519 if ((status & CDNC_UART_INT_PARITY) != 0) 520 c_status |= UART_STAT_PARERR; 521 if ((status & CDNC_UART_INT_FRAMING) != 0) 522 c_status |= UART_STAT_FRAMERR; 523 } 524 525 while ((RD4(bas, CDNC_UART_CHAN_STAT_REG) & 526 CDNC_UART_CHAN_STAT_REG_RXEMPTY) == 0) { 527 c = RD4(bas, CDNC_UART_FIFO) & 0xff; 528 #ifdef KDB 529 /* Detect break and drop into debugger. */ 530 if (c == 0 && (c_status & UART_STAT_FRAMERR) != 0 && 531 sc->sc_sysdev != NULL && 532 sc->sc_sysdev->type == UART_DEV_CONSOLE) { 533 kdb_break(); 534 WR4(bas, CDNC_UART_ISTAT_REG, CDNC_UART_INT_FRAMING); 535 } 536 #endif 537 uart_rx_put(sc, c | c_status); 538 } 539 540 uart_unlock(sc->sc_hwmtx); 541 542 return (0); 543 } 544 545 static int 546 cdnc_uart_bus_param(struct uart_softc *sc, int baudrate, int databits, 547 int stopbits, int parity) 548 { 549 550 return (cdnc_uart_set_params(&sc->sc_bas, baudrate, 551 databits, stopbits, parity)); 552 } 553 554 static int 555 cdnc_uart_bus_ipend(struct uart_softc *sc) 556 { 557 int ipend = 0; 558 struct uart_bas *bas = &sc->sc_bas; 559 uint32_t istatus; 560 561 uart_lock(sc->sc_hwmtx); 562 563 istatus = RD4(bas, CDNC_UART_ISTAT_REG); 564 565 /* Clear interrupt bits. */ 566 WR4(bas, CDNC_UART_ISTAT_REG, istatus & 567 (CDNC_UART_INT_RXTRIG | CDNC_UART_INT_RXTMOUT | 568 CDNC_UART_INT_TXOVR | CDNC_UART_INT_RXOVR | 569 CDNC_UART_INT_TXEMPTY | CDNC_UART_INT_DMSI)); 570 571 /* Receive data. */ 572 if ((istatus & (CDNC_UART_INT_RXTRIG | CDNC_UART_INT_RXTMOUT)) != 0) 573 ipend |= SER_INT_RXREADY; 574 575 /* Transmit fifo empty. */ 576 if (sc->sc_txbusy && (istatus & CDNC_UART_INT_TXEMPTY) != 0) { 577 /* disable txempty interrupt. */ 578 WR4(bas, CDNC_UART_IDIS_REG, CDNC_UART_INT_TXEMPTY); 579 ipend |= SER_INT_TXIDLE; 580 } 581 582 /* TX Overflow. */ 583 if ((istatus & CDNC_UART_INT_TXOVR) != 0) 584 ipend |= SER_INT_OVERRUN; 585 586 /* RX Overflow. */ 587 if ((istatus & CDNC_UART_INT_RXOVR) != 0) 588 ipend |= SER_INT_OVERRUN; 589 590 /* Modem signal change. */ 591 if ((istatus & CDNC_UART_INT_DMSI) != 0) { 592 WR4(bas, CDNC_UART_MODEM_STAT_REG, 593 CDNC_UART_MODEM_STAT_REG_DDCD | 594 CDNC_UART_MODEM_STAT_REG_TERI | 595 CDNC_UART_MODEM_STAT_REG_DDSR | 596 CDNC_UART_MODEM_STAT_REG_DCTS); 597 ipend |= SER_INT_SIGCHG; 598 } 599 600 uart_unlock(sc->sc_hwmtx); 601 return (ipend); 602 } 603 604 static int 605 cdnc_uart_bus_flush(struct uart_softc *sc, int what) 606 { 607 608 return (0); 609 } 610 611 static int 612 cdnc_uart_bus_getsig(struct uart_softc *sc) 613 { 614 struct uart_bas *bas = &sc->sc_bas; 615 uint32_t new, old, sig; 616 uint8_t modem_status; 617 618 do { 619 old = sc->sc_hwsig; 620 sig = old; 621 uart_lock(sc->sc_hwmtx); 622 modem_status = RD4(bas, CDNC_UART_MODEM_STAT_REG); 623 uart_unlock(sc->sc_hwmtx); 624 SIGCHG(modem_status & CDNC_UART_MODEM_STAT_REG_DSR, 625 sig, SER_DSR, SER_DDSR); 626 SIGCHG(modem_status & CDNC_UART_MODEM_STAT_REG_CTS, 627 sig, SER_CTS, SER_DCTS); 628 SIGCHG(modem_status & CDNC_UART_MODEM_STAT_REG_DCD, 629 sig, SER_DCD, SER_DDCD); 630 SIGCHG(modem_status & CDNC_UART_MODEM_STAT_REG_RI, 631 sig, SER_RI, SER_DRI); 632 new = sig & ~SER_MASK_DELTA; 633 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 634 return (sig); 635 } 636 637 static int 638 cdnc_uart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 639 { 640 struct uart_bas *bas = &sc->sc_bas; 641 uint32_t uart_ctrl, modem_ctrl; 642 int error = 0; 643 644 uart_lock(sc->sc_hwmtx); 645 646 switch (request) { 647 case UART_IOCTL_BREAK: 648 uart_ctrl = RD4(bas, CDNC_UART_CTRL_REG); 649 if (data) { 650 uart_ctrl |= CDNC_UART_CTRL_REG_STARTBRK; 651 uart_ctrl &= ~CDNC_UART_CTRL_REG_STOPBRK; 652 } else { 653 uart_ctrl |= CDNC_UART_CTRL_REG_STOPBRK; 654 uart_ctrl &= ~CDNC_UART_CTRL_REG_STARTBRK; 655 } 656 WR4(bas, CDNC_UART_CTRL_REG, uart_ctrl); 657 break; 658 case UART_IOCTL_IFLOW: 659 modem_ctrl = RD4(bas, CDNC_UART_MODEM_CTRL_REG); 660 if (data) 661 modem_ctrl |= CDNC_UART_MODEM_CTRL_REG_RTS; 662 else 663 modem_ctrl &= ~CDNC_UART_MODEM_CTRL_REG_RTS; 664 WR4(bas, CDNC_UART_MODEM_CTRL_REG, modem_ctrl); 665 break; 666 default: 667 error = EINVAL; 668 break; 669 } 670 671 uart_unlock(sc->sc_hwmtx); 672 673 return (error); 674 } 675 676 static void 677 cdnc_uart_bus_grab(struct uart_softc *sc) 678 { 679 680 /* Enable interrupts. */ 681 WR4(&sc->sc_bas, CDNC_UART_IEN_REG, 682 CDNC_UART_INT_TXOVR | CDNC_UART_INT_RXOVR | 683 CDNC_UART_INT_DMSI); 684 } 685 686 static void 687 cdnc_uart_bus_ungrab(struct uart_softc *sc) 688 { 689 690 /* Enable interrupts. */ 691 WR4(&sc->sc_bas, CDNC_UART_IEN_REG, 692 CDNC_UART_INT_RXTRIG | CDNC_UART_INT_RXTMOUT | 693 CDNC_UART_INT_TXOVR | CDNC_UART_INT_RXOVR | 694 CDNC_UART_INT_DMSI); 695 } 696 697 static struct uart_class uart_cdnc_class = { 698 "cdnc_uart", 699 cdnc_uart_bus_methods, 700 sizeof(struct uart_softc), 701 .uc_ops = &cdnc_uart_ops, 702 .uc_range = 8 703 }; 704 705 static struct ofw_compat_data compat_data[] = { 706 {"cadence,uart", (uintptr_t)&uart_cdnc_class}, 707 {"cdns,uart-r1p12", (uintptr_t)&uart_cdnc_class}, 708 {"xlnx,xuartps", (uintptr_t)&uart_cdnc_class}, 709 {NULL, (uintptr_t)NULL}, 710 }; 711 UART_FDT_CLASS_AND_DEVICE(compat_data); 712