1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2005 Olivier Houchard All rights reserved. 5 * Copyright (c) 2012 Thomas Skibo All rights reserved. 6 * Copyright (c) 2005 M. Warner Losh <imp@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* A driver for the Cadence AMBA UART as used by the Xilinx Zynq-7000. 32 * 33 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual. 34 * (v1.4) November 16, 2012. Xilinx doc UG585. UART is covered in Ch. 19 35 * and register definitions are in appendix B.33. 36 */ 37 38 #include <sys/cdefs.h> 39 __FBSDID("$FreeBSD$"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/bus.h> 44 #include <sys/conf.h> 45 #include <sys/cons.h> 46 #include <machine/bus.h> 47 48 #include <dev/uart/uart.h> 49 #include <dev/uart/uart_cpu.h> 50 #include <dev/uart/uart_cpu_fdt.h> 51 #include <dev/uart/uart_bus.h> 52 53 #include "uart_if.h" 54 55 #define UART_FIFO_SIZE 64 56 57 #define RD4(bas, reg) \ 58 bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs((bas), (reg))) 59 #define WR4(bas, reg, value) \ 60 bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs((bas), (reg)), \ 61 (value)) 62 63 /* Register definitions for Cadence UART Controller. 64 */ 65 #define CDNC_UART_CTRL_REG 0x00 /* Control Register. */ 66 #define CDNC_UART_CTRL_REG_STOPBRK (1<<8) 67 #define CDNC_UART_CTRL_REG_STARTBRK (1<<7) 68 #define CDNC_UART_CTRL_REG_TORST (1<<6) 69 #define CDNC_UART_CTRL_REG_TX_DIS (1<<5) 70 #define CDNC_UART_CTRL_REG_TX_EN (1<<4) 71 #define CDNC_UART_CTRL_REG_RX_DIS (1<<3) 72 #define CDNC_UART_CTRL_REG_RX_EN (1<<2) 73 #define CDNC_UART_CTRL_REG_TXRST (1<<1) 74 #define CDNC_UART_CTRL_REG_RXRST (1<<0) 75 76 #define CDNC_UART_MODE_REG 0x04 /* Mode Register. */ 77 #define CDNC_UART_MODE_REG_CHMOD_R_LOOP (3<<8) /* [9:8] - channel mode */ 78 #define CDNC_UART_MODE_REG_CHMOD_L_LOOP (2<<8) 79 #define CDNC_UART_MODE_REG_CHMOD_AUTECHO (1<<8) 80 #define CDNC_UART_MODE_REG_STOP2 (2<<6) /* [7:6] - stop bits */ 81 #define CDNC_UART_MODE_REG_PAR_NONE (4<<3) /* [5:3] - parity type */ 82 #define CDNC_UART_MODE_REG_PAR_MARK (3<<3) 83 #define CDNC_UART_MODE_REG_PAR_SPACE (2<<3) 84 #define CDNC_UART_MODE_REG_PAR_ODD (1<<3) 85 #define CDNC_UART_MODE_REG_PAR_EVEN (0<<3) 86 #define CDNC_UART_MODE_REG_6BIT (3<<1) /* [2:1] - character len */ 87 #define CDNC_UART_MODE_REG_7BIT (2<<1) 88 #define CDNC_UART_MODE_REG_8BIT (0<<1) 89 #define CDNC_UART_MODE_REG_CLKSEL (1<<0) 90 91 #define CDNC_UART_IEN_REG 0x08 /* Interrupt registers. */ 92 #define CDNC_UART_IDIS_REG 0x0C 93 #define CDNC_UART_IMASK_REG 0x10 94 #define CDNC_UART_ISTAT_REG 0x14 95 #define CDNC_UART_INT_TXOVR (1<<12) 96 #define CDNC_UART_INT_TXNRLYFUL (1<<11) /* tx "nearly" full */ 97 #define CDNC_UART_INT_TXTRIG (1<<10) 98 #define CDNC_UART_INT_DMSI (1<<9) /* delta modem status */ 99 #define CDNC_UART_INT_RXTMOUT (1<<8) 100 #define CDNC_UART_INT_PARITY (1<<7) 101 #define CDNC_UART_INT_FRAMING (1<<6) 102 #define CDNC_UART_INT_RXOVR (1<<5) 103 #define CDNC_UART_INT_TXFULL (1<<4) 104 #define CDNC_UART_INT_TXEMPTY (1<<3) 105 #define CDNC_UART_INT_RXFULL (1<<2) 106 #define CDNC_UART_INT_RXEMPTY (1<<1) 107 #define CDNC_UART_INT_RXTRIG (1<<0) 108 #define CDNC_UART_INT_ALL 0x1FFF 109 110 #define CDNC_UART_BAUDGEN_REG 0x18 111 #define CDNC_UART_RX_TIMEO_REG 0x1C 112 #define CDNC_UART_RX_WATER_REG 0x20 113 114 #define CDNC_UART_MODEM_CTRL_REG 0x24 115 #define CDNC_UART_MODEM_CTRL_REG_FCM (1<<5) /* automatic flow control */ 116 #define CDNC_UART_MODEM_CTRL_REG_RTS (1<<1) 117 #define CDNC_UART_MODEM_CTRL_REG_DTR (1<<0) 118 119 #define CDNC_UART_MODEM_STAT_REG 0x28 120 #define CDNC_UART_MODEM_STAT_REG_FCMS (1<<8) /* flow control mode (rw) */ 121 #define CDNC_UART_MODEM_STAT_REG_DCD (1<<7) 122 #define CDNC_UART_MODEM_STAT_REG_RI (1<<6) 123 #define CDNC_UART_MODEM_STAT_REG_DSR (1<<5) 124 #define CDNC_UART_MODEM_STAT_REG_CTS (1<<4) 125 #define CDNC_UART_MODEM_STAT_REG_DDCD (1<<3) /* change in DCD (w1tc) */ 126 #define CDNC_UART_MODEM_STAT_REG_TERI (1<<2) /* trail edge ring (w1tc) */ 127 #define CDNC_UART_MODEM_STAT_REG_DDSR (1<<1) /* change in DSR (w1tc) */ 128 #define CDNC_UART_MODEM_STAT_REG_DCTS (1<<0) /* change in CTS (w1tc) */ 129 130 #define CDNC_UART_CHAN_STAT_REG 0x2C /* Channel status register. */ 131 #define CDNC_UART_CHAN_STAT_REG_TXNRLYFUL (1<<14) /* tx "nearly" full */ 132 #define CDNC_UART_CHAN_STAT_REG_TXTRIG (1<<13) 133 #define CDNC_UART_CHAN_STAT_REG_FDELT (1<<12) 134 #define CDNC_UART_CHAN_STAT_REG_TXACTIVE (1<<11) 135 #define CDNC_UART_CHAN_STAT_REG_RXACTIVE (1<<10) 136 #define CDNC_UART_CHAN_STAT_REG_TXFULL (1<<4) 137 #define CDNC_UART_CHAN_STAT_REG_TXEMPTY (1<<3) 138 #define CDNC_UART_CHAN_STAT_REG_RXEMPTY (1<<1) 139 #define CDNC_UART_CHAN_STAT_REG_RXTRIG (1<<0) 140 141 #define CDNC_UART_FIFO 0x30 /* Data FIFO (tx and rx) */ 142 #define CDNC_UART_BAUDDIV_REG 0x34 143 #define CDNC_UART_FLOWDEL_REG 0x38 144 #define CDNC_UART_TX_WATER_REG 0x44 145 146 /* 147 * Low-level UART interface. 148 */ 149 static int cdnc_uart_probe(struct uart_bas *bas); 150 static void cdnc_uart_init(struct uart_bas *bas, int, int, int, int); 151 static void cdnc_uart_term(struct uart_bas *bas); 152 static void cdnc_uart_putc(struct uart_bas *bas, int); 153 static int cdnc_uart_rxready(struct uart_bas *bas); 154 static int cdnc_uart_getc(struct uart_bas *bas, struct mtx *mtx); 155 156 extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs; 157 158 static struct uart_ops cdnc_uart_ops = { 159 .probe = cdnc_uart_probe, 160 .init = cdnc_uart_init, 161 .term = cdnc_uart_term, 162 .putc = cdnc_uart_putc, 163 .rxready = cdnc_uart_rxready, 164 .getc = cdnc_uart_getc, 165 }; 166 167 #define SIGCHG(c, i, s, d) \ 168 if (c) { \ 169 i |= (i & s) ? s : s | d; \ 170 } else { \ 171 i = (i & s) ? (i & ~s) | d : i; \ 172 } 173 174 static int 175 cdnc_uart_probe(struct uart_bas *bas) 176 { 177 178 return (0); 179 } 180 181 static int 182 cdnc_uart_set_baud(struct uart_bas *bas, int baudrate) 183 { 184 uint32_t baudgen, bauddiv; 185 uint32_t best_bauddiv, best_baudgen, best_error; 186 uint32_t baud_out, err; 187 188 best_bauddiv = 0; 189 best_baudgen = 0; 190 best_error = ~0; 191 192 /* Try all possible bauddiv values and pick best match. */ 193 for (bauddiv = 4; bauddiv <= 255; bauddiv++) { 194 baudgen = (bas->rclk + (baudrate * (bauddiv + 1)) / 2) / 195 (baudrate * (bauddiv + 1)); 196 if (baudgen < 1 || baudgen > 0xffff) 197 continue; 198 199 baud_out = bas->rclk / (baudgen * (bauddiv + 1)); 200 err = baud_out > baudrate ? 201 baud_out - baudrate : baudrate - baud_out; 202 203 if (err < best_error) { 204 best_error = err; 205 best_bauddiv = bauddiv; 206 best_baudgen = baudgen; 207 } 208 } 209 210 if (best_bauddiv > 0) { 211 WR4(bas, CDNC_UART_BAUDDIV_REG, best_bauddiv); 212 WR4(bas, CDNC_UART_BAUDGEN_REG, best_baudgen); 213 return (0); 214 } else 215 return (-1); /* out of range */ 216 } 217 218 static int 219 cdnc_uart_set_params(struct uart_bas *bas, int baudrate, int databits, 220 int stopbits, int parity) 221 { 222 uint32_t mode_reg_value = 0; 223 224 switch (databits) { 225 case 6: 226 mode_reg_value |= CDNC_UART_MODE_REG_6BIT; 227 break; 228 case 7: 229 mode_reg_value |= CDNC_UART_MODE_REG_7BIT; 230 break; 231 case 8: 232 default: 233 mode_reg_value |= CDNC_UART_MODE_REG_8BIT; 234 break; 235 } 236 237 if (stopbits == 2) 238 mode_reg_value |= CDNC_UART_MODE_REG_STOP2; 239 240 switch (parity) { 241 case UART_PARITY_MARK: 242 mode_reg_value |= CDNC_UART_MODE_REG_PAR_MARK; 243 break; 244 case UART_PARITY_SPACE: 245 mode_reg_value |= CDNC_UART_MODE_REG_PAR_SPACE; 246 break; 247 case UART_PARITY_ODD: 248 mode_reg_value |= CDNC_UART_MODE_REG_PAR_ODD; 249 break; 250 case UART_PARITY_EVEN: 251 mode_reg_value |= CDNC_UART_MODE_REG_PAR_EVEN; 252 break; 253 case UART_PARITY_NONE: 254 default: 255 mode_reg_value |= CDNC_UART_MODE_REG_PAR_NONE; 256 break; 257 } 258 259 WR4(bas, CDNC_UART_MODE_REG, mode_reg_value); 260 261 if (baudrate > 0 && cdnc_uart_set_baud(bas, baudrate) < 0) 262 return (EINVAL); 263 264 return(0); 265 } 266 267 static void 268 cdnc_uart_hw_init(struct uart_bas *bas) 269 { 270 271 /* Reset RX and TX. */ 272 WR4(bas, CDNC_UART_CTRL_REG, 273 CDNC_UART_CTRL_REG_RXRST | CDNC_UART_CTRL_REG_TXRST); 274 275 /* Interrupts all off. */ 276 WR4(bas, CDNC_UART_IDIS_REG, CDNC_UART_INT_ALL); 277 WR4(bas, CDNC_UART_ISTAT_REG, CDNC_UART_INT_ALL); 278 279 /* Clear delta bits. */ 280 WR4(bas, CDNC_UART_MODEM_STAT_REG, 281 CDNC_UART_MODEM_STAT_REG_DDCD | CDNC_UART_MODEM_STAT_REG_TERI | 282 CDNC_UART_MODEM_STAT_REG_DDSR | CDNC_UART_MODEM_STAT_REG_DCTS); 283 284 /* RX FIFO water level, stale timeout */ 285 WR4(bas, CDNC_UART_RX_WATER_REG, UART_FIFO_SIZE/2); 286 WR4(bas, CDNC_UART_RX_TIMEO_REG, 10); 287 288 /* TX FIFO water level (not used.) */ 289 WR4(bas, CDNC_UART_TX_WATER_REG, UART_FIFO_SIZE/2); 290 291 /* Bring RX and TX online. */ 292 WR4(bas, CDNC_UART_CTRL_REG, 293 CDNC_UART_CTRL_REG_RX_EN | CDNC_UART_CTRL_REG_TX_EN | 294 CDNC_UART_CTRL_REG_TORST | CDNC_UART_CTRL_REG_STOPBRK); 295 296 /* Set DTR and RTS. */ 297 WR4(bas, CDNC_UART_MODEM_CTRL_REG, CDNC_UART_MODEM_CTRL_REG_DTR | 298 CDNC_UART_MODEM_CTRL_REG_RTS); 299 } 300 301 /* 302 * Initialize this device for use as a console. 303 */ 304 static void 305 cdnc_uart_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 306 int parity) 307 { 308 309 /* Initialize hardware. */ 310 cdnc_uart_hw_init(bas); 311 312 /* Set baudrate, parameters. */ 313 (void)cdnc_uart_set_params(bas, baudrate, databits, stopbits, parity); 314 } 315 316 /* 317 * Free resources now that we're no longer the console. This appears to 318 * be never called, and I'm unsure quite what to do if I am called. 319 */ 320 static void 321 cdnc_uart_term(struct uart_bas *bas) 322 { 323 324 /* XXX */ 325 } 326 327 /* 328 * Put a character of console output (so we do it here polling rather than 329 * interrupt driven). 330 */ 331 static void 332 cdnc_uart_putc(struct uart_bas *bas, int c) 333 { 334 335 /* Wait for room. */ 336 while ((RD4(bas,CDNC_UART_CHAN_STAT_REG) & 337 CDNC_UART_CHAN_STAT_REG_TXFULL) != 0) 338 ; 339 340 WR4(bas, CDNC_UART_FIFO, c); 341 342 while ((RD4(bas,CDNC_UART_CHAN_STAT_REG) & 343 CDNC_UART_CHAN_STAT_REG_TXEMPTY) == 0) 344 ; 345 } 346 347 /* 348 * Check for a character available. 349 */ 350 static int 351 cdnc_uart_rxready(struct uart_bas *bas) 352 { 353 354 return ((RD4(bas, CDNC_UART_CHAN_STAT_REG) & 355 CDNC_UART_CHAN_STAT_REG_RXEMPTY) == 0); 356 } 357 358 /* 359 * Block waiting for a character. 360 */ 361 static int 362 cdnc_uart_getc(struct uart_bas *bas, struct mtx *mtx) 363 { 364 int c; 365 366 uart_lock(mtx); 367 368 while ((RD4(bas, CDNC_UART_CHAN_STAT_REG) & 369 CDNC_UART_CHAN_STAT_REG_RXEMPTY) != 0) { 370 uart_unlock(mtx); 371 DELAY(4); 372 uart_lock(mtx); 373 } 374 375 c = RD4(bas, CDNC_UART_FIFO); 376 377 uart_unlock(mtx); 378 379 c &= 0xff; 380 return (c); 381 } 382 383 /*****************************************************************************/ 384 /* 385 * High-level UART interface. 386 */ 387 388 static int cdnc_uart_bus_probe(struct uart_softc *sc); 389 static int cdnc_uart_bus_attach(struct uart_softc *sc); 390 static int cdnc_uart_bus_flush(struct uart_softc *, int); 391 static int cdnc_uart_bus_getsig(struct uart_softc *); 392 static int cdnc_uart_bus_ioctl(struct uart_softc *, int, intptr_t); 393 static int cdnc_uart_bus_ipend(struct uart_softc *); 394 static int cdnc_uart_bus_param(struct uart_softc *, int, int, int, int); 395 static int cdnc_uart_bus_receive(struct uart_softc *); 396 static int cdnc_uart_bus_setsig(struct uart_softc *, int); 397 static int cdnc_uart_bus_transmit(struct uart_softc *); 398 static void cdnc_uart_bus_grab(struct uart_softc *); 399 static void cdnc_uart_bus_ungrab(struct uart_softc *); 400 401 static kobj_method_t cdnc_uart_bus_methods[] = { 402 KOBJMETHOD(uart_probe, cdnc_uart_bus_probe), 403 KOBJMETHOD(uart_attach, cdnc_uart_bus_attach), 404 KOBJMETHOD(uart_flush, cdnc_uart_bus_flush), 405 KOBJMETHOD(uart_getsig, cdnc_uart_bus_getsig), 406 KOBJMETHOD(uart_ioctl, cdnc_uart_bus_ioctl), 407 KOBJMETHOD(uart_ipend, cdnc_uart_bus_ipend), 408 KOBJMETHOD(uart_param, cdnc_uart_bus_param), 409 KOBJMETHOD(uart_receive, cdnc_uart_bus_receive), 410 KOBJMETHOD(uart_setsig, cdnc_uart_bus_setsig), 411 KOBJMETHOD(uart_transmit, cdnc_uart_bus_transmit), 412 KOBJMETHOD(uart_grab, cdnc_uart_bus_grab), 413 KOBJMETHOD(uart_ungrab, cdnc_uart_bus_ungrab), 414 415 KOBJMETHOD_END 416 }; 417 418 int 419 cdnc_uart_bus_probe(struct uart_softc *sc) 420 { 421 422 sc->sc_txfifosz = UART_FIFO_SIZE; 423 sc->sc_rxfifosz = UART_FIFO_SIZE; 424 sc->sc_hwiflow = 0; 425 sc->sc_hwoflow = 0; 426 427 device_set_desc(sc->sc_dev, "Cadence UART"); 428 429 return (0); 430 } 431 432 static int 433 cdnc_uart_bus_attach(struct uart_softc *sc) 434 { 435 struct uart_bas *bas = &sc->sc_bas; 436 struct uart_devinfo *di; 437 438 if (sc->sc_sysdev != NULL) { 439 di = sc->sc_sysdev; 440 (void)cdnc_uart_set_params(bas, di->baudrate, di->databits, 441 di->stopbits, di->parity); 442 } else 443 cdnc_uart_hw_init(bas); 444 445 (void)cdnc_uart_bus_getsig(sc); 446 447 /* Enable interrupts. */ 448 WR4(bas, CDNC_UART_IEN_REG, 449 CDNC_UART_INT_RXTRIG | CDNC_UART_INT_RXTMOUT | 450 CDNC_UART_INT_TXOVR | CDNC_UART_INT_RXOVR | 451 CDNC_UART_INT_DMSI); 452 453 return (0); 454 } 455 456 static int 457 cdnc_uart_bus_transmit(struct uart_softc *sc) 458 { 459 int i; 460 struct uart_bas *bas = &sc->sc_bas; 461 462 uart_lock(sc->sc_hwmtx); 463 464 /* Clear sticky TXEMPTY status bit. */ 465 WR4(bas, CDNC_UART_ISTAT_REG, CDNC_UART_INT_TXEMPTY); 466 467 for (i = 0; i < sc->sc_txdatasz; i++) 468 WR4(bas, CDNC_UART_FIFO, sc->sc_txbuf[i]); 469 470 /* Enable TX empty interrupt. */ 471 WR4(bas, CDNC_UART_IEN_REG, CDNC_UART_INT_TXEMPTY); 472 sc->sc_txbusy = 1; 473 474 uart_unlock(sc->sc_hwmtx); 475 476 return (0); 477 } 478 479 static int 480 cdnc_uart_bus_setsig(struct uart_softc *sc, int sig) 481 { 482 struct uart_bas *bas = &sc->sc_bas; 483 uint32_t new, old, modem_ctrl; 484 485 do { 486 old = sc->sc_hwsig; 487 new = old; 488 if (sig & SER_DDTR) { 489 SIGCHG(sig & SER_DTR, new, SER_DTR, SER_DDTR); 490 } 491 if (sig & SER_DRTS) { 492 SIGCHG(sig & SER_RTS, new, SER_RTS, SER_DRTS); 493 } 494 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 495 uart_lock(sc->sc_hwmtx); 496 modem_ctrl = RD4(bas, CDNC_UART_MODEM_CTRL_REG) & 497 ~(CDNC_UART_MODEM_CTRL_REG_DTR | CDNC_UART_MODEM_CTRL_REG_RTS); 498 if ((new & SER_DTR) != 0) 499 modem_ctrl |= CDNC_UART_MODEM_CTRL_REG_DTR; 500 if ((new & SER_RTS) != 0) 501 modem_ctrl |= CDNC_UART_MODEM_CTRL_REG_RTS; 502 WR4(bas, CDNC_UART_MODEM_CTRL_REG, modem_ctrl); 503 504 uart_unlock(sc->sc_hwmtx); 505 return (0); 506 } 507 508 static int 509 cdnc_uart_bus_receive(struct uart_softc *sc) 510 { 511 struct uart_bas *bas = &sc->sc_bas; 512 uint32_t status; 513 int c, c_status = 0; 514 515 uart_lock(sc->sc_hwmtx); 516 517 /* Check for parity or framing errors and clear the status bits. */ 518 status = RD4(bas, CDNC_UART_ISTAT_REG); 519 if ((status & (CDNC_UART_INT_FRAMING | CDNC_UART_INT_PARITY)) != 0) { 520 WR4(bas, CDNC_UART_ISTAT_REG, 521 status & (CDNC_UART_INT_FRAMING | CDNC_UART_INT_PARITY)); 522 if ((status & CDNC_UART_INT_PARITY) != 0) 523 c_status |= UART_STAT_PARERR; 524 if ((status & CDNC_UART_INT_FRAMING) != 0) 525 c_status |= UART_STAT_FRAMERR; 526 } 527 528 while ((RD4(bas, CDNC_UART_CHAN_STAT_REG) & 529 CDNC_UART_CHAN_STAT_REG_RXEMPTY) == 0) { 530 c = RD4(bas, CDNC_UART_FIFO) & 0xff; 531 #ifdef KDB 532 /* Detect break and drop into debugger. */ 533 if (c == 0 && (c_status & UART_STAT_FRAMERR) != 0 && 534 sc->sc_sysdev != NULL && 535 sc->sc_sysdev->type == UART_DEV_CONSOLE) { 536 kdb_break(); 537 WR4(bas, CDNC_UART_ISTAT_REG, CDNC_UART_INT_FRAMING); 538 } 539 #endif 540 uart_rx_put(sc, c | c_status); 541 } 542 543 uart_unlock(sc->sc_hwmtx); 544 545 return (0); 546 } 547 548 static int 549 cdnc_uart_bus_param(struct uart_softc *sc, int baudrate, int databits, 550 int stopbits, int parity) 551 { 552 553 return (cdnc_uart_set_params(&sc->sc_bas, baudrate, 554 databits, stopbits, parity)); 555 } 556 557 static int 558 cdnc_uart_bus_ipend(struct uart_softc *sc) 559 { 560 int ipend = 0; 561 struct uart_bas *bas = &sc->sc_bas; 562 uint32_t istatus; 563 564 uart_lock(sc->sc_hwmtx); 565 566 istatus = RD4(bas, CDNC_UART_ISTAT_REG); 567 568 /* Clear interrupt bits. */ 569 WR4(bas, CDNC_UART_ISTAT_REG, istatus & 570 (CDNC_UART_INT_RXTRIG | CDNC_UART_INT_RXTMOUT | 571 CDNC_UART_INT_TXOVR | CDNC_UART_INT_RXOVR | 572 CDNC_UART_INT_TXEMPTY | CDNC_UART_INT_DMSI)); 573 574 /* Receive data. */ 575 if ((istatus & (CDNC_UART_INT_RXTRIG | CDNC_UART_INT_RXTMOUT)) != 0) 576 ipend |= SER_INT_RXREADY; 577 578 /* Transmit fifo empty. */ 579 if (sc->sc_txbusy && (istatus & CDNC_UART_INT_TXEMPTY) != 0) { 580 /* disable txempty interrupt. */ 581 WR4(bas, CDNC_UART_IDIS_REG, CDNC_UART_INT_TXEMPTY); 582 ipend |= SER_INT_TXIDLE; 583 } 584 585 /* TX Overflow. */ 586 if ((istatus & CDNC_UART_INT_TXOVR) != 0) 587 ipend |= SER_INT_OVERRUN; 588 589 /* RX Overflow. */ 590 if ((istatus & CDNC_UART_INT_RXOVR) != 0) 591 ipend |= SER_INT_OVERRUN; 592 593 /* Modem signal change. */ 594 if ((istatus & CDNC_UART_INT_DMSI) != 0) { 595 WR4(bas, CDNC_UART_MODEM_STAT_REG, 596 CDNC_UART_MODEM_STAT_REG_DDCD | 597 CDNC_UART_MODEM_STAT_REG_TERI | 598 CDNC_UART_MODEM_STAT_REG_DDSR | 599 CDNC_UART_MODEM_STAT_REG_DCTS); 600 ipend |= SER_INT_SIGCHG; 601 } 602 603 uart_unlock(sc->sc_hwmtx); 604 return (ipend); 605 } 606 607 static int 608 cdnc_uart_bus_flush(struct uart_softc *sc, int what) 609 { 610 611 return (0); 612 } 613 614 static int 615 cdnc_uart_bus_getsig(struct uart_softc *sc) 616 { 617 struct uart_bas *bas = &sc->sc_bas; 618 uint32_t new, old, sig; 619 uint8_t modem_status; 620 621 do { 622 old = sc->sc_hwsig; 623 sig = old; 624 uart_lock(sc->sc_hwmtx); 625 modem_status = RD4(bas, CDNC_UART_MODEM_STAT_REG); 626 uart_unlock(sc->sc_hwmtx); 627 SIGCHG(modem_status & CDNC_UART_MODEM_STAT_REG_DSR, 628 sig, SER_DSR, SER_DDSR); 629 SIGCHG(modem_status & CDNC_UART_MODEM_STAT_REG_CTS, 630 sig, SER_CTS, SER_DCTS); 631 SIGCHG(modem_status & CDNC_UART_MODEM_STAT_REG_DCD, 632 sig, SER_DCD, SER_DDCD); 633 SIGCHG(modem_status & CDNC_UART_MODEM_STAT_REG_RI, 634 sig, SER_RI, SER_DRI); 635 new = sig & ~SER_MASK_DELTA; 636 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 637 return (sig); 638 } 639 640 static int 641 cdnc_uart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 642 { 643 struct uart_bas *bas = &sc->sc_bas; 644 uint32_t uart_ctrl, modem_ctrl; 645 int error = 0; 646 647 uart_lock(sc->sc_hwmtx); 648 649 switch (request) { 650 case UART_IOCTL_BREAK: 651 uart_ctrl = RD4(bas, CDNC_UART_CTRL_REG); 652 if (data) { 653 uart_ctrl |= CDNC_UART_CTRL_REG_STARTBRK; 654 uart_ctrl &= ~CDNC_UART_CTRL_REG_STOPBRK; 655 } else { 656 uart_ctrl |= CDNC_UART_CTRL_REG_STOPBRK; 657 uart_ctrl &= ~CDNC_UART_CTRL_REG_STARTBRK; 658 } 659 WR4(bas, CDNC_UART_CTRL_REG, uart_ctrl); 660 break; 661 case UART_IOCTL_IFLOW: 662 modem_ctrl = RD4(bas, CDNC_UART_MODEM_CTRL_REG); 663 if (data) 664 modem_ctrl |= CDNC_UART_MODEM_CTRL_REG_RTS; 665 else 666 modem_ctrl &= ~CDNC_UART_MODEM_CTRL_REG_RTS; 667 WR4(bas, CDNC_UART_MODEM_CTRL_REG, modem_ctrl); 668 break; 669 default: 670 error = EINVAL; 671 break; 672 } 673 674 uart_unlock(sc->sc_hwmtx); 675 676 return (error); 677 } 678 679 static void 680 cdnc_uart_bus_grab(struct uart_softc *sc) 681 { 682 683 /* Enable interrupts. */ 684 WR4(&sc->sc_bas, CDNC_UART_IEN_REG, 685 CDNC_UART_INT_TXOVR | CDNC_UART_INT_RXOVR | 686 CDNC_UART_INT_DMSI); 687 } 688 689 static void 690 cdnc_uart_bus_ungrab(struct uart_softc *sc) 691 { 692 693 /* Enable interrupts. */ 694 WR4(&sc->sc_bas, CDNC_UART_IEN_REG, 695 CDNC_UART_INT_RXTRIG | CDNC_UART_INT_RXTMOUT | 696 CDNC_UART_INT_TXOVR | CDNC_UART_INT_RXOVR | 697 CDNC_UART_INT_DMSI); 698 } 699 700 static struct uart_class uart_cdnc_class = { 701 "cdnc_uart", 702 cdnc_uart_bus_methods, 703 sizeof(struct uart_softc), 704 .uc_ops = &cdnc_uart_ops, 705 .uc_range = 8 706 }; 707 708 static struct ofw_compat_data compat_data[] = { 709 {"cadence,uart", (uintptr_t)&uart_cdnc_class}, 710 {"cdns,uart-r1p12", (uintptr_t)&uart_cdnc_class}, 711 {"xlnx,xuartps", (uintptr_t)&uart_cdnc_class}, 712 {NULL, (uintptr_t)NULL}, 713 }; 714 UART_FDT_CLASS_AND_DEVICE(compat_data); 715