1 /*- 2 * Copyright (c) 2005 M. Warner Losh 3 * Copyright (c) 2005 Olivier Houchard 4 * Copyright (c) 2012 Thomas Skibo 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* A driver for the Cadence AMBA UART as used by the Xilinx Zynq-7000. 31 * 32 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual. 33 * (v1.4) November 16, 2012. Xilinx doc UG585. UART is covered in Ch. 19 34 * and register definitions are in appendix B.33. 35 */ 36 37 38 #include <sys/cdefs.h> 39 __FBSDID("$FreeBSD$"); 40 41 #include "opt_global.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/bus.h> 46 #include <sys/conf.h> 47 #include <sys/cons.h> 48 #include <sys/tty.h> 49 #include <machine/bus.h> 50 51 #include <dev/uart/uart.h> 52 #include <dev/uart/uart_cpu.h> 53 #include <dev/uart/uart_bus.h> 54 55 #include "uart_if.h" 56 57 #define UART_FIFO_SIZE 64 58 59 #define RD4(bas, reg) \ 60 bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs((bas), (reg))) 61 #define WR4(bas, reg, value) \ 62 bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs((bas), (reg)), \ 63 (value)) 64 65 /* Register definitions for Cadence UART Controller. 66 */ 67 #define CDNC_UART_CTRL_REG 0x00 /* Control Register. */ 68 #define CDNC_UART_CTRL_REG_STOPBRK (1<<8) 69 #define CDNC_UART_CTRL_REG_STARTBRK (1<<7) 70 #define CDNC_UART_CTRL_REG_TORST (1<<6) 71 #define CDNC_UART_CTRL_REG_TX_DIS (1<<5) 72 #define CDNC_UART_CTRL_REG_TX_EN (1<<4) 73 #define CDNC_UART_CTRL_REG_RX_DIS (1<<3) 74 #define CDNC_UART_CTRL_REG_RX_EN (1<<2) 75 #define CDNC_UART_CTRL_REG_TXRST (1<<1) 76 #define CDNC_UART_CTRL_REG_RXRST (1<<0) 77 78 #define CDNC_UART_MODE_REG 0x04 /* Mode Register. */ 79 #define CDNC_UART_MODE_REG_CHMOD_R_LOOP (3<<8) /* [9:8] - channel mode */ 80 #define CDNC_UART_MODE_REG_CHMOD_L_LOOP (2<<8) 81 #define CDNC_UART_MODE_REG_CHMOD_AUTECHO (1<<8) 82 #define CDNC_UART_MODE_REG_STOP2 (2<<6) /* [7:6] - stop bits */ 83 #define CDNC_UART_MODE_REG_PAR_NONE (4<<3) /* [5:3] - parity type */ 84 #define CDNC_UART_MODE_REG_PAR_MARK (3<<3) 85 #define CDNC_UART_MODE_REG_PAR_SPACE (2<<3) 86 #define CDNC_UART_MODE_REG_PAR_ODD (1<<3) 87 #define CDNC_UART_MODE_REG_PAR_EVEN (0<<3) 88 #define CDNC_UART_MODE_REG_6BIT (3<<1) /* [2:1] - character len */ 89 #define CDNC_UART_MODE_REG_7BIT (2<<1) 90 #define CDNC_UART_MODE_REG_8BIT (0<<1) 91 #define CDNC_UART_MODE_REG_CLKSEL (1<<0) 92 93 #define CDNC_UART_IEN_REG 0x08 /* Interrupt registers. */ 94 #define CDNC_UART_IDIS_REG 0x0C 95 #define CDNC_UART_IMASK_REG 0x10 96 #define CDNC_UART_ISTAT_REG 0x14 97 #define CDNC_UART_INT_TXOVR (1<<12) 98 #define CDNC_UART_INT_TXNRLYFUL (1<<11) /* tx "nearly" full */ 99 #define CDNC_UART_INT_TXTRIG (1<<10) 100 #define CDNC_UART_INT_DMSI (1<<9) /* delta modem status */ 101 #define CDNC_UART_INT_RXTMOUT (1<<8) 102 #define CDNC_UART_INT_PARITY (1<<7) 103 #define CDNC_UART_INT_FRAMING (1<<6) 104 #define CDNC_UART_INT_RXOVR (1<<5) 105 #define CDNC_UART_INT_TXFULL (1<<4) 106 #define CDNC_UART_INT_TXEMPTY (1<<3) 107 #define CDNC_UART_INT_RXFULL (1<<2) 108 #define CDNC_UART_INT_RXEMPTY (1<<1) 109 #define CDNC_UART_INT_RXTRIG (1<<0) 110 #define CDNC_UART_INT_ALL 0x1FFF 111 112 #define CDNC_UART_BAUDGEN_REG 0x18 113 #define CDNC_UART_RX_TIMEO_REG 0x1C 114 #define CDNC_UART_RX_WATER_REG 0x20 115 116 #define CDNC_UART_MODEM_CTRL_REG 0x24 117 #define CDNC_UART_MODEM_CTRL_REG_FCM (1<<5) /* automatic flow control */ 118 #define CDNC_UART_MODEM_CTRL_REG_RTS (1<<1) 119 #define CDNC_UART_MODEM_CTRL_REG_DTR (1<<0) 120 121 #define CDNC_UART_MODEM_STAT_REG 0x28 122 #define CDNC_UART_MODEM_STAT_REG_FCMS (1<<8) /* flow control mode (rw) */ 123 #define CDNC_UART_MODEM_STAT_REG_DCD (1<<7) 124 #define CDNC_UART_MODEM_STAT_REG_RI (1<<6) 125 #define CDNC_UART_MODEM_STAT_REG_DSR (1<<5) 126 #define CDNC_UART_MODEM_STAT_REG_CTS (1<<4) 127 #define CDNC_UART_MODEM_STAT_REG_DDCD (1<<3) /* change in DCD (w1tc) */ 128 #define CDNC_UART_MODEM_STAT_REG_TERI (1<<2) /* trail edge ring (w1tc) */ 129 #define CDNC_UART_MODEM_STAT_REG_DDSR (1<<1) /* change in DSR (w1tc) */ 130 #define CDNC_UART_MODEM_STAT_REG_DCTS (1<<0) /* change in CTS (w1tc) */ 131 132 #define CDNC_UART_CHAN_STAT_REG 0x2C /* Channel status register. */ 133 #define CDNC_UART_CHAN_STAT_REG_TXNRLYFUL (1<<14) /* tx "nearly" full */ 134 #define CDNC_UART_CHAN_STAT_REG_TXTRIG (1<<13) 135 #define CDNC_UART_CHAN_STAT_REG_FDELT (1<<12) 136 #define CDNC_UART_CHAN_STAT_REG_TXACTIVE (1<<11) 137 #define CDNC_UART_CHAN_STAT_REG_RXACTIVE (1<<10) 138 #define CDNC_UART_CHAN_STAT_REG_TXFULL (1<<4) 139 #define CDNC_UART_CHAN_STAT_REG_TXEMPTY (1<<3) 140 #define CDNC_UART_CHAN_STAT_REG_RXEMPTY (1<<1) 141 #define CDNC_UART_CHAN_STAT_REG_RXTRIG (1<<0) 142 143 #define CDNC_UART_FIFO 0x30 /* Data FIFO (tx and rx) */ 144 #define CDNC_UART_BAUDDIV_REG 0x34 145 #define CDNC_UART_FLOWDEL_REG 0x38 146 #define CDNC_UART_TX_WATER_REG 0x44 147 148 149 /* 150 * Low-level UART interface. 151 */ 152 static int cdnc_uart_probe(struct uart_bas *bas); 153 static void cdnc_uart_init(struct uart_bas *bas, int, int, int, int); 154 static void cdnc_uart_term(struct uart_bas *bas); 155 static void cdnc_uart_putc(struct uart_bas *bas, int); 156 static int cdnc_uart_rxready(struct uart_bas *bas); 157 static int cdnc_uart_getc(struct uart_bas *bas, struct mtx *mtx); 158 159 extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs; 160 161 static struct uart_ops cdnc_uart_ops = { 162 .probe = cdnc_uart_probe, 163 .init = cdnc_uart_init, 164 .term = cdnc_uart_term, 165 .putc = cdnc_uart_putc, 166 .rxready = cdnc_uart_rxready, 167 .getc = cdnc_uart_getc, 168 }; 169 170 #define SIGCHG(c, i, s, d) \ 171 if (c) { \ 172 i |= (i & s) ? s : s | d; \ 173 } else { \ 174 i = (i & s) ? (i & ~s) | d : i; \ 175 } 176 177 static int 178 cdnc_uart_probe(struct uart_bas *bas) 179 { 180 181 return (0); 182 } 183 184 static int 185 cdnc_uart_set_baud(struct uart_bas *bas, int baudrate) 186 { 187 uint32_t baudgen, bauddiv; 188 uint32_t best_bauddiv, best_baudgen, best_error; 189 uint32_t baud_out, err; 190 191 best_bauddiv = 0; 192 best_baudgen = 0; 193 best_error = ~0; 194 195 /* Try all possible bauddiv values and pick best match. */ 196 for (bauddiv = 4; bauddiv <= 255; bauddiv++) { 197 baudgen = (bas->rclk + (baudrate * (bauddiv + 1)) / 2) / 198 (baudrate * (bauddiv + 1)); 199 if (baudgen < 1 || baudgen > 0xffff) 200 continue; 201 202 baud_out = bas->rclk / (baudgen * (bauddiv + 1)); 203 err = baud_out > baudrate ? 204 baud_out - baudrate : baudrate - baud_out; 205 206 if (err < best_error) { 207 best_error = err; 208 best_bauddiv = bauddiv; 209 best_baudgen = baudgen; 210 } 211 } 212 213 if (best_bauddiv > 0) { 214 WR4(bas, CDNC_UART_BAUDDIV_REG, best_bauddiv); 215 WR4(bas, CDNC_UART_BAUDGEN_REG, best_baudgen); 216 return (0); 217 } else 218 return (-1); /* out of range */ 219 } 220 221 static int 222 cdnc_uart_set_params(struct uart_bas *bas, int baudrate, int databits, 223 int stopbits, int parity) 224 { 225 uint32_t mode_reg_value = 0; 226 227 switch (databits) { 228 case 6: 229 mode_reg_value |= CDNC_UART_MODE_REG_6BIT; 230 break; 231 case 7: 232 mode_reg_value |= CDNC_UART_MODE_REG_7BIT; 233 break; 234 case 8: 235 default: 236 mode_reg_value |= CDNC_UART_MODE_REG_8BIT; 237 break; 238 } 239 240 if (stopbits == 2) 241 mode_reg_value |= CDNC_UART_MODE_REG_STOP2; 242 243 switch (parity) { 244 case UART_PARITY_MARK: 245 mode_reg_value |= CDNC_UART_MODE_REG_PAR_MARK; 246 break; 247 case UART_PARITY_SPACE: 248 mode_reg_value |= CDNC_UART_MODE_REG_PAR_SPACE; 249 break; 250 case UART_PARITY_ODD: 251 mode_reg_value |= CDNC_UART_MODE_REG_PAR_ODD; 252 break; 253 case UART_PARITY_EVEN: 254 mode_reg_value |= CDNC_UART_MODE_REG_PAR_EVEN; 255 break; 256 case UART_PARITY_NONE: 257 default: 258 mode_reg_value |= CDNC_UART_MODE_REG_PAR_NONE; 259 break; 260 } 261 262 WR4(bas, CDNC_UART_MODE_REG, mode_reg_value); 263 264 if (baudrate > 0 && cdnc_uart_set_baud(bas, baudrate) < 0) 265 return (EINVAL); 266 267 return(0); 268 } 269 270 static void 271 cdnc_uart_hw_init(struct uart_bas *bas) 272 { 273 274 /* Reset RX and TX. */ 275 WR4(bas, CDNC_UART_CTRL_REG, 276 CDNC_UART_CTRL_REG_RXRST | CDNC_UART_CTRL_REG_TXRST); 277 278 /* Interrupts all off. */ 279 WR4(bas, CDNC_UART_IDIS_REG, CDNC_UART_INT_ALL); 280 WR4(bas, CDNC_UART_ISTAT_REG, CDNC_UART_INT_ALL); 281 282 /* Clear delta bits. */ 283 WR4(bas, CDNC_UART_MODEM_STAT_REG, 284 CDNC_UART_MODEM_STAT_REG_DDCD | CDNC_UART_MODEM_STAT_REG_TERI | 285 CDNC_UART_MODEM_STAT_REG_DDSR | CDNC_UART_MODEM_STAT_REG_DCTS); 286 287 /* RX FIFO water level, stale timeout */ 288 WR4(bas, CDNC_UART_RX_WATER_REG, UART_FIFO_SIZE/2); 289 WR4(bas, CDNC_UART_RX_TIMEO_REG, 10); 290 291 /* TX FIFO water level (not used.) */ 292 WR4(bas, CDNC_UART_TX_WATER_REG, UART_FIFO_SIZE/2); 293 294 /* Bring RX and TX online. */ 295 WR4(bas, CDNC_UART_CTRL_REG, 296 CDNC_UART_CTRL_REG_RX_EN | CDNC_UART_CTRL_REG_TX_EN | 297 CDNC_UART_CTRL_REG_TORST | CDNC_UART_CTRL_REG_STOPBRK); 298 299 /* Set DTR and RTS. */ 300 WR4(bas, CDNC_UART_MODEM_CTRL_REG, CDNC_UART_MODEM_CTRL_REG_DTR | 301 CDNC_UART_MODEM_CTRL_REG_RTS); 302 } 303 304 /* 305 * Initialize this device for use as a console. 306 */ 307 static void 308 cdnc_uart_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 309 int parity) 310 { 311 312 /* Initialize hardware. */ 313 cdnc_uart_hw_init(bas); 314 315 /* Set baudrate, parameters. */ 316 (void)cdnc_uart_set_params(bas, baudrate, databits, stopbits, parity); 317 } 318 319 /* 320 * Free resources now that we're no longer the console. This appears to 321 * be never called, and I'm unsure quite what to do if I am called. 322 */ 323 static void 324 cdnc_uart_term(struct uart_bas *bas) 325 { 326 327 /* XXX */ 328 } 329 330 /* 331 * Put a character of console output (so we do it here polling rather than 332 * interrutp driven). 333 */ 334 static void 335 cdnc_uart_putc(struct uart_bas *bas, int c) 336 { 337 338 /* Wait for room. */ 339 while ((RD4(bas,CDNC_UART_CHAN_STAT_REG) & 340 CDNC_UART_CHAN_STAT_REG_TXFULL) != 0) 341 ; 342 343 WR4(bas, CDNC_UART_FIFO, c); 344 345 while ((RD4(bas,CDNC_UART_CHAN_STAT_REG) & 346 CDNC_UART_CHAN_STAT_REG_TXEMPTY) == 0) 347 ; 348 } 349 350 /* 351 * Check for a character available. 352 */ 353 static int 354 cdnc_uart_rxready(struct uart_bas *bas) 355 { 356 357 return ((RD4(bas, CDNC_UART_CHAN_STAT_REG) & 358 CDNC_UART_CHAN_STAT_REG_RXEMPTY) == 0); 359 } 360 361 /* 362 * Block waiting for a character. 363 */ 364 static int 365 cdnc_uart_getc(struct uart_bas *bas, struct mtx *mtx) 366 { 367 int c; 368 369 uart_lock(mtx); 370 371 while ((RD4(bas, CDNC_UART_CHAN_STAT_REG) & 372 CDNC_UART_CHAN_STAT_REG_RXEMPTY) != 0) { 373 uart_unlock(mtx); 374 DELAY(4); 375 uart_lock(mtx); 376 } 377 378 c = RD4(bas, CDNC_UART_FIFO); 379 380 uart_unlock(mtx); 381 382 c &= 0xff; 383 return (c); 384 } 385 386 /*****************************************************************************/ 387 /* 388 * High-level UART interface. 389 */ 390 391 static int cdnc_uart_bus_probe(struct uart_softc *sc); 392 static int cdnc_uart_bus_attach(struct uart_softc *sc); 393 static int cdnc_uart_bus_flush(struct uart_softc *, int); 394 static int cdnc_uart_bus_getsig(struct uart_softc *); 395 static int cdnc_uart_bus_ioctl(struct uart_softc *, int, intptr_t); 396 static int cdnc_uart_bus_ipend(struct uart_softc *); 397 static int cdnc_uart_bus_param(struct uart_softc *, int, int, int, int); 398 static int cdnc_uart_bus_receive(struct uart_softc *); 399 static int cdnc_uart_bus_setsig(struct uart_softc *, int); 400 static int cdnc_uart_bus_transmit(struct uart_softc *); 401 static void cdnc_uart_bus_grab(struct uart_softc *); 402 static void cdnc_uart_bus_ungrab(struct uart_softc *); 403 404 static kobj_method_t cdnc_uart_bus_methods[] = { 405 KOBJMETHOD(uart_probe, cdnc_uart_bus_probe), 406 KOBJMETHOD(uart_attach, cdnc_uart_bus_attach), 407 KOBJMETHOD(uart_flush, cdnc_uart_bus_flush), 408 KOBJMETHOD(uart_getsig, cdnc_uart_bus_getsig), 409 KOBJMETHOD(uart_ioctl, cdnc_uart_bus_ioctl), 410 KOBJMETHOD(uart_ipend, cdnc_uart_bus_ipend), 411 KOBJMETHOD(uart_param, cdnc_uart_bus_param), 412 KOBJMETHOD(uart_receive, cdnc_uart_bus_receive), 413 KOBJMETHOD(uart_setsig, cdnc_uart_bus_setsig), 414 KOBJMETHOD(uart_transmit, cdnc_uart_bus_transmit), 415 KOBJMETHOD(uart_grab, cdnc_uart_bus_grab), 416 KOBJMETHOD(uart_ungrab, cdnc_uart_bus_ungrab), 417 418 KOBJMETHOD_END 419 }; 420 421 int 422 cdnc_uart_bus_probe(struct uart_softc *sc) 423 { 424 425 sc->sc_txfifosz = UART_FIFO_SIZE; 426 sc->sc_rxfifosz = UART_FIFO_SIZE; 427 sc->sc_hwiflow = 0; 428 sc->sc_hwoflow = 0; 429 430 device_set_desc(sc->sc_dev, "Cadence UART"); 431 432 return (0); 433 } 434 435 static int 436 cdnc_uart_bus_attach(struct uart_softc *sc) 437 { 438 struct uart_bas *bas = &sc->sc_bas; 439 struct uart_devinfo *di; 440 441 if (sc->sc_sysdev != NULL) { 442 di = sc->sc_sysdev; 443 (void)cdnc_uart_set_params(bas, di->baudrate, di->databits, 444 di->stopbits, di->parity); 445 } else 446 cdnc_uart_hw_init(bas); 447 448 (void)cdnc_uart_bus_getsig(sc); 449 450 /* Enable interrupts. */ 451 WR4(bas, CDNC_UART_IEN_REG, 452 CDNC_UART_INT_RXTRIG | CDNC_UART_INT_RXTMOUT | 453 CDNC_UART_INT_TXOVR | CDNC_UART_INT_RXOVR | 454 CDNC_UART_INT_DMSI); 455 456 return (0); 457 } 458 459 static int 460 cdnc_uart_bus_transmit(struct uart_softc *sc) 461 { 462 int i; 463 struct uart_bas *bas = &sc->sc_bas; 464 465 uart_lock(sc->sc_hwmtx); 466 467 /* Clear sticky TXEMPTY status bit. */ 468 WR4(bas, CDNC_UART_ISTAT_REG, CDNC_UART_INT_TXEMPTY); 469 470 for (i = 0; i < sc->sc_txdatasz; i++) 471 WR4(bas, CDNC_UART_FIFO, sc->sc_txbuf[i]); 472 473 /* Enable TX empty interrupt. */ 474 WR4(bas, CDNC_UART_IEN_REG, CDNC_UART_INT_TXEMPTY); 475 sc->sc_txbusy = 1; 476 477 uart_unlock(sc->sc_hwmtx); 478 479 return (0); 480 } 481 482 static int 483 cdnc_uart_bus_setsig(struct uart_softc *sc, int sig) 484 { 485 struct uart_bas *bas = &sc->sc_bas; 486 uint32_t new, old, modem_ctrl; 487 488 do { 489 old = sc->sc_hwsig; 490 new = old; 491 if (sig & SER_DDTR) { 492 SIGCHG(sig & SER_DTR, new, SER_DTR, SER_DDTR); 493 } 494 if (sig & SER_DRTS) { 495 SIGCHG(sig & SER_RTS, new, SER_RTS, SER_DRTS); 496 } 497 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 498 uart_lock(sc->sc_hwmtx); 499 modem_ctrl = RD4(bas, CDNC_UART_MODEM_CTRL_REG) & 500 ~(CDNC_UART_MODEM_CTRL_REG_DTR | CDNC_UART_MODEM_CTRL_REG_RTS); 501 if ((new & SER_DTR) != 0) 502 modem_ctrl |= CDNC_UART_MODEM_CTRL_REG_DTR; 503 if ((new & SER_RTS) != 0) 504 modem_ctrl |= CDNC_UART_MODEM_CTRL_REG_RTS; 505 WR4(bas, CDNC_UART_MODEM_CTRL_REG, modem_ctrl); 506 507 uart_unlock(sc->sc_hwmtx); 508 return (0); 509 } 510 511 static int 512 cdnc_uart_bus_receive(struct uart_softc *sc) 513 { 514 struct uart_bas *bas = &sc->sc_bas; 515 uint32_t status; 516 int c, c_status = 0; 517 518 uart_lock(sc->sc_hwmtx); 519 520 /* Check for parity or framing errors and clear the status bits. */ 521 status = RD4(bas, CDNC_UART_ISTAT_REG); 522 if ((status & (CDNC_UART_INT_FRAMING | CDNC_UART_INT_PARITY)) != 0) { 523 WR4(bas, CDNC_UART_ISTAT_REG, 524 status & (CDNC_UART_INT_FRAMING | CDNC_UART_INT_PARITY)); 525 if ((status & CDNC_UART_INT_PARITY) != 0) 526 c_status |= UART_STAT_PARERR; 527 if ((status & CDNC_UART_INT_FRAMING) != 0) 528 c_status |= UART_STAT_FRAMERR; 529 } 530 531 while ((RD4(bas, CDNC_UART_CHAN_STAT_REG) & 532 CDNC_UART_CHAN_STAT_REG_RXEMPTY) == 0) { 533 c = RD4(bas, CDNC_UART_FIFO) & 0xff; 534 #ifdef KDB 535 /* Detect break and drop into debugger. */ 536 if (c == 0 && (c_status & UART_STAT_FRAMERR) != 0 && 537 sc->sc_sysdev != NULL && 538 sc->sc_sysdev->type == UART_DEV_CONSOLE) { 539 kdb_break(); 540 WR4(bas, CDNC_UART_ISTAT_REG, CDNC_UART_INT_FRAMING); 541 } 542 #endif 543 uart_rx_put(sc, c | c_status); 544 } 545 546 uart_unlock(sc->sc_hwmtx); 547 548 return (0); 549 } 550 551 static int 552 cdnc_uart_bus_param(struct uart_softc *sc, int baudrate, int databits, 553 int stopbits, int parity) 554 { 555 556 return (cdnc_uart_set_params(&sc->sc_bas, baudrate, 557 databits, stopbits, parity)); 558 } 559 560 static int 561 cdnc_uart_bus_ipend(struct uart_softc *sc) 562 { 563 int ipend = 0; 564 struct uart_bas *bas = &sc->sc_bas; 565 uint32_t istatus; 566 567 uart_lock(sc->sc_hwmtx); 568 569 istatus = RD4(bas, CDNC_UART_ISTAT_REG); 570 571 /* Clear interrupt bits. */ 572 WR4(bas, CDNC_UART_ISTAT_REG, istatus & 573 (CDNC_UART_INT_RXTRIG | CDNC_UART_INT_RXTMOUT | 574 CDNC_UART_INT_TXOVR | CDNC_UART_INT_RXOVR | 575 CDNC_UART_INT_TXEMPTY | CDNC_UART_INT_DMSI)); 576 577 /* Receive data. */ 578 if ((istatus & (CDNC_UART_INT_RXTRIG | CDNC_UART_INT_RXTMOUT)) != 0) 579 ipend |= SER_INT_RXREADY; 580 581 /* Transmit fifo empty. */ 582 if (sc->sc_txbusy && (istatus & CDNC_UART_INT_TXEMPTY) != 0) { 583 /* disable txempty interrupt. */ 584 WR4(bas, CDNC_UART_IDIS_REG, CDNC_UART_INT_TXEMPTY); 585 ipend |= SER_INT_TXIDLE; 586 } 587 588 /* TX Overflow. */ 589 if ((istatus & CDNC_UART_INT_TXOVR) != 0) 590 ipend |= SER_INT_OVERRUN; 591 592 /* RX Overflow. */ 593 if ((istatus & CDNC_UART_INT_RXOVR) != 0) 594 ipend |= SER_INT_OVERRUN; 595 596 /* Modem signal change. */ 597 if ((istatus & CDNC_UART_INT_DMSI) != 0) { 598 WR4(bas, CDNC_UART_MODEM_STAT_REG, 599 CDNC_UART_MODEM_STAT_REG_DDCD | 600 CDNC_UART_MODEM_STAT_REG_TERI | 601 CDNC_UART_MODEM_STAT_REG_DDSR | 602 CDNC_UART_MODEM_STAT_REG_DCTS); 603 ipend |= SER_INT_SIGCHG; 604 } 605 606 uart_unlock(sc->sc_hwmtx); 607 return (ipend); 608 } 609 610 static int 611 cdnc_uart_bus_flush(struct uart_softc *sc, int what) 612 { 613 614 return (0); 615 } 616 617 static int 618 cdnc_uart_bus_getsig(struct uart_softc *sc) 619 { 620 struct uart_bas *bas = &sc->sc_bas; 621 uint32_t new, old, sig; 622 uint8_t modem_status; 623 624 do { 625 old = sc->sc_hwsig; 626 sig = old; 627 uart_lock(sc->sc_hwmtx); 628 modem_status = RD4(bas, CDNC_UART_MODEM_STAT_REG); 629 uart_unlock(sc->sc_hwmtx); 630 SIGCHG(modem_status & CDNC_UART_MODEM_STAT_REG_DSR, 631 sig, SER_DSR, SER_DDSR); 632 SIGCHG(modem_status & CDNC_UART_MODEM_STAT_REG_CTS, 633 sig, SER_CTS, SER_DCTS); 634 SIGCHG(modem_status & CDNC_UART_MODEM_STAT_REG_DCD, 635 sig, SER_DCD, SER_DDCD); 636 SIGCHG(modem_status & CDNC_UART_MODEM_STAT_REG_RI, 637 sig, SER_RI, SER_DRI); 638 new = sig & ~SER_MASK_DELTA; 639 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 640 return (sig); 641 } 642 643 static int 644 cdnc_uart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 645 { 646 struct uart_bas *bas = &sc->sc_bas; 647 uint32_t uart_ctrl, modem_ctrl; 648 int error = 0; 649 650 uart_lock(sc->sc_hwmtx); 651 652 switch (request) { 653 case UART_IOCTL_BREAK: 654 uart_ctrl = RD4(bas, CDNC_UART_CTRL_REG); 655 if (data) { 656 uart_ctrl |= CDNC_UART_CTRL_REG_STARTBRK; 657 uart_ctrl &= ~CDNC_UART_CTRL_REG_STOPBRK; 658 } else { 659 uart_ctrl |= CDNC_UART_CTRL_REG_STOPBRK; 660 uart_ctrl &= ~CDNC_UART_CTRL_REG_STARTBRK; 661 } 662 WR4(bas, CDNC_UART_CTRL_REG, uart_ctrl); 663 break; 664 case UART_IOCTL_IFLOW: 665 modem_ctrl = RD4(bas, CDNC_UART_MODEM_CTRL_REG); 666 if (data) 667 modem_ctrl |= CDNC_UART_MODEM_CTRL_REG_RTS; 668 else 669 modem_ctrl &= ~CDNC_UART_MODEM_CTRL_REG_RTS; 670 WR4(bas, CDNC_UART_MODEM_CTRL_REG, modem_ctrl); 671 break; 672 default: 673 error = EINVAL; 674 break; 675 } 676 677 uart_unlock(sc->sc_hwmtx); 678 679 return (error); 680 } 681 682 static void 683 cdnc_uart_bus_grab(struct uart_softc *sc) 684 { 685 686 /* Enable interrupts. */ 687 WR4(&sc->sc_bas, CDNC_UART_IEN_REG, 688 CDNC_UART_INT_TXOVR | CDNC_UART_INT_RXOVR | 689 CDNC_UART_INT_DMSI); 690 } 691 692 static void 693 cdnc_uart_bus_ungrab(struct uart_softc *sc) 694 { 695 696 /* Enable interrupts. */ 697 WR4(&sc->sc_bas, CDNC_UART_IEN_REG, 698 CDNC_UART_INT_RXTRIG | CDNC_UART_INT_RXTMOUT | 699 CDNC_UART_INT_TXOVR | CDNC_UART_INT_RXOVR | 700 CDNC_UART_INT_DMSI); 701 } 702 703 struct uart_class uart_cdnc_class = { 704 "cdnc_uart", 705 cdnc_uart_bus_methods, 706 sizeof(struct uart_softc), 707 .uc_ops = &cdnc_uart_ops, 708 .uc_range = 8 709 }; 710