1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011 5 * Ben Gray <ben.r.gray@gmail.com>. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/conf.h> 33 #include <sys/kernel.h> 34 #include <sys/rman.h> 35 #include <sys/module.h> 36 #include <sys/proc.h> 37 #include <sys/condvar.h> 38 39 #include <dev/fdt/simplebus.h> 40 #include <dev/fdt/fdt_common.h> 41 #include <dev/ofw/ofw_bus_subr.h> 42 43 #include <dev/usb/usb.h> 44 #include <dev/usb/usbdi.h> 45 46 #include <dev/usb/usb_core.h> 47 #include <dev/usb/usb_busdma.h> 48 #include <dev/usb/usb_process.h> 49 #include <dev/usb/usb_util.h> 50 51 #include <dev/usb/usb_controller.h> 52 #include <dev/usb/usb_bus.h> 53 #include <dev/usb/controller/ehci.h> 54 #include <dev/usb/controller/ehcireg.h> 55 56 #include <machine/bus.h> 57 58 #include <arm/ti/usb/omap_usb.h> 59 60 #include <arm/ti/omap4/pandaboard/pandaboard.h> 61 62 /* EHCI */ 63 #define OMAP_USBHOST_HCCAPBASE 0x0000 64 #define OMAP_USBHOST_HCSPARAMS 0x0004 65 #define OMAP_USBHOST_HCCPARAMS 0x0008 66 #define OMAP_USBHOST_USBCMD 0x0010 67 #define OMAP_USBHOST_USBSTS 0x0014 68 #define OMAP_USBHOST_USBINTR 0x0018 69 #define OMAP_USBHOST_FRINDEX 0x001C 70 #define OMAP_USBHOST_CTRLDSSEGMENT 0x0020 71 #define OMAP_USBHOST_PERIODICLISTBASE 0x0024 72 #define OMAP_USBHOST_ASYNCLISTADDR 0x0028 73 #define OMAP_USBHOST_CONFIGFLAG 0x0050 74 #define OMAP_USBHOST_PORTSC(i) (0x0054 + (0x04 * (i))) 75 #define OMAP_USBHOST_INSNREG00 0x0090 76 #define OMAP_USBHOST_INSNREG01 0x0094 77 #define OMAP_USBHOST_INSNREG02 0x0098 78 #define OMAP_USBHOST_INSNREG03 0x009C 79 #define OMAP_USBHOST_INSNREG04 0x00A0 80 #define OMAP_USBHOST_INSNREG05_UTMI 0x00A4 81 #define OMAP_USBHOST_INSNREG05_ULPI 0x00A4 82 #define OMAP_USBHOST_INSNREG06 0x00A8 83 #define OMAP_USBHOST_INSNREG07 0x00AC 84 #define OMAP_USBHOST_INSNREG08 0x00B0 85 86 #define OMAP_USBHOST_INSNREG04_DISABLE_UNSUSPEND (1 << 5) 87 88 #define OMAP_USBHOST_INSNREG05_ULPI_CONTROL_SHIFT 31 89 #define OMAP_USBHOST_INSNREG05_ULPI_PORTSEL_SHIFT 24 90 #define OMAP_USBHOST_INSNREG05_ULPI_OPSEL_SHIFT 22 91 #define OMAP_USBHOST_INSNREG05_ULPI_REGADD_SHIFT 16 92 #define OMAP_USBHOST_INSNREG05_ULPI_EXTREGADD_SHIFT 8 93 #define OMAP_USBHOST_INSNREG05_ULPI_WRDATA_SHIFT 0 94 95 #define ULPI_FUNC_CTRL_RESET (1 << 5) 96 97 /*-------------------------------------------------------------------------*/ 98 99 /* 100 * Macros for Set and Clear 101 * See ULPI 1.1 specification to find the registers with Set and Clear offsets 102 */ 103 #define ULPI_SET(a) (a + 1) 104 #define ULPI_CLR(a) (a + 2) 105 106 /*-------------------------------------------------------------------------*/ 107 108 /* 109 * Register Map 110 */ 111 #define ULPI_VENDOR_ID_LOW 0x00 112 #define ULPI_VENDOR_ID_HIGH 0x01 113 #define ULPI_PRODUCT_ID_LOW 0x02 114 #define ULPI_PRODUCT_ID_HIGH 0x03 115 #define ULPI_FUNC_CTRL 0x04 116 #define ULPI_IFC_CTRL 0x07 117 #define ULPI_OTG_CTRL 0x0a 118 #define ULPI_USB_INT_EN_RISE 0x0d 119 #define ULPI_USB_INT_EN_FALL 0x10 120 #define ULPI_USB_INT_STS 0x13 121 #define ULPI_USB_INT_LATCH 0x14 122 #define ULPI_DEBUG 0x15 123 #define ULPI_SCRATCH 0x16 124 125 #define OMAP_EHCI_HC_DEVSTR "TI OMAP USB 2.0 controller" 126 127 struct omap_ehci_softc { 128 ehci_softc_t base; /* storage for EHCI code */ 129 device_t sc_dev; 130 }; 131 132 static device_attach_t omap_ehci_attach; 133 static device_detach_t omap_ehci_detach; 134 135 /** 136 * omap_ehci_read_4 - read a 32-bit value from the EHCI registers 137 * omap_ehci_write_4 - write a 32-bit value from the EHCI registers 138 * @sc: omap ehci device context 139 * @off: byte offset within the register set to read from 140 * @val: the value to write into the register 141 * 142 * 143 * LOCKING: 144 * None 145 * 146 * RETURNS: 147 * nothing in case of write function, if read function returns the value read. 148 */ 149 static inline uint32_t 150 omap_ehci_read_4(struct omap_ehci_softc *sc, bus_size_t off) 151 { 152 return (bus_read_4(sc->base.sc_io_res, off)); 153 } 154 155 static inline void 156 omap_ehci_write_4(struct omap_ehci_softc *sc, bus_size_t off, uint32_t val) 157 { 158 bus_write_4(sc->base.sc_io_res, off, val); 159 } 160 161 /** 162 * omap_ehci_soft_phy_reset - resets the phy using the reset command 163 * @isc: omap ehci device context 164 * @port: port to send the reset over 165 * 166 * 167 * LOCKING: 168 * none 169 * 170 * RETURNS: 171 * nothing 172 */ 173 static void 174 omap_ehci_soft_phy_reset(struct omap_ehci_softc *isc, unsigned int port) 175 { 176 unsigned long timeout = (hz < 10) ? 1 : ((100 * hz) / 1000); 177 uint32_t reg; 178 179 reg = ULPI_FUNC_CTRL_RESET 180 /* FUNCTION_CTRL_SET register */ 181 | (ULPI_SET(ULPI_FUNC_CTRL) << OMAP_USBHOST_INSNREG05_ULPI_REGADD_SHIFT) 182 /* Write */ 183 | (2 << OMAP_USBHOST_INSNREG05_ULPI_OPSEL_SHIFT) 184 /* PORTn */ 185 | ((port + 1) << OMAP_USBHOST_INSNREG05_ULPI_PORTSEL_SHIFT) 186 /* start ULPI access*/ 187 | (1 << OMAP_USBHOST_INSNREG05_ULPI_CONTROL_SHIFT); 188 189 omap_ehci_write_4(isc, OMAP_USBHOST_INSNREG05_ULPI, reg); 190 191 /* Wait for ULPI access completion */ 192 while ((omap_ehci_read_4(isc, OMAP_USBHOST_INSNREG05_ULPI) 193 & (1 << OMAP_USBHOST_INSNREG05_ULPI_CONTROL_SHIFT))) { 194 /* Sleep for a tick */ 195 pause("USBPHY_RESET", 1); 196 197 if (timeout-- == 0) { 198 device_printf(isc->sc_dev, "PHY reset operation timed out\n"); 199 break; 200 } 201 } 202 } 203 204 /** 205 * omap_ehci_init - initialises the USB host EHCI controller 206 * @isc: omap ehci device context 207 * 208 * This initialisation routine is quite heavily based on the work done by the 209 * OMAP Linux team (for which I thank them very much). The init sequence is 210 * almost identical, diverging only for the FreeBSD specifics. 211 * 212 * LOCKING: 213 * none 214 * 215 * RETURNS: 216 * 0 on success, a negative error code on failure. 217 */ 218 static int 219 omap_ehci_init(struct omap_ehci_softc *isc) 220 { 221 uint32_t reg = 0; 222 int i; 223 device_t uhh_dev; 224 225 uhh_dev = device_get_parent(isc->sc_dev); 226 device_printf(isc->sc_dev, "Starting TI EHCI USB Controller\n"); 227 228 /* Set the interrupt threshold control, it controls the maximum rate at 229 * which the host controller issues interrupts. We set it to 1 microframe 230 * at startup - the default is 8 mircoframes (equates to 1ms). 231 */ 232 reg = omap_ehci_read_4(isc, OMAP_USBHOST_USBCMD); 233 reg &= 0xff00ffff; 234 reg |= (1 << 16); 235 omap_ehci_write_4(isc, OMAP_USBHOST_USBCMD, reg); 236 237 /* Soft reset the PHY using PHY reset command over ULPI */ 238 for (i = 0; i < OMAP_HS_USB_PORTS; i++) { 239 if (omap_usb_port_mode(uhh_dev, i) == EHCI_HCD_OMAP_MODE_PHY) 240 omap_ehci_soft_phy_reset(isc, i); 241 } 242 243 return(0); 244 } 245 246 /** 247 * omap_ehci_probe - starts the given command 248 * @dev: 249 * 250 * Effectively boilerplate EHCI resume code. 251 * 252 * LOCKING: 253 * Caller should be holding the OMAP3_MMC lock. 254 * 255 * RETURNS: 256 * EH_HANDLED or EH_NOT_HANDLED 257 */ 258 static int 259 omap_ehci_probe(device_t dev) 260 { 261 if (!ofw_bus_status_okay(dev)) 262 return (ENXIO); 263 264 if (!ofw_bus_is_compatible(dev, "ti,ehci-omap")) 265 return (ENXIO); 266 267 device_set_desc(dev, OMAP_EHCI_HC_DEVSTR); 268 269 return (BUS_PROBE_DEFAULT); 270 } 271 272 /** 273 * omap_ehci_attach - driver entry point, sets up the ECHI controller/driver 274 * @dev: the new device handle 275 * 276 * Sets up bus spaces, interrupt handles, etc for the EHCI controller. It also 277 * parses the resource hints and calls omap_ehci_init() to initialise the 278 * H/W. 279 * 280 * LOCKING: 281 * none 282 * 283 * RETURNS: 284 * 0 on success or a positive error code on failure. 285 */ 286 static int 287 omap_ehci_attach(device_t dev) 288 { 289 struct omap_ehci_softc *isc = device_get_softc(dev); 290 ehci_softc_t *sc = &isc->base; 291 #ifdef SOC_OMAP4 292 phandle_t root; 293 #endif 294 int err; 295 int rid; 296 297 #ifdef SOC_OMAP4 298 /* 299 * If we're running a Pandaboard, run Pandaboard-specific 300 * init code. 301 */ 302 root = OF_finddevice("/"); 303 if (ofw_bus_node_is_compatible(root, "ti,omap4-panda")) 304 pandaboard_usb_hub_init(); 305 #endif 306 307 /* initialise some bus fields */ 308 sc->sc_bus.parent = dev; 309 sc->sc_bus.devices = sc->sc_devices; 310 sc->sc_bus.devices_max = EHCI_MAX_DEVICES; 311 sc->sc_bus.dma_bits = 32; 312 313 sprintf(sc->sc_vendor, "Texas Instruments"); 314 315 /* save the device */ 316 isc->sc_dev = dev; 317 318 /* get all DMA memory */ 319 if (usb_bus_mem_alloc_all(&sc->sc_bus, USB_GET_DMA_TAG(dev), 320 &ehci_iterate_hw_softc)) { 321 return (ENOMEM); 322 } 323 324 /* Allocate resource for the EHCI register set */ 325 rid = 0; 326 sc->sc_io_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); 327 if (!sc->sc_io_res) { 328 device_printf(dev, "Error: Could not map EHCI memory\n"); 329 goto error; 330 } 331 /* Request an interrupt resource */ 332 rid = 0; 333 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE); 334 if (sc->sc_irq_res == NULL) { 335 device_printf(dev, "Error: could not allocate irq\n"); 336 goto error; 337 } 338 339 /* Add this device as a child of the USBus device */ 340 sc->sc_bus.bdev = device_add_child(dev, "usbus", DEVICE_UNIT_ANY); 341 if (!sc->sc_bus.bdev) { 342 device_printf(dev, "Error: could not add USB device\n"); 343 goto error; 344 } 345 346 device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus); 347 device_set_desc(sc->sc_bus.bdev, OMAP_EHCI_HC_DEVSTR); 348 349 /* Initialise the ECHI registers */ 350 err = omap_ehci_init(isc); 351 if (err) { 352 device_printf(dev, "Error: could not setup OMAP EHCI, %d\n", err); 353 goto error; 354 } 355 356 /* Set the tag and size of the register set in the EHCI context */ 357 sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res); 358 sc->sc_io_tag = rman_get_bustag(sc->sc_io_res); 359 sc->sc_io_size = rman_get_size(sc->sc_io_res); 360 361 /* Setup the interrupt */ 362 err = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 363 NULL, (driver_intr_t *)ehci_interrupt, sc, &sc->sc_intr_hdl); 364 if (err) { 365 device_printf(dev, "Error: could not setup irq, %d\n", err); 366 sc->sc_intr_hdl = NULL; 367 goto error; 368 } 369 370 /* Finally we are ready to kick off the ECHI host controller */ 371 err = ehci_init(sc); 372 if (err == 0) { 373 err = device_probe_and_attach(sc->sc_bus.bdev); 374 } 375 if (err) { 376 device_printf(dev, "Error: USB init failed err=%d\n", err); 377 goto error; 378 } 379 380 return (0); 381 382 error: 383 omap_ehci_detach(dev); 384 return (ENXIO); 385 } 386 387 /** 388 * omap_ehci_detach - detach the device and cleanup the driver 389 * @dev: device handle 390 * 391 * Clean-up routine where everything initialised in omap_ehci_attach is 392 * freed and cleaned up. This function calls omap_ehci_fini() to shutdown 393 * the on-chip module. 394 * 395 * LOCKING: 396 * none 397 * 398 * RETURNS: 399 * Always returns 0 (success). 400 */ 401 static int 402 omap_ehci_detach(device_t dev) 403 { 404 struct omap_ehci_softc *isc = device_get_softc(dev); 405 ehci_softc_t *sc = &isc->base; 406 int err; 407 408 /* during module unload there are lots of children leftover */ 409 device_delete_children(dev); 410 411 /* 412 * disable interrupts that might have been switched on in ehci_init 413 */ 414 if (sc->sc_io_res) { 415 EWRITE4(sc, EHCI_USBINTR, 0); 416 } 417 418 if (sc->sc_irq_res && sc->sc_intr_hdl) { 419 /* 420 * only call ehci_detach() after ehci_init() 421 */ 422 ehci_detach(sc); 423 424 err = bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intr_hdl); 425 if (err) 426 device_printf(dev, "Error: could not tear down irq, %d\n", err); 427 sc->sc_intr_hdl = NULL; 428 } 429 430 /* Free the resources stored in the base EHCI handler */ 431 if (sc->sc_irq_res) { 432 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 433 sc->sc_irq_res = NULL; 434 } 435 if (sc->sc_io_res) { 436 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_io_res); 437 sc->sc_io_res = NULL; 438 } 439 440 return (0); 441 } 442 443 static device_method_t ehci_methods[] = { 444 /* Device interface */ 445 DEVMETHOD(device_probe, omap_ehci_probe), 446 DEVMETHOD(device_attach, omap_ehci_attach), 447 DEVMETHOD(device_detach, omap_ehci_detach), 448 449 DEVMETHOD(device_suspend, bus_generic_suspend), 450 DEVMETHOD(device_resume, bus_generic_resume), 451 DEVMETHOD(device_shutdown, bus_generic_shutdown), 452 453 /* Bus interface */ 454 DEVMETHOD(bus_print_child, bus_generic_print_child), 455 {0, 0} 456 }; 457 458 static driver_t ehci_driver = { 459 "ehci", 460 ehci_methods, 461 sizeof(struct omap_ehci_softc), 462 }; 463 464 DRIVER_MODULE(omap_ehci, omap_uhh, ehci_driver, 0, 0); 465