1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 5 * Ben Gray <ben.r.gray@gmail.com>. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/conf.h> 35 #include <sys/kernel.h> 36 #include <sys/rman.h> 37 #include <sys/module.h> 38 #include <sys/proc.h> 39 #include <sys/condvar.h> 40 41 #include <dev/fdt/simplebus.h> 42 #include <dev/fdt/fdt_common.h> 43 #include <dev/ofw/ofw_bus_subr.h> 44 45 #include <dev/usb/usb.h> 46 #include <dev/usb/usbdi.h> 47 48 #include <dev/usb/usb_core.h> 49 #include <dev/usb/usb_busdma.h> 50 #include <dev/usb/usb_process.h> 51 #include <dev/usb/usb_util.h> 52 53 #include <dev/usb/usb_controller.h> 54 #include <dev/usb/usb_bus.h> 55 #include <dev/usb/controller/ehci.h> 56 #include <dev/usb/controller/ehcireg.h> 57 58 #include <machine/bus.h> 59 60 #include <arm/ti/ti_prcm.h> 61 #include <arm/ti/usb/omap_usb.h> 62 63 #include <arm/ti/omap4/pandaboard/pandaboard.h> 64 65 /* EHCI */ 66 #define OMAP_USBHOST_HCCAPBASE 0x0000 67 #define OMAP_USBHOST_HCSPARAMS 0x0004 68 #define OMAP_USBHOST_HCCPARAMS 0x0008 69 #define OMAP_USBHOST_USBCMD 0x0010 70 #define OMAP_USBHOST_USBSTS 0x0014 71 #define OMAP_USBHOST_USBINTR 0x0018 72 #define OMAP_USBHOST_FRINDEX 0x001C 73 #define OMAP_USBHOST_CTRLDSSEGMENT 0x0020 74 #define OMAP_USBHOST_PERIODICLISTBASE 0x0024 75 #define OMAP_USBHOST_ASYNCLISTADDR 0x0028 76 #define OMAP_USBHOST_CONFIGFLAG 0x0050 77 #define OMAP_USBHOST_PORTSC(i) (0x0054 + (0x04 * (i))) 78 #define OMAP_USBHOST_INSNREG00 0x0090 79 #define OMAP_USBHOST_INSNREG01 0x0094 80 #define OMAP_USBHOST_INSNREG02 0x0098 81 #define OMAP_USBHOST_INSNREG03 0x009C 82 #define OMAP_USBHOST_INSNREG04 0x00A0 83 #define OMAP_USBHOST_INSNREG05_UTMI 0x00A4 84 #define OMAP_USBHOST_INSNREG05_ULPI 0x00A4 85 #define OMAP_USBHOST_INSNREG06 0x00A8 86 #define OMAP_USBHOST_INSNREG07 0x00AC 87 #define OMAP_USBHOST_INSNREG08 0x00B0 88 89 #define OMAP_USBHOST_INSNREG04_DISABLE_UNSUSPEND (1 << 5) 90 91 #define OMAP_USBHOST_INSNREG05_ULPI_CONTROL_SHIFT 31 92 #define OMAP_USBHOST_INSNREG05_ULPI_PORTSEL_SHIFT 24 93 #define OMAP_USBHOST_INSNREG05_ULPI_OPSEL_SHIFT 22 94 #define OMAP_USBHOST_INSNREG05_ULPI_REGADD_SHIFT 16 95 #define OMAP_USBHOST_INSNREG05_ULPI_EXTREGADD_SHIFT 8 96 #define OMAP_USBHOST_INSNREG05_ULPI_WRDATA_SHIFT 0 97 98 #define ULPI_FUNC_CTRL_RESET (1 << 5) 99 100 /*-------------------------------------------------------------------------*/ 101 102 /* 103 * Macros for Set and Clear 104 * See ULPI 1.1 specification to find the registers with Set and Clear offsets 105 */ 106 #define ULPI_SET(a) (a + 1) 107 #define ULPI_CLR(a) (a + 2) 108 109 /*-------------------------------------------------------------------------*/ 110 111 /* 112 * Register Map 113 */ 114 #define ULPI_VENDOR_ID_LOW 0x00 115 #define ULPI_VENDOR_ID_HIGH 0x01 116 #define ULPI_PRODUCT_ID_LOW 0x02 117 #define ULPI_PRODUCT_ID_HIGH 0x03 118 #define ULPI_FUNC_CTRL 0x04 119 #define ULPI_IFC_CTRL 0x07 120 #define ULPI_OTG_CTRL 0x0a 121 #define ULPI_USB_INT_EN_RISE 0x0d 122 #define ULPI_USB_INT_EN_FALL 0x10 123 #define ULPI_USB_INT_STS 0x13 124 #define ULPI_USB_INT_LATCH 0x14 125 #define ULPI_DEBUG 0x15 126 #define ULPI_SCRATCH 0x16 127 128 #define OMAP_EHCI_HC_DEVSTR "TI OMAP USB 2.0 controller" 129 130 struct omap_ehci_softc { 131 ehci_softc_t base; /* storage for EHCI code */ 132 device_t sc_dev; 133 }; 134 135 static device_attach_t omap_ehci_attach; 136 static device_detach_t omap_ehci_detach; 137 138 /** 139 * omap_ehci_read_4 - read a 32-bit value from the EHCI registers 140 * omap_ehci_write_4 - write a 32-bit value from the EHCI registers 141 * @sc: omap ehci device context 142 * @off: byte offset within the register set to read from 143 * @val: the value to write into the register 144 * 145 * 146 * LOCKING: 147 * None 148 * 149 * RETURNS: 150 * nothing in case of write function, if read function returns the value read. 151 */ 152 static inline uint32_t 153 omap_ehci_read_4(struct omap_ehci_softc *sc, bus_size_t off) 154 { 155 return (bus_read_4(sc->base.sc_io_res, off)); 156 } 157 158 static inline void 159 omap_ehci_write_4(struct omap_ehci_softc *sc, bus_size_t off, uint32_t val) 160 { 161 bus_write_4(sc->base.sc_io_res, off, val); 162 } 163 164 /** 165 * omap_ehci_soft_phy_reset - resets the phy using the reset command 166 * @isc: omap ehci device context 167 * @port: port to send the reset over 168 * 169 * 170 * LOCKING: 171 * none 172 * 173 * RETURNS: 174 * nothing 175 */ 176 static void 177 omap_ehci_soft_phy_reset(struct omap_ehci_softc *isc, unsigned int port) 178 { 179 unsigned long timeout = (hz < 10) ? 1 : ((100 * hz) / 1000); 180 uint32_t reg; 181 182 reg = ULPI_FUNC_CTRL_RESET 183 /* FUNCTION_CTRL_SET register */ 184 | (ULPI_SET(ULPI_FUNC_CTRL) << OMAP_USBHOST_INSNREG05_ULPI_REGADD_SHIFT) 185 /* Write */ 186 | (2 << OMAP_USBHOST_INSNREG05_ULPI_OPSEL_SHIFT) 187 /* PORTn */ 188 | ((port + 1) << OMAP_USBHOST_INSNREG05_ULPI_PORTSEL_SHIFT) 189 /* start ULPI access*/ 190 | (1 << OMAP_USBHOST_INSNREG05_ULPI_CONTROL_SHIFT); 191 192 omap_ehci_write_4(isc, OMAP_USBHOST_INSNREG05_ULPI, reg); 193 194 /* Wait for ULPI access completion */ 195 while ((omap_ehci_read_4(isc, OMAP_USBHOST_INSNREG05_ULPI) 196 & (1 << OMAP_USBHOST_INSNREG05_ULPI_CONTROL_SHIFT))) { 197 198 /* Sleep for a tick */ 199 pause("USBPHY_RESET", 1); 200 201 if (timeout-- == 0) { 202 device_printf(isc->sc_dev, "PHY reset operation timed out\n"); 203 break; 204 } 205 } 206 } 207 208 /** 209 * omap_ehci_init - initialises the USB host EHCI controller 210 * @isc: omap ehci device context 211 * 212 * This initialisation routine is quite heavily based on the work done by the 213 * OMAP Linux team (for which I thank them very much). The init sequence is 214 * almost identical, diverging only for the FreeBSD specifics. 215 * 216 * LOCKING: 217 * none 218 * 219 * RETURNS: 220 * 0 on success, a negative error code on failure. 221 */ 222 static int 223 omap_ehci_init(struct omap_ehci_softc *isc) 224 { 225 uint32_t reg = 0; 226 int i; 227 device_t uhh_dev; 228 229 uhh_dev = device_get_parent(isc->sc_dev); 230 device_printf(isc->sc_dev, "Starting TI EHCI USB Controller\n"); 231 232 /* Set the interrupt threshold control, it controls the maximum rate at 233 * which the host controller issues interrupts. We set it to 1 microframe 234 * at startup - the default is 8 mircoframes (equates to 1ms). 235 */ 236 reg = omap_ehci_read_4(isc, OMAP_USBHOST_USBCMD); 237 reg &= 0xff00ffff; 238 reg |= (1 << 16); 239 omap_ehci_write_4(isc, OMAP_USBHOST_USBCMD, reg); 240 241 /* Soft reset the PHY using PHY reset command over ULPI */ 242 for (i = 0; i < OMAP_HS_USB_PORTS; i++) { 243 if (omap_usb_port_mode(uhh_dev, i) == EHCI_HCD_OMAP_MODE_PHY) 244 omap_ehci_soft_phy_reset(isc, i); 245 246 } 247 248 return(0); 249 } 250 251 /** 252 * omap_ehci_probe - starts the given command 253 * @dev: 254 * 255 * Effectively boilerplate EHCI resume code. 256 * 257 * LOCKING: 258 * Caller should be holding the OMAP3_MMC lock. 259 * 260 * RETURNS: 261 * EH_HANDLED or EH_NOT_HANDLED 262 */ 263 static int 264 omap_ehci_probe(device_t dev) 265 { 266 if (!ofw_bus_status_okay(dev)) 267 return (ENXIO); 268 269 if (!ofw_bus_is_compatible(dev, "ti,ehci-omap")) 270 return (ENXIO); 271 272 device_set_desc(dev, OMAP_EHCI_HC_DEVSTR); 273 274 return (BUS_PROBE_DEFAULT); 275 } 276 277 /** 278 * omap_ehci_attach - driver entry point, sets up the ECHI controller/driver 279 * @dev: the new device handle 280 * 281 * Sets up bus spaces, interrupt handles, etc for the EHCI controller. It also 282 * parses the resource hints and calls omap_ehci_init() to initialise the 283 * H/W. 284 * 285 * LOCKING: 286 * none 287 * 288 * RETURNS: 289 * 0 on success or a positive error code on failure. 290 */ 291 static int 292 omap_ehci_attach(device_t dev) 293 { 294 struct omap_ehci_softc *isc = device_get_softc(dev); 295 ehci_softc_t *sc = &isc->base; 296 #ifdef SOC_OMAP4 297 phandle_t root; 298 #endif 299 int err; 300 int rid; 301 302 #ifdef SOC_OMAP4 303 /* 304 * If we're running a Pandaboard, run Pandaboard-specific 305 * init code. 306 */ 307 root = OF_finddevice("/"); 308 if (ofw_bus_node_is_compatible(root, "ti,omap4-panda")) 309 pandaboard_usb_hub_init(); 310 #endif 311 312 /* initialise some bus fields */ 313 sc->sc_bus.parent = dev; 314 sc->sc_bus.devices = sc->sc_devices; 315 sc->sc_bus.devices_max = EHCI_MAX_DEVICES; 316 sc->sc_bus.dma_bits = 32; 317 318 sprintf(sc->sc_vendor, "Texas Instruments"); 319 320 /* save the device */ 321 isc->sc_dev = dev; 322 323 /* get all DMA memory */ 324 if (usb_bus_mem_alloc_all(&sc->sc_bus, USB_GET_DMA_TAG(dev), 325 &ehci_iterate_hw_softc)) { 326 return (ENOMEM); 327 } 328 329 /* Allocate resource for the EHCI register set */ 330 rid = 0; 331 sc->sc_io_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); 332 if (!sc->sc_io_res) { 333 device_printf(dev, "Error: Could not map EHCI memory\n"); 334 goto error; 335 } 336 /* Request an interrupt resource */ 337 rid = 0; 338 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE); 339 if (sc->sc_irq_res == NULL) { 340 device_printf(dev, "Error: could not allocate irq\n"); 341 goto error; 342 } 343 344 /* Add this device as a child of the USBus device */ 345 sc->sc_bus.bdev = device_add_child(dev, "usbus", -1); 346 if (!sc->sc_bus.bdev) { 347 device_printf(dev, "Error: could not add USB device\n"); 348 goto error; 349 } 350 351 device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus); 352 device_set_desc(sc->sc_bus.bdev, OMAP_EHCI_HC_DEVSTR); 353 354 /* Initialise the ECHI registers */ 355 err = omap_ehci_init(isc); 356 if (err) { 357 device_printf(dev, "Error: could not setup OMAP EHCI, %d\n", err); 358 goto error; 359 } 360 361 /* Set the tag and size of the register set in the EHCI context */ 362 sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res); 363 sc->sc_io_tag = rman_get_bustag(sc->sc_io_res); 364 sc->sc_io_size = rman_get_size(sc->sc_io_res); 365 366 /* Setup the interrupt */ 367 err = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 368 NULL, (driver_intr_t *)ehci_interrupt, sc, &sc->sc_intr_hdl); 369 if (err) { 370 device_printf(dev, "Error: could not setup irq, %d\n", err); 371 sc->sc_intr_hdl = NULL; 372 goto error; 373 } 374 375 /* Finally we are ready to kick off the ECHI host controller */ 376 err = ehci_init(sc); 377 if (err == 0) { 378 err = device_probe_and_attach(sc->sc_bus.bdev); 379 } 380 if (err) { 381 device_printf(dev, "Error: USB init failed err=%d\n", err); 382 goto error; 383 } 384 385 return (0); 386 387 error: 388 omap_ehci_detach(dev); 389 return (ENXIO); 390 } 391 392 /** 393 * omap_ehci_detach - detach the device and cleanup the driver 394 * @dev: device handle 395 * 396 * Clean-up routine where everything initialised in omap_ehci_attach is 397 * freed and cleaned up. This function calls omap_ehci_fini() to shutdown 398 * the on-chip module. 399 * 400 * LOCKING: 401 * none 402 * 403 * RETURNS: 404 * Always returns 0 (success). 405 */ 406 static int 407 omap_ehci_detach(device_t dev) 408 { 409 struct omap_ehci_softc *isc = device_get_softc(dev); 410 ehci_softc_t *sc = &isc->base; 411 int err; 412 413 /* during module unload there are lots of children leftover */ 414 device_delete_children(dev); 415 416 /* 417 * disable interrupts that might have been switched on in ehci_init 418 */ 419 if (sc->sc_io_res) { 420 EWRITE4(sc, EHCI_USBINTR, 0); 421 } 422 423 if (sc->sc_irq_res && sc->sc_intr_hdl) { 424 /* 425 * only call ehci_detach() after ehci_init() 426 */ 427 ehci_detach(sc); 428 429 err = bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intr_hdl); 430 if (err) 431 device_printf(dev, "Error: could not tear down irq, %d\n", err); 432 sc->sc_intr_hdl = NULL; 433 } 434 435 /* Free the resources stored in the base EHCI handler */ 436 if (sc->sc_irq_res) { 437 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 438 sc->sc_irq_res = NULL; 439 } 440 if (sc->sc_io_res) { 441 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_io_res); 442 sc->sc_io_res = NULL; 443 } 444 445 return (0); 446 } 447 448 static device_method_t ehci_methods[] = { 449 /* Device interface */ 450 DEVMETHOD(device_probe, omap_ehci_probe), 451 DEVMETHOD(device_attach, omap_ehci_attach), 452 DEVMETHOD(device_detach, omap_ehci_detach), 453 454 DEVMETHOD(device_suspend, bus_generic_suspend), 455 DEVMETHOD(device_resume, bus_generic_resume), 456 DEVMETHOD(device_shutdown, bus_generic_shutdown), 457 458 /* Bus interface */ 459 DEVMETHOD(bus_print_child, bus_generic_print_child), 460 461 {0, 0} 462 }; 463 464 static driver_t ehci_driver = { 465 "ehci", 466 ehci_methods, 467 sizeof(struct omap_ehci_softc), 468 }; 469 470 static devclass_t ehci_devclass; 471 472 DRIVER_MODULE(omap_ehci, omap_uhh, ehci_driver, ehci_devclass, 0, 0); 473